V
BE
are forward bias voltage and difference
of forward bias voltages of two bipolar
transistors operating at unequal current
densities and constants a, b are chosen so as to
have zero temperature coefficient. Now,
ln(n)
T
V
BE
V =
(2)
where n is unit number of bipolar devices
connected in parallel to have unequal current
densities. The values of negative and positive
temperature coefficients in Austria micro
systems (AMS) 0.35 m technology are 1.5
mV/C and +0.085 mV/C, respectively.
Fig. 2: Reference Generation.
From the above Figure 2:
( ) ) 3 (
3
R
2
R
1
os
V  ln(n)
T
V
BE2
V (REF)
out
V


.

\

+ + =
V
OS
is input offset voltage of opamp and Q1
and Q2 are two parasitic vertical PNP bipolar
transistors, n is ratio of emitter area of Q1 and
Q2, taken to be 24.
OPERATIONAL AMPLIFIER
DESIGN
The opamp is to be used in the reference
circuit is very important building block, whose
performance impacts the output of the
reference circuit. The opamp having input
Journal of VLSI Design Tools and Technology
Volume 3, Issue 1, ISSN: 2249 474X
__________________________________________________________________________________________
JoVDTT(2013) 17 STM Journals 2013. All Rights Reserved Page 3
common mode voltage around 0.671 V, equals
to forward bias voltage (V
BE
) of the bipolar
transistor (Implemented in standard CMOS
technology) is required in core of the reference
circuit. The gain of the opamp should be high
enough to keep both the node at the same
potential. In bandgap reference circuit,
generally current is derived from reference
voltage therefore, only way in which V
REF
may
depend on power supply is through a finite
power supply rejection ratio (PSRR) of the op
amp [7]. Simultaneously, when the reference
circuits are used in mixed signal circuits like
comparators and data converters, low noise is
also required. The above design constraints
conclude to following considerations:
The gain of the opamp should be more than
70dB.The input common mode requirement
makes it difficult to use NMOS input
differential stage.As the output is taken from
source follower, the low output voltage
prevents to use the cascoded architecture.
Therefore, it leads to use the two stage op
amp.The offset voltage produces by the op
amp may be the limiting factor for the correct
operation of the reference circuit.PSRR and
noise performance of the circuit should be
good enough.Keeping all above considerations
for implementation, authors have taken the
simple two stage opamp architecture and
reduced the input offset voltage, as well as
noise of the opamp. While, other performance
parameters are kept according to requirements.
I nput Offset Reduction
The input offset voltage of the opamp is
contributed by systematic and random offset
voltage. The systematic offset voltage is
introduced due to improper design of the
circuit.
Fig. 3: Two Stage OpAmp.
The systematic offset voltage can be
minimized by choosing the equal current
densities in MN1, MN2 and MN3 as well as
the same transistor length of all above devices
[8, 9]. Therefore, for minimum systematic
offset:
1 2 4
3 3 6
1
2
MN MN MP
MN MN MP
W W W
L L L
W W W
L L L
     
  
\ . \ . \ .
= =
     
  
\ . \ . \ .
(1)
While, the random input offset voltage arises
due to mismatches in device threshold
voltage(Vt) and gain factor between the input
pair, which is the cause of photolithography,
ion implantation, etching and other process
related factors [3, 10, 11]. The random input
offset voltage of the circuit shown in Figure 3
can be expressed as [9]:






.

\


.

\


.

\


.

\


.

\


.

\

+




.

\

+ =

.

\


.

\

MN1,2
L
W
MN1,2
L
W
MP1,2
L
W
MP1,2
L
W
2
MP2
t
V
GS
V
MP1
m
g
MN1
m
g
MP1,2 t
V
MN1,2 t
V
os
V
(2)
Random offset voltage depends upon
mismatch in threshold voltages between
transistors MP1 and MP2, MN1 and MN2,
transconductance ratio of MN1 and MP1 and
mismatches in dimensions of these transistors.
Random input offset voltage itself varies with
temperature; therefore, it is more accurate to
take offset voltage as function of statistical
variation. By Pelgroms device mismatch
model [3, 12]:
V (V )
TH MN1,2
(V V )
TH GS MP1
(V )
TH MN3,4
(V V )
TH GS MN1
os
=
(3)
Where is standard deviation of threshold
voltage. From above simplified equation,
authors conclude that, the overdrive voltages
ratio of MN2 and MP2 also plays an important
role in minimizing the offset voltage. In more
simplified way the above equation takes the
form,
( )
( )
A
VTH
V
os
W L
MP1,2
V Vt
A GS
VTH MP1
V Vt W L
GS MN1,2
MN1
=
+
 

\ .
 

\ .
(4)
High Performance Reference Circuit with Operational Amplifier Rajput et al.
__________________________________________________________________________________________
JoPC(2013) 17 STM Journals 2013. All Rights Reserved Page 4
A
VTH
is threshold area proportionality
dependent parameter, which has the value 9.5
mV m for NMOS and 14.5 mV m for
PMOS in 0.35 m AMS technology [12]. It is
clear that offset voltage depends upon the
device dimensions. Therefore, offset voltage
can be reduced by taking the large dimensions
of devices and choosing the proper ratio of
overdrive voltages of the devices according to
the Eq. (4). In this design, authors have
achieved input offset voltage ( value) up to
892 V.
Noise Minimization
Noise is also unwanted and random parameter
which reduces the performance of the circuit.
The power spectral densities (PSDs) of
thermal and flicker noise coefficients for the
above architecture are described as:
2
2
2
2 2
6 6
2 2 2 2
16
(1
3 2 ( / )
( / )
( / )
)
( / ) ( / )
thermal
n ox DMN
MN
p DMP MP
n DMN MN
n DMN MN n DMN MN
kT
V
C I W L
I W L
I W L
I W L I W L
=
+ +
(5)
and,
2
ker
2
2 2 2 2 6 2
2 2 6 2
( ) [1
( ) 2
( ) ( ) ( ) ( )]
n
flic
n OX
MN MN DMN P DMP
MP DMN MN DMN
KF
V f
C WL MN f
L L I KF I
KFn L I L I
=
+ +
(6)
where
n
and
p
are the carrier motilities, KF
n
and KF
p
are flicker noise coefficients of
NMOS and PMOS, respectively. k, is
Boltzmann Constant and C
OX
is capacitance
per unit area of the gate oxide.
From the Eqs. (5) and (6), authors conclude
that the factors to reduce the noise level in the
circuit are bias current of I
DMN2,
type of pair
used in input, aspect ratios and sizes of the
MOSFET devices used.
The choice of NMOS or PMOS is actually
based on the particular application and
availability of CMOS process for design. To
achieve high power supply rejection,
cascading (MP
3
, MP
5
and MP
4
, MP
6
) has been
done. Authors have simulated opamp for
conventional method and Pelgroms method
and analyzed impact of offset voltage on
reference voltage variation.
The simulated performance of the opamp is
given in the Table 1. The plots of the opamp
simulations are given in Figures 47.
From Figures 47 and from Table 1, it can be
observed that by taking Pelgroms model of
optimization, input offset voltage is much
reduced and other parameters are well within
acceptable range.
Table 1: Simulated Results of OpAmp.
Parameters
Conventional
Method
Pelgroms Method
Mean
Value
()
Standard
Deviatio
n
()
Mean
Value()
Standard
Deviation
()
Gain (dB)
104.27 2.01 96.83 6.11
Phase
Margin (.)
71.41 3.26 54.16 2.88
Unity Gain
Freq. (MHz)
2.89 0.21 3.57 0.163
Input Offset
Voltage(mV)
18.58 1.59 29.48 0.892
Input Noise at DC (V)
at 1 MHz(nV)
2.006
45
0.918
39
PROPOSED BGR CIRCUIT
The proposed bandgap reference circuit is
shown in Figure 4, contains an opamp, core
bandgap, supply independent biasing and a
startup circuit. High gain opamp keeps the
upper nodes of the bipolar transistors Q1and
Q2 at the same voltage level. Q1 is unit
transistor and Q2 is combination of 24 devices
connected in parallel n=8 and 24 are generally
preferred choices from layout point of view,
but for n=8, ratio of R1 and R3 is more
compare to n= 24.
The output of reference voltage is taken from
source of MN4. The source voltage of MN4
and MN6 are same. Transistors MP12, MP8,
MP13, MN6 and MN7 are supply independent
biasing circuit which is biasing opamp and an
extra biasing current can be taken from drain
of MP15. To improve the PSRR extra row of
transistors or cascoding from supply end has
been done.
Journal of VLSI Design Tools and Technology
Volume 3, Issue 1, ISSN: 2249 474X
__________________________________________________________________________________________
JoVDTT(2013) 17 STM Journals 2013. All Rights Reserved Page 5
Fig. 4: Bandgap Reference Circuit.
SIMULATED RESULTS
In order, to ensure the methodology used in
our design, Monte Carlo simulation was done
to include the mismatches. Results are shown
in Figures 56, for operational amplifier and
Figures 79, for bandgap reference circuit.
Monte Carlo Resistor and MOS/Bipolar
Transistor models are used for 1000
simulations. The simulations are carried out on
Cadence tool with AMS 0.35 m CMOS
technology. The simulated mean () value,
standard deviation () and plots are given in
Figure.
Fig. 5: Simulation for OpAmp.
In Figure 5 (13) Monte Carlo simulation
results of gain, phase margin and unity gain
bandwidth are shown. In Figure 6 (14) Input
offset voltage and PSRR at 10 Hz, 1 kHz and 1
MHz are shown.
Fig. 6: Offset Voltage (1) and PSRR (2, 3, 4)
at l0 Hz, 1 KHz and 1 MHz Histogram of Op
Amp.
The reference voltage variations with
temperature and supply voltage for typical
parameters are presented in Figures 7 and 8,
respectively.
Fig. 7: Vref versus Temperature.
Fig. 8: Vref versus Supply Voltage.
Authors have compared the simulation results
of the circuit designed by conventional method
and using low input offset opamp in Table 2.
Using conventional opamp which has more
offset voltage, V
REF
variation and temperature
coefficient are 1.63% and 102.46 ppm/C,
High Performance Reference Circuit with Operational Amplifier Rajput et al.
__________________________________________________________________________________________
JoPC(2013) 17 STM Journals 2013. All Rights Reserved Page 6
respectively. While, using low input offset op
amp, the reference voltage of value 1.219 with
maximum 0.66% variation and temperature
coefficient of 41.99 ppm/C have been
achieved. From the simulated results, authors
have observed that more than 58% of
reference voltage variation and temperature
coefficient have been reduced by carefully
designing the circuit using Pelgroms device
mismatch model. Overall performance and
comparison of circuits designed by traditional
method and improved procedure are given in
Table 2. Monte Carlo simulation results of
improved circuit for reference voltage
variation and PSRR at 10 Hz, 1 KHz, 1 MHz
are shown in Figure 9 (14) respectively.
Fig. 9: Vref vs Temp., PSRR at 10 Hz, 1 KHz
and 1 MHz (14).
Table 2: Simulated Results of Reference Circuit.
Parameter Simulated Value
Traditional
Circuit
Improved
Circuit
Monte Carlo
Mean value() of
Reference
Voltage V
REF
(V)
1.22 1.21916
Standard
Deviation () of
V
REF
(mV)
20.03 8.16
Temperature
Coefficient
(ppm/C)
102.06 41.99
Maximum
Variation of
V
REF
(%)
1.63 0.66
PSRR (dB)
At 10 Hz
At 1 kHz
At 1 MHz
54.27 5.97 103.28 4.97
53.36 4.19 99.99 1.97
16.40 0.713 42.98 0.317
Maximum
Current (A)
100 100
TESTING RESULT
The designed BGR circuit has been fabricated
in AMS 0.35 m CMOS Process through
europractice. The circuit has been tested by
semiconductor characterization chamber
(SCC) for 10% supply voltage variation and
10/ C to 110/ C range. In order, to verify the
tested results the packaged circuit has been
tested in temperature variation chamber.
The fabricated circuit has been tested on 5
dies. The tested results are given as follows:
Fig. 10: Measured Results for Voltage
Reference Variation with Temperature.
Fig.11: Chip MicroPhotograph of BGR
Circuit.
The circuit has been tested for both supply and
temperature variation. The maximum variation
of reference voltage with supply is 0.89%
while, in case of temperature the maximum
variation is 0.31mV and temperature
coefficient 63 ppm/C throughout the
temperature range of 10 to 110C. The total
area of the circuit is 0.45 mm
2
in 0.35 m
CMOS.
CONCLUSION
A bandgap reference circuit has been designed
and simulated successfully in AMS 0.35 m
standard CMOS technology. A low input
Journal of VLSI Design Tools and Technology
Volume 3, Issue 1, ISSN: 2249 474X
__________________________________________________________________________________________
JoVDTT(2013) 17 STM Journals 2013. All Rights Reserved Page 7
offset operational amplifier without trimming
is used in the circuit to upgrade the
performance. Pelgroms device mismatch
model is used in the design of operational
amplifier.
By using low input offset opamp and
carefully designing the reference circuit, an
average 58% reduction in variation of
reference voltage with temperature has been
achieved. The PSRR obtained is 42 dB with
almost negligible standard deviation.
ACKNOWLEDGEMENT
The authors would like to thank to group
members of IC Design Group, CEERI, Pilani
and DIT/MCIT (Government of India) for
hardware and software support through
SMDPII Project at CEERI, Pilani.
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