ANAND INSTITUTE OF HIGHER TECHNOLOGY

DEPARTMENT OF MECHANICAL ENGINEERING

ELECTRONICS AND MICROPROCESSORS (147406)

Question bank
Mr.M.Somasekar,M.E.,Lec

Department of MECHANICAL ENGINEERING (10-14) 147406 EMP

ANAND INSTITUTE OF HIGHER TECHNOLOGY Kazhipattur-603 103 Department of ECE Subject: Electronics and Microprocessors Staff Name: M.Somasekar Designation: Lecturer UNIT-I PART A 1. Rectifier. ( Apr/May 2011 -R2008, Nev/Dec 2010-R2008, Apr/May 2008, Nov/Dec 2005) a) Draw the circuit of Bridge rectifier with input and output wave forms. (Apr/May 2011 ,R2008) Code : 147406 Branch: Mech A&B Semester: IV

b) Define Rectifier

( Nev/Dec 2010 ,R2008)

A device, such as a diode, that converts alternating current to direct current. c) What is a rectifier? Which main electronic device is involved in rectification? (Apr/May 2008) Rectifier is a device used to convert AC signal to DC signal. PN junction diode is the main electronic device used as rectifier d) Define rectification. (Nov/Dec 2005) It is the process of converting AC into pulsating DC is called rectification. 2. Diffusion (Apr/May 2011-R2008, Nov/Dec 2006) a) What is diffusion current (Apr/May 2011,R2008) In a semiconductor material the charge carriers have the tendency to move from the region of higher concentration to that of lower concentration of the same type of charge

Department of MECHANICAL ENGINEERING (10-14) 147406 EMP

carriers. Thus the movement of charge carriers takes place resulting in a current called diffusion current. b) Define the terms: Drift and Diffusion.( Nov/Dec 2006) When an electric field is applied across the semiconductor, the holes move towards the negative terminal of the battery and electrons move towards the positive terminal of the battery. This combined effect causes a current flow in the circuit. This current is called as drift current. Drift current density due to holes (Jp) is given by i Drift current density due to electrons (Jn) is given by Jp = q n n E A concentration gradient exists, if the number of either of electrons or holes is greater in one region of a semiconductor as compared to the rest of the region. The holes and electrons then tend to move from region of higher concentration to the electric current produced due to this process is known as diffusion current. Diffusion current density due to holes is given by Jp = -q Dp (dp / dx). Diffusion current density due to electrons is given by Jn = -q Dn (dn / dx). 3. PN Junction (Nov/Dec 2010-R2008, Apr/may2010, May/Jun 2009) a) What is a PN Junction? (Nov/Dec 2010,R2008) The interface between two regions in a semiconductor crystal which have been treated so that one is a p-type semiconductor and the other is an n-type semiconductor; it contains a permanent dipole charge layer. b) What is avalanche breakdown (Apr/may2010,Nov/Dec 2009) In PN junction diode the avalanche breakdown takes place in lightly doped material. When reverse bias due to collision with valance electron new charge carrier will produce this form a cumulative process and the junction will be breakdown. c) State the law of mass action (Apr/may2010,Nov/Dec 2005) Mass action law state that in a semiconductor the product of the number of holes and the number of electrons is constant and is independent of the amount of donor and acceptor impurity doping n.p=ni2 d) Define the Breakdown voltage in PN Junction. (May/Jun 2009) In reverse biased condition the conduction of PN diode is very low, if the reverse bias voltage increases then the reverse current increases upto certain limit after that diode breakdown will occur and that voltage is called as breakdown voltage. 4. Zener diode (Apr/may2010, Nov/Dec 2007,Apr/May 2005 , Nov/Dec 2003) a) Draw the circuit of Zener voltage regulator. (Apr/may2010) A half wave rectifier having a resistance load of 1 kilo ohm rectifies an alternating voltage of 325v peak value and the diode has a forward resistance of 100 ohm. Calculate its dc power output.

Department of MECHANICAL ENGINEERING (10-14) 147406 EMP

b) Define zener breakdown voltage(Nov/Dec 2007) When a PN junction is heavily doped the depletion region is narrow. Under reverse biased condition the electric field across the depletion layer is very intense. Such an intense field is enough to pull the electrons out of the valance bands of the stable atoms. Such a creation of electron hole pair is called as zerer effect. The voltage when this effect takes place is called as zener breakdown voltage. c) What is meant by Zener breakdown?(Apr/May 2005 & Nov/Dec 2003) Heavy doping of P and N regions, the depletion region width becomes very small for an applied voltage the field across the depletion region becomes very high this is Zener break down. 5. Semi-conductor (Nov/Dec 2009, May/Jun 2009, May/Jun 2007,May 2006 Nov/Dec 2005, Apr/May 2004, Nov/Dec 2003) a) What are the differences between intrinsic and extrinsic semiconductor? (Nov/Dec 2009) Intrinsic Semiconductor 1. Pure type of semiconductor 2. Conduction is less Extrinsic Semiconductor Impure type of semiconductor Conduction is more

b) What are the Intrinsic and Extrinsic semiconductors? (May/Jun 2009) Purest form of semiconductors are called as intrinsic semiconductor, its conduction level is low. Impure semiconductor are called as extrinsic semiconductor its conduction level is high c) What are extrinsic semiconductors (May/Jun 2007) Impure semiconductors are called as extrinsic semiconductors, which has high conduction level. It is formed by adding some doping agent to intrinsic semiconductor. d) Define intrinsic and extrinsic semiconductor?(MAY 2007),(MAY 2006 ) Pure form of semiconductor is intrinsic semiconductor. Impure form of semiconductor is extrinsic semiconductor. e) What is meant by doping? (MAY 2006)

Adding impurities (pentavalent or trivalent) to semiconductor is called doping. d) What is mass action law? (Nov/Dec 2005) Under thermal equilibrium for any semiconductor, the product of the number of holes (n) and the number of electrons (p) is constant and is independent of the amount of donor and

Department of MECHANICAL ENGINEERING (10-14) 147406 EMP

acceptor impurity doping. This relationship is known as mass action law and is given by n*p = ni2 where ni is intrinsic concentration. f) What is the Fermi level in an N type material and a P type material? (Nov/Dec 2005) In an N type semiconductor, the Fermi level will lie below the bottom of the conduction band. It is given by EF = EC kT ln (NC/ND). In a P type semiconductor, the Fermi level will be above the top of the valence band. It is given by EF = EV + kT ln (NV/NA) g) What is meant by carrier lifetime for electrons and holes? (Apr/May 2004) In a pure semiconductor the number of holes is equal to the number of free electrons. Thermal agitation, however, continues to produce new hole-electron pairs while other holeelectron pairs disappear as a result of recombination. On an average, a hole or an electron will exist for recombination. This time is called the mean life time of the hole and electron respectively. Carrier lifetime range from nanoseconds to hundreds of microseconds. h) Write down the expression for drift current density due to holes and electrons. (Nov/Dec 2004) Drift current density due to holes (Jp) is given by Jp = q p p E Drift current density due to electrons (Jn) is given by Jp = q n n E Where q is the charge, p is hole concentration, n is electron concentration, n & p is electron and hole mobility. i) Write the expression for conductivity in an extrinsic semiconductor. (Nov/Dec 2003) The conductivity of a N-type semiconductor is given by N = qnN n ~ q ND n since nN ~ ND The conductivity of a P-type semiconductor is given by p = qPp p ~ q NA p since Pp ~ NA . j) How is P type semiconductor formed? (Nov/Dec 2003) Doping a trivalent type impurities forms P type semiconductor k) What is Einstein relationship for semiconductor? Write down the expression (Nov/Dec 2003) The ratio of diffusion coefficient to mobility of electrons and holes will be equal to the volt equivalent of temperature. This relationship is called Einstein relationship and it is given by Dp/ p = Dn/ n = kT/q = VT. The importance of this relationship is to determine the diffusion coefficiszent of electrons and holes 6. Energy gap (Apr/May 2008, Nov/Dec 2007) a) What is the energy gap? (Apr/May 2008) The gap between the valance band and the conduction band is called as energy gap or forbidden energy gap

Department of MECHANICAL ENGINEERING (10-14) 147406 EMP

b) Draw the energy band diagrams for Ge and Si (Nov/Dec 2007)

Silicon energy band diagram

Ge energy band diagram

c) Draw the energy band diagram for an insulating material. (MAY 2007 MECH)

d) Draw the energy band diagram of N type silicon semiconductor at room temperature. (Apr/May2005 & Nov Dec 2003)

Department of MECHANICAL ENGINEERING (10-14) 147406 EMP

e) Find the speed and kinetic energy of electron after it has moved through a potential difference of 5000Volts. (Apr/May 2004 & Nov/Dec 2003) Speed of electron (v) = (2qV / m) = (2 * 1.6 * 10 -19 * 5000) / 9.1 * 10 -31 = 4.2 * 107 m/sec Kinetic Energy = q * V = 1.6 * 10 -19 * 5000 = 8 * 10 -16 joules = 5000 Ev PART-B

1. Zener diode (Apr/May 2011-R2008,Nov/Dec 2010-R2008, Apr/May 2011-R2008, Apr2010, Nov2009, May 2009, May 2006) a) Designa Zenervoltageregulatorfortheoutputvoltageof5Vandoutput currentof200mA.SupportyouranswerwiththeZenercharacteristics andrelevantcircuitdiagram.( Apr/May 2011-R2008) b) WhatisZenereffect?ExplaintheZenerdiodecharacteristicsandexplain howitisusedasavoltageregulator (Nov/Dec 2010-R2008) c) Designa Zenervoltageregulatorfortheoutputvoltageof5Vandoutput currentof200mA.SupportyouranswerwiththeZenercharacteristics andrelevantcircuitdiagram.( Apr/May 2011-R2008) d) Explain the operation of zener voltage regulator with neat diagrams (10)(Apr2010) e) IS it possible to replace a zener diode with an ordinary rectifier diode? If no, explain the desired characteristics of zener diode (apr 2010) f) How do you obtain voltage regulation using zener diode (6) (Nov2009) g) Explain the zener effect. (4) (Nov2009) h) What is called zener effect? (3)(May 2009) i) How zener diode acts as a voltage regulator? (5) (May 2009) j) Draw the V-I characteristic of a typical Zener Diode and explain Zener breakdown phenomena. (8) (May 2006) 2. Rectifier (Nov/Dec 2010-R2008, Apr 2010, May2009, Nov2009, May 2008, May2007, Nov2007, Nov 2006) a) Sketchandexplaintheoperationofahalfandfull-waverectifier.(Nov/Dec 2010-R2008) b) A half wave rectifier having a resistive load of 1k-ohm rectifies an alternating voltage of 325V peak value and the diode has a forward resistance of 100ohm.Calculate (i) Peak, average and rms value of current (ii) DC power output (iii) AC power output (iv) Efficiency of the rectifier (Apr 2010) c) Explain the working of full wave rectifier with filter. (11) (May2009) d) Explain with neat diagram the operation of full wave rectifier and find the ripple factor. (10) (Nov2009) e) Draw the circuit diagram of full wave rectifier with filter and explain its working with input and output waveforms. (10) (May 2008)
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Department of MECHANICAL ENGINEERING (10-14) 147406 EMP

f) How the voltage regulation is achieved in rectifier circuits? Explain (6) (May 2008) g) Compare in detail half wave and full wave rectifiers. (8) (May2007) h) (i) Discuss with necessary diagrams and waveforms the working of a full wave rectifier. Derive the formula for the average output voltage. (10)(May 2007) i) Explain about the circuitry of (Nov2007) (i) Half wave rectifier (ii) Full wave rectifier and draw its output waveform (Nov2007) j) Explain the characteristics of Full wave rectifier with enough wave forms (8) (Nov 2006) 3. PN junction ( Apr/May 2011-R2008, Apr 2010, May2009, May2008, Nov 2006) a) Explain the operation of open circuited PN junction using the energy bandstructure. ( Apr/May 2011-R2008) b) Draw the energy band structure of open circuited PN junction (6) (Apr 2010) c) Draw and explain the formation of a PN junction and explain the working of the diode under forward and reverse bias conditions (Apr 2010) d) (i) Draw the forward and reverse characteristics of PN diode and explain its operation (12) (Nov 2009) e) What is a PN junction?What happens when PN junction is (May2009) (1)Forward biased (2)Reverse biased. (10) e) What is Barrier potential (3) (May2009) f) What is barrier potential in a P-N junction? What happens to the P-N junction, when it is forward and reverse biased? Draw appropriate diagrams. (10) (May2008) g) Explain the phenomena involved in the breakdown of a PN junction under reverse biased condition. (May2008) h) Explain how ion charges produce internal barrior Voltage Vb in a PN junction by showing its depletion zone. (Nov 2006) 4. Semi-conductor (May2007, Nov 2006) a) Make a detailed classification of solids based on energy band theory. (8) (May2007) b) How are intrinsic and extrinsic semiconductors different? (6) (May2007) c) Briefly explain the following: (nov2007) (i) Intrinsic semiconductors (ii) Extrinsic semiconductors d) Write short notes on the applications of semiconductor diodes. (8) (Nov 2006)

UNIT II PART A

Department of MECHANICAL ENGINEERING (10-14) 147406 EMP

1. Transistor biasing (Nov /Dec 2011 -R2008,MAY 2009, Nov/Dec 2007, Apr/May 2004) a) What are the various types of transistor ,R2008),(MAY 2009), (Nov/Dec 2007) i) ii) iii) iv) Fixed bias Emitter feedback bias. Collector feedback bias. Voltage divider bias. or i) ii) iii) There are three biasing circuits Self bias Fixed bias Collector base bias (Apr/May 2004) biasing circuits?( Nov /Dec 2011

b) What is the need of transistor biasing?

To produce distortion free output in amplifier circuits the supply voltages and resistances n the circuit must be suitably chosen. These voltages and resistances establish a set of D.C voltage and current to operate the transistor in the act region. These voltages and current are called as quietiseent values which determine the operating prints or Q points for the transit or. The process of giving proper supply voltages and resistances for obtaining the desired Q point is called biasing. 2. UJT Transistor ?( Nov /Dec 2011 -R2008, Apr/May 2011-R2008, Apl/May 2010, Nov/Dec 2005, Nov/Dec 2004) a) Mention any two applications of UJT ?( Nov /Dec 2011 ,R2008) i) UJT useful, especially in simple oscillator circuits. ii) large AC current control. iii) In addition to its use as the active device in relaxation oscillators, one of the most important applications of UJTs or PUTs is to trigger thyristors (SCR, TRIAC, etc.).
b) Write the equation governing intrinsic stand-off ratio. (Apr/May 2011 ,R2008)

The PUT equivalent of the unijunction transistor is shown in Figure below. External PUT resistors R1 and R2 replace unijunction transistor internal resistors RB1 and RB2, respectively. These resistors allow the calculation of the intrinsic standoff ratio .

Department of MECHANICAL ENGINEERING (10-14) 147406 EMP

c) Name the regions of UJT V-I characteristics (Apl/May 2010)

There are three operating regions in UJT i) Cutoff region ii) Negative resistance region iii) Saturation region
d) Define intrinsic stand off ratio of an UJT. What is its range? (Nov/Dec 2005) With emitter terminal open, if voltage VBB is applied between two bases, the voltage gradient is established along the N type bar. The voltage drop across RB1 is given by V1 = VBB where = RB1 / (RB1 +RB2) is the intrinsic standoff ratio. The typical value of ranges from 0.56 to 0.75 e) Why does a UJT show negative resistance characteristics?

(Nov/Dec 2005) In the V-I characteristics of UJT, at the peak voltage VP = VBB + V, the diode starts conducting and holes are injected into N layer. Hence, the resistance decreases thereby decreasing emitter voltage VE for the increase in IE. So there is a negative resistance region from peak point P to valley point V.
f) What is inter-base resistance of UJT?

(Nov/Dec 2004)

The total resistance between the base terminals B1 and B2 of UJT is called inter-base resistance RBB. It is given as RBB = RB1 + RB2. 3. BJT (Apr/May 2011- R2008, Apr/May 2010, Nov/Dec 2009, Apl/may 2008, MAY 2007 MECH, Nov/Dec 2005, Nov/Dec 2003) a) Define stability factor for BJT (Apr/May 2011, R2008, Apr/May 2010) A measure of a transistor amplifiers bias stability equale to the rate of change of collector current with respect to reverse saturation current. The stability factor is defined as the rate of change of collector current(IC) with respect to the reverse saturation current (ICO) keeping B and VBE constant
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Department of MECHANICAL ENGINEERING (10-14) 147406 EMP

Stability factor S=IC/ICO b) What is early effect in BJTs? (Apl/May 2010) ( Nov/Dec 2009) When the collector-base voltage is made to increase, it increases the depletion region across the collector base junction, with the result that the effective width of the base terminal decreases. This variation of effective base width by collector base voltage is known as base width modulation (or) early effect c) Write any four differences between BJT and FET. (Nov/Dec 2009) The BJT is a current-controlled device since its output is determined on the input current, while FET is considered as a voltage-controlled device, because it depends on the field effect of the applied voltage. The BJT (Bipolar Junction Transistor) uses both the minority and majority carriers (holes and electrons), while FETs, which are sometimes called unipolar transistors, uses either holes or electrons for conduction. BJTs three terminals are named the base, emitter, and collector, while FETs are named the source, drain, and gate. BJTs are the first type to be commercially massed produced. d) Why transistor is called current controlled device? (Apl/may 2008) A bipolar transistor has base emitter and collector electrodes, and is a current-controlled device (able to deliver a change in output voltage in response to a change in input current) with a low input impedance. This type of transistor is widely used as a amplifier and is also a key component in oscillators, high-speed integrated circuits, and switching circuits. e) Sketch the fixed bias circuit for a BJT. (MAY 2007 MECH)

f) What is early effect? By what other name, it is known? (Nov/Dec 2005) When the collector-base voltage is made to increase, it increases the depletion region across the collector base junction, with the result that the effective width of the base terminal decreases. This variation of effective base width by collector base voltage is known as base width modulation (or) early effect
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Department of MECHANICAL ENGINEERING (10-14) 147406 EMP

g) Define delay time and rise time in the switching characteristics of transistor. (Nov/Dec 2003) Three factors contribute to the delay time 1. When the driving signal is applied to the transistor i/p, non-zero time is required to charge up the emitter junction transition capacitance, so the transistor may be brought from cut-off to active region. 2. even when the transistor has been brought to the point where minority carriers have begin t cross the emitter junction into the base, a time interval is required 3. Some time is required for collector current to raise to 10% of its maximum. Rise time: Rise time are due to the fact that it a base current step is used to saturate the transistor or return to it from saturation to cut-off, the transistor collector current must traverse the active region. 4. Define voltage safety factor of Thyristor (Apl/May 2010) Peak Reverse Voltage: The maximum reverse voltage (cathode positive with respect to anode) that can be applied to an SCR without conduction in the reverse direction, is called the peak reverse voltage (PRV) or peak inverse voltage (PIV) Peak reverse voltage (PRV) is an important consideration while SCR is operating in an AC circuit. During negative half cycle of an supply reverse voltage acts across the SCR and if it exceeds beyond PRV, there may be avalanche breakdown and SCR will get damaged if the current is not limited by the external circuit. Commercially available SCR have PRV rating up to 2.5KV. 5. SCR (MAY 2009, Nov/Dec 2005, Nov/Dec 2004, Nov/Dec 2003) a) Mention any two application of SCR. (MAY 2009) i) Motor speed control ii) Heater control iii) Phase control iv) Relay control b) SCR is made of silicon and not of germanium- Why? (Nov/Dec 2005) As leakage current in silicon is very small compared to germanium, SCRs made of silicon and not of germanium c) Define holding current of a SCR? (Nov/Dec 2003) & (Nov/Dec 2004) This is the value of anode current below which the SCR switches from the on state to the off state. This value increases with decreasing value of IG and is maximum for IG=0

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Department of MECHANICAL ENGINEERING (10-14) 147406 EMP

d) Draw the V-I characteristics of SCR?

(Nov/Dec 2003)

6. Amlifier (Apl/may 2008, MAY 2006 MECH) a) What is a feedback amplifier? (Apl/may 2008) A feedback amplifier is one in which the output signal is sampled and feed back to the input to form an error signal that drives the amplifier. When a fraction of the output of an amplifier is combined with the input feedback exists, if the feedback opposes the original signal, it is negative feedback and if it increases the signal it is positive feedback. b) What are the different specification parameters which are important for the optimal performance of an amplifier (MAY 2006 MECH) i) High gain ii) Low input resistance iii) High output resistance. 7. Write two advantages of negative feedback (May/Jun 2007) i) Higher fidelity (more linear operation) ii) Highly stabilized gain iii) Increased band width iv) Less harmonic distortion v) Less amplitude distortion vi) Reduced noise and less phase distortion FET a) What is pinch of voltage in FET? (Apr/May 2005) When the drain current saturation level is reached, the shape of the depletion regions is such that they appear to pinch off the channel for this reason, the drain source voltage at which ID levels off is designated the pinch-off voltage VP.

8.

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Department of MECHANICAL ENGINEERING (10-14) 147406 EMP

b) What are the two main types of field effect transistors (FET)? Which characteristics of a FET make it superior to the bipolar junction transistor?(May/June 2005) Two main types of field effect transistor are junction field effect transistor and metaloxide semiconductor field effect transistor JFET are much easier to fabricate because they occupy less space than BJT. FET can act as a excellent buffer amplifier but BJT has low i/p impedance. 9. Draw sketches to show the construction of a TRIAC? (Apr/May 2004)

PART B 1. Explain in detail the circuitry of Class-B push pull power amplifier and discuss its merits and demerits. (Nov/Dec 2011-R2008) 2. SCR,TRIAC and DIAC i) Explain the characteristics of SCR TRIAC and DIAC (only the characteristics). (Nov/Dec 2011-R2008) ii) Explain with neat diagram SCR and its characteristics (input and output characteristics). (10) (Nov 2009) iii) Explain the working of SCR and state any two applications. (8) (May 2009) iv) Why Triac is called a doubled ended SCR? Explain the construction, operation and characteristics of a Triac with a help of neat diagram. (16) (May 2008) v) What is TRIAC? Explain its characterisdtics and construction vi) Discuss the applivcation of TRIAC in temperature control (May 2007) vii) Explain the basic priciple and operation of a SCR (Nov 2007) 3. Amplifier (Apr/May 2011-R2008, May 2007) a) If the various parameters of a CE amplifier which uses the self bias Vcc = 12 V, R1 = 10 K, R2 = 5 K, Rc = 1 K, RE= 2 K and = 100, find the coordinates of the operating point the stability factor Assuming the transistor to be silicon. b) Differentiate CB,CC,CE configuration of BJT.
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(Apr/May 2011-R2008) (May 2007)

Department of MECHANICAL ENGINEERING (10-14) 147406 EMP

c) Explain the common emitter characteristics of BJT and explain its output and input characteristics (10) d) Find IC and IE for a transistor for which both the emitter and collector junctions are reverse biased. Assume ICO=5A,IEO=3.57A and F=0.98. (6) e) With neat circuit diagrams, explain the methods of transistor biasing. f) Explain in detail about the CE configuration with a neat circuitry (10) g) Explain the Input-output characteristics for common base NPN transistor with its neat graphs h) Draw the circuit of a transistor in the common emitter configuration. Sketch the output characteristics. Indicate the active, saturation and cut-off regions. (16) i) Compare four different biasing circuit in detail (4) j) Discuss how negative feedback improves stability, increases bandwidth and reduces distortion. (4) k) Derive the general expression for stability factor. (6) 4. Negative Feedback system (Apr/May 2011-R2008, Nov 2009, May 2009) a. Why do we prefix negative feedback system? Explain the operation of voltage shunt feed back with required diagrams. (Apr/May 2011-R2008) b. Write an application of negative feedback in temperature control. (6) (Nov 2009) c. State the concept of feedback. (4) (May 2009) 5. JFET (Apr 2010) a. Explain the construction of JFET. Also define its characteristic parameters(Apr 2010) b. write in detail about the operation of JFET under various biasing conditions (Apr 2010) c. Explain the working of JFET

6. State any two application of switching transistors in motor speed control.(4) (May 2009) 7. Explain the operation of UJT and list its applications (Nov 2007)

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Department of MECHANICAL ENGINEERING (10-14) 147406 EMP

UNIT III PART A

1. Problems (Apr/May 2011, Nov /Dec 2010, Apr/May 2010, MAY 2009, Apr/May 2008, Nov/Dec 2007,Nov 2005, Apr 2005,Nov 2004, Apr 2004) a) Simplify the Boolean equation (Apr/May 2011) F = (A+B+C)(A+B+C) = ( A.A+A.B+A.C + A.B+B.B+B.C+AC+B.C+C.C) = (1+ A.B+A.C+A.B+1+B.C+AC+B.C+1) = ( A.B+ A.B+A.C+ AC +B.C+B.C) = (A.B+A (C+C) +B (C+C)) = (A.B+ A+B)

b) Convert 65 into BCD.( Nov /Dec 2010) 65= 0110 0101 c) Using Boolean laws, prove that X.Y+Y=X+Y (Apr/May 2010) A+AB=A+AB+AB =A+AB+AB =A+ (A+A) B =A+ (1.B) =A+B d) Write the binary equivalent of 25355(MAY 2009) (110001100001011)2 e) Solve the following: (1F8)16= (__? __) 8= (__? __) 2 (Apr/May 2008) (1F8)16 = (770)8 = (111111000)2 j) Convert the binary numbere 110001 into its decimal equivalent (Nov/Dec 2007) The decimal equivalent of this binary number (110001)2 is (49)10 f) Prove that A+A'B = A + B, Using Boolean algebra. A+AB = (A+A') (A+B) = 1 (A+B) where A+A' = 1 = A+B g) Construct the truth table of F=(AB)(CD). Sl.no 1 2 3 A 0 0 0 B 0 0 0 C 0 0 1 D 0 1 0 (Nov 2005)

(Nov 2005)

AB CD F=(AB)(CD) 0 0 0 0 1 1 0 1 1
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Department of MECHANICAL ENGINEERING (10-14) 147406 EMP

4 5 6 7 8 9 10 11 12 13 14 15 16

0 0 0 0 0 1 1 1 1 1 1 1 1

0 1 1 1 1 0 0 0 0 1 1 1 1

1 0 0 1 1 0 0 1 1 0 0 1 1

1 0 1 0 1 0 1 0 1 0 1 0 1

0 1 1 1 1 1 1 1 1 0 0 0 0

0 0 1 1 0 0 1 1 0 0 1 1 0

0 1 0 0 1 1 0 0 1 0 1 1 0 (Apr 2005)

h) Simplify A+AB+A'+B. A+AB+A'+B = A (1+B) + A'+B where 1+B=1 = A+A'+B = 1+ B where A+A'=1 =1 i) Perform 2s complement subtraction of 010110-100101. 1s complement of minuend100101 = 011010 2s complement of 011010 = 011011 Addition of 010110 + 011011 = 110001 There is no end carry. Therefore, the answer is (2s complement of 110001) Answer = - 001111

(Nov 2004)

j) Obtain 3 level NOR NOR implementation of f(a,b,c,d,e,f)=[ab+cd ]ef. (Nov 2004) f (a, b, c, d, e, f)=[ab+cd ]ef = abef +cdef = abef . cdef = a+b+e+f . c+d+e+f k) Apply Demorgans theorems to simplify (A+BC') '. (A +BC') = A'. (BC') ' = A. (B'+ C) (Apr 2004)

l) If A and B are Boolean variables check if (A.A') (A A')=(B+B') (B' B). (Apr 2003) A 0 1 A 1 0 AA AA (AA) (AA) 0 0 1 1 1 1 B B 0 1 1 0 B+B 1 1 BB (B+B) (BB) 1 1 0 0

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Department of MECHANICAL ENGINEERING (10-14) 147406 EMP

2. Flip flop and latches (Apr/May 2011, Apr/May 2010,Nov/Dec 2009, April/May-2008, Nov/Dec 2007, Nov /Dec 2006, Apr 2004, Nov 2003, Apr 2003) a) Draw the circuit of transparent latch. (Apr/May 2011)

b) What are the methods used to eliminate racing (Apr/May 2010) A race condition occurs when the output of logic circuit is fed back into the input in such a way as to change the output such that settling of the inputs delays the final stabilization of the outputs. It can also occur when two inputs to a circuit change at the same relative time, but the result depends on time sequence, such as in a D-flip flop where the clock is edge triggered. In essence to avoid a race condition, you want to design the circuit so that propagation delay is not accumulate in series. c) How do you implement D flip flop using SR flip flop? (Nov/Dec 2009)

d) What is a flip-flop? ( May 2009, April/May-2008) The basic unit for storage is flip-flop. A flip-flop maintains its output state either at 1 or 0 until directed by an input signal to change its state. There are various types of flip-flop. Some of them are mentioned below they are, RS flip-flop e) What are the different types of flip flops(Nov/Dec 2007) (Nov /Dec 2006) There are four types of flip-flops i) R-S flip flop ii) D flip flop iii) JK flip flop iv) T flip flop
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Department of MECHANICAL ENGINEERING (10-14) 147406 EMP

f) Write the characteristic equation of JK flip-flop. A(t + 1) = JA' + K'A B( t + 1) = JB' + K'B

(Apr 2004)

g) State a limitation of SR flip-flop. (Nov 2003) The last input condition in SR flip-flop is S=1 and R=1. This Condition will produce 0 at the output of both the NOR gate. Hence Qn+1=0 and Q'n+1= 0. This condition violates the fact that the outputs Qn+1 and Q'n+1 are the complements of each other. In normal operation, this condition must be avoided by making sure that 1s are not a applied to both inputs simultaneously. h) What is the condition of a JK flip-flop to work as a D flip-flop? J=D K=D 3. Logic gates ( Nov /Dec 2010, Nov/Dec 2009, MAY 2007, MAY 2006, Nov 2004) a) Give the truth table and symbolic representation of NAND and NOR( Nov /Dec 2010) (Apr 2003)

b) How do you implement EXOR gates using NAND gate only? (Nov/Dec 2009)

c) Write the truth table for 2 input NAND gate. A 0 0 1 1 B 0 1 0 1 Y 1 1 1 0

(MAY 2007)

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Department of MECHANICAL ENGINEERING (10-14) 147406 EMP

d) Draw the two input AND Gate and give its truth table A 0 0 1 1 B 0 1 0 1 Y 0 0 0 1

(MAY 2006 )

e) What are tristate gates? (Apr 2005) This is a modification of a totem pole TTL where the wired connection of outputs common bus system. This is capable of producing three distinct states a high, a low and a high impedance state. f) What are the universal gates? (Nov 2004) NAND and NOR are universal gates, because they replace all the other gates in a circuit. 4. Draw the circuit of full adder (Apr/May 2010)

5. Write three laws of Boolean algebra. i) Commutative law ii) Associative law iii) Distributive law iv) Idempotent law v) Identity law vi) Absorbtion law vii) De- Morgans law

(MAY 2007)

6. State Demorgans law. (MAY 2006, Apr 2005) (X+Y) = X' .Y' Demorgans law is mostly useful in simplifying expressions in which a products or sum variables is inverted. 7. What are binary counters? i) Binary up ripple counter. ii) Binary down counter. iii) Up down counter. (NOV 2006)

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Department of MECHANICAL ENGINEERING (10-14) 147406 EMP

8. Define fan in. (Nov 2005/ Nov 2004) Fan in is defined as the total number of inputs to a logic gate. 9. Define hazard. (Nov 2005/Nov 2003) Hazard is the unwanted transient i.e. Spike or glitch that occur due to unequal propagation delays through a combination circuit. 10. What is combinational circuit? Give an example. (Apr 2005) A combinational circuit consists of logic gates whose outputs at any time are determined from the present combination of inputs. Examples of combinational circuits are adder, coder, magnitude comparator etc. 11. Define noise margin. (Apr 2005/Nov 2003) It is the maximum noise voltage added to an input signal of a digital circuit that does not cause an undesirable chance in circuit output. 12. What is a sequential circuit? Give an example. (Apr 2005) The logic circuit whose outputs at any instant of time depend not only on the present inputs but also on the past outputs are called sequential circuits. Example : flip-flops.

13. What is demux? (Apr 2004) Demultiplexer is a circuit that receives information on a single line and transmits this information on one of 2n possible output lines. A demultiplexer is a decoder with an enable input. 14. What is an asynchronous sequential circuit? (Nov 2004) If a circuit is not controlled by a clock the transition of one state to next state occur whenever there is a change in the input to the circuit at any time and hence this circuit is called asynchronous sequential circuit. 15. What is a EPROM ? (Apr 2004) EPROM is a programmable ROM whose content can be erased using ultra violet rays and the ROM can be subsequently programmed 16. Name two sequential switching circuits. Pulse mode sequential circuit Fundamental mode sequential circuit (Apr 2003)

PART B 1. Counter ( APRIL/MAY 2011.R-2008, Apr 2010, May 2007) a) With the logic diagram, explain the working of Ring Counter. Also draw the timing diagrams ( APRIL/MAY 2011.R-2008) b) With a neat timing diagram and truth table explain with operation of 4 bit ripple counter.

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Department of MECHANICAL ENGINEERING (10-14) 147406 EMP

c) Design a 4 bit binary parallel counter. Support your answer with circuit diagram and truth table. (Apr 2010) d) Describe the operation of a 4 bit, binary ripple counter. (10) ( May 2007)

2. Logic gates (Apr/May 2011) a) Reduce the following function and implement using universal gates F = ABC+ABC+ABC+ABC+ABC+ABC
b) c)

d) e)

(Apr/May 2011) Which gates are called universal gates?Why?State and prove the Demorgans theorem with truth table. (8) Reduce the given expression: (1) Y= (A+B+C)(A+B) (2) Y=AB+ABC+ABC (3) Y=1+A (BC+BC+BC)+ABC+AC (4) Y= (A+B+C) + (B+C) Discuss the advantage of binary system. (4) Write the truth table for AND, OR, NOT, NAND, NOR, XOR. (8)

3. Half adder and Full adder (Nov/Dec 2010, May 2009, May 2008) a) Design a half and Full Adder (Nov/Dec 2010) b) Implement the full adder circuit from its truth table. c) With necessary diagrams and truth tables, explain the operation of half adder and full adder (6+6) d) Draw and explain the operation of full adder circuit. (10) e) Design an full adder. (8) (May 2009) f) Draw the logic circuit,symbol and truth table of a full adder and explain its operation. (6) (May 2008) 4. ADC and DAC ( Nov/Dec 2010, Apr 2010, Nov 2009, May 2009, May 2007) a) Explain the successive approximation type of A/D and resistor to ladder D/A converter. ( Nov/Dec 2010) b) Discuss in detail, the principle of operation of digital to analog converter. (Apr 2010) c) Explain with neat diagram the operation of Analog to Digital converter and List out the various methods of implementing Analog to digital converter. (16) (Nov 2009) d) Explain the working of successive approximation type A/D converter. (8) (May 2009)
e) Write notes on A/D conversion (8) (May 2007) f) List the types of A/D converter and explain any one with suitable diagram. (8)

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Department of MECHANICAL ENGINEERING (10-14) 147406 EMP

5. FLIPFLOPS (May 2008,Nov 2007) a) Draw a circuit diagram of clocked R-S flip-flop and explain its function with truth table. (10) (May 2008 b) Explain the working of the following: (1) JK flip flop. (2) T-flip flop. (nov2007) c) Explain the operation of JK flip flop with truth table. (6) d) Explain the working of JK,RS flipflops. (8)

UNIT IV PART A 1. Programs and problems( Apr/May 2011, Apl/May 2010, Nov/Dec 2009, Nov 2005 , Apr 2005, Nov 2004, Nov 2003) a) What is the output at part 1 when the following instructions are executed? (Apr/May 2011) MVI A, 8FH A= 8F ADI 72H = 72 JC LOOP C= 1 SUM=01 OUT PORT 1 HLT LOOP: XRA A = 01 xor 01 OUT PORT 1 = 00H HLT Solution :The content of accumulator will be sent to Port 1 i.e. 00 b) Specify the output at port 1 if the following ALP is executed (Apl/May 2010) MVI B,88 MOV A,B MOV C,A MVI D,73 OUT port1 HLT Solution:- The content of accumulator will be sent to Port 1 ie 88

c) Write a 8085 program to multiply the number by six using shift operation (Nov/Dec 2009)

LXI H, 2200 : Initialize the memory pointer MOV E, M : Get multiplicand

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Department of MECHANICAL ENGINEERING (10-14) 147406 EMP

MVI D, 00H : Extend to 16-bits MVI A, 06H: Get 6 as mulitiplier LXI H, 0000 : Product = 0 MVI B, 08H: Initialize counter with count 8 MULT: DAD H: Product = product x 2 RAL : Rotate left through carry

JNC SKIP: Is carry from multiplier 1 ? DAD D : Yes, Product =Product + Multiplicand SKIP: DCR B : Is counter = zero JNZ MULT : no, repeat SHLD 2300H : Store the result HLT : End of program d) Write an 8085 assembly language program, which checks to see if the number is even or odd and if it is odd returns a 0 in B register else returns a 1. (Nov 2005 ECE) PUSH PSW POP B MOV A,C STA 2000H. HLT e) If 6 MHZ crystal is connected with 8085 how much is the time taken by 8085 to complete opcode fetch cycle and memory read cycle. (NOV 2005 IT) External clock frequency = 6MHZ internal clock frequency = external clock/2 = 6/2= 3 MHZ time period of one T states=1/3 MHZ= 0.333s time taken to complete opcode fetch and memory read cycle= 7T*0.333s=2.31s f) Give the clock out frequency and state T of 8085 when the crystal frequencies are (a) 5 MHz (b) 6.144 MHz. (Apr 2005 CSE) The clock frequencies are 5/2 =2.5 MHz and 6.144/2 = 3.07

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Department of MECHANICAL ENGINEERING (10-14) 147406 EMP

g)

If the frequency of the crystal connected to 8085 is 6 MHz, Calculate the time to fetch and execute NOP instruction. (Nov 2004 IT) This instruction performs no operation ,just provide delay Time taken to fetch and

execute nop is 4T*0.33s= 1.32s h) Write an ALP for time delay using a register pair available in 8085. (Nov 2004 ECE) LXI h 4500 DCX h MOV A,C ORA B JNZ Loop i) Identify the opcodes, operands and find the number of bytes of the following instruction. MVI H, 47 H, ADI F 5 H, SUB C. (Nov 2003 CSE) Loop: MVIH,47 26, 47 2 bytes ADI F5H C6,F5 2 bytes SUB C 91 1 bytes 2. Registers (Nov/Dec 2010, NOV2006 ) a) List out the 16-bit registers of 8085. (Nov/Dec 2010) There are three 16-bit register pairs, BC, DE, and HL b) Give the format of flag register in 8085. (MAY 2006 IT,NOV2006 CSE) D7 Sign Flag D6 Zero Flag D5 D4 Auxiliary Carry flag D3 D2 Parity Flag D1 D0 Carry Flag

3. Instruction (Nov/Dec 2010, Apl/May 2010, May/Jun 2009, Apr/May 2008, Nov/Dec 2007, Nov/Dec 2006,Nov 2005,APRIL 2004,Nov 2003) a) Explain the 8085 instruction DAA. (Nov/Dec 2010) The contents of the accumulator are changed from a binaryvalue to two 4-bit binary coded decimal (BCD) digits.This isthe only instruction that uses the auxiliary flag to perform thebinary to BCD conversion, and the conversion procedure isdescribed below.S, Z, AC, P, CY flags are altered to reflectthe results of the operation. If the value of the low-order 4-bits in the accumulator isgreater than 9 or if AC flag is set, the instruction adds 6 to thelow-order four bits. If the value of the high-order 4-bits in the accumulator isgreater than 9 or if the Carry flag is set, the instruction adds 6to the high-order four bits.

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Department of MECHANICAL ENGINEERING (10-14) 147406 EMP

b) Shortly comment on DAA instruction (Apl/May 2010) Decimal Adjust Accumulator used to adjust the hexadecimal value in Accumulator to its equivalent BCD value. It can be used only after addition operation.

c) Explain the mnemonic Instruction LHLD and SHLD. (May/Jun 2009) LHLD-Load the 16-bit content pointed by the specified address to HL register pair SHLD-Store the 16-bit content of HL register pair to address specified d) What is a mnemonic instruction? (Apr/May 2008) Even though the instructions cab be written in hexa decimal code it is still difficult to understand a program written in hexadecimal numbers. So each manufacturer of a microprocessor has devised a symbolic code for each instruction called a mnemonic. The mnemonic for a particular instruction consists of letter that suggests the operation to be performed by that instruction. e) Explain about the instruction in 8085 (a) SHLD (b) STAX rp (Nov/Dec 2007) SHLD -Store the 16 bit content of HL register pair to the address specified STAX rp -Store the 8 bit content of accumulator to the address pointed by register pair f) Give the Description for the instruction RRC of 8085. (Nov/Dec 2006) Rotate Accumulator Right The content of the accumulator is rotated right by one bit. The zero bit of the accumulator (B0) is moved to the seventh bit (B7) as well as to carry bit. g) Give the significance of SIM and RIM instruction in 8085 microprocessor. (NOV2006 CSE, APRIL 2004 ECE) SIM is used to mask the hardware interrupts RST 7.5, 6.5, 5.5. It also used to send data through SOD line. RIM is used to check whether an interrupt is masked or not. It is also used to read data from SID line. h) How are branch instructions classified? (MAY 2006 MECH) i) Conditional jump ii) Unconditional jump iii) Call iv) Return. i) Write different external hardware synchronization instructions of 8085. (NOV 2006 MECH) i) Halt instruction ii) NOP iii) EI &DI iv) SIM&RIM j) Give the description for the instruction RRC of 8085.(NOV 2006 MECH) RRC: rotate accumulator right to carry. The content of A register is rotated right by one bit and the right most bit of A register is rotated to carry.
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Department of MECHANICAL ENGINEERING (10-14) 147406 EMP

k) Write the operation carried out when 8085 execute DAD H instruction. (NOV 2005 IT) The content of register pair is added with content of HL register pair. Only carry flag is affected l) What are the types of instruction for 8085 microprocessor? (Nov 2005 CSE)

The 8085 can be classified into the following categories Data transfer, Arithmetic, logical, branching and machine control instruction MHz m) What are the two compare instructions in 8085? (Nov 2004 ECE) CMP reg, CMP M n) Explain the execution of the instruction CMA M in 8085. (Nov 2003 ECE) The content of memory address by HL pair is compared with ACC. The comparison is performed by subtracting the content of memory from A register. The subtraction is performed in ALU and the result is used to modify flags and then discarded. After execution of the instruction the content of the Acc and the memory are not altered. All flags are affected by this instruction.

4. Differentiate memory mapped I/O (Apl/May 2010) Memory Mapped I/O 1. 16-bit address is allotted to I/O devices. 2. The devices are accessed by I/O read or I/O write cycle. 3. All instructions related to memory can be used for data transfer. 4. A large number of I/O ports can be interfaced.

techniques from I/O mapped I/O techniques Standard I/O mapped I/O 8-bit address is allotted to I/O devices. The devices are accessed by memory read or memory writes. Only IN and OUT instructions can be used for data transfer. Only 256 ports can be interfaced.

5. Interrupt (Apr/May 2010, Nov/Dec 2009, MAY 2007 MECH, May/Jun 2007) a) List the interrupt and their call locations (Apr/May 2010) b) List four interrupts of 8085 (May/Jun 2007) c) How many interrupts are available in 8085? List out. (Nov/Dec 2009) d) List four interrupts of 8085. (MAY 2007 MECH) There are five interrupts in 8085 RST5.5 RST6.5
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Department of MECHANICAL ENGINEERING (10-14) 147406 EMP

RST7.5 TRAP INTR 6. Addressing modes (May/Jun 2009, MAY 2007 MECH, MAY 2009,Apl/May 2008, Nov/Dec 2007, May/Jun 2007) a) List the various types of addressing modes in 8085. (May/Jun 2009) (Or) Name addressing modes of 8085. (MAY 2007 MECH, MAY 2009) (Or) What are the various types of addressing modes in 8085 (Nov/Dec 2007) (Or) Name two addressing modes of 8085 (May/Jun 2007) 8085 supports five addressing modes they are i) Immediate addressing mode ii) Direct addressing mode iii) Indirect addressing mode iv) Register addressing mode v) Implied addressing mode b) What is meant by an addressing mode? (Apl/May 2008) Various formats of specifying the operands by its location and nature is called as addressing mode.

7. Pin discription (MAY2006 , Nov 2004) a) State the function of ALE and TRAP pins in 8085. (MAY2006 IT, Nov 2004 IT) ALE: The ALE (Address Latch Enable) is signal used to demultiplex the address and data lines using the external latch. It is used as enable signal for external latch. TRAP: The interrupt TRAP is non maskable and it cannot be disabled by DI instruction. Also the Trap is not disabled by the system reset or after recognition of another interrupt. The only signal, which can override TRAP, is HOLD. b) State the function of HOLD pin in INTEL 8085 processor. (Apr 2004 IT)

The HOLD and HLDA signals are used for the DMA type of data transfer. This type of data transfer is achieved by employing a DMA controller in the system. When DMA is required the DMA controller will place a high signal on the HOLD pin of 8085. When HOLD input is asserted high, the processor will enter a wait state and drive all its tristate pins to high impedance state and send an acknowledge signal to DMA controller through HLDA pin. Upon receiving the acknowledge signal, the DMA controller will take control of the bus and perform DMA transfer and AT the end it asserts HOLD signal low. 8. Specify how a program counter is useful in program execution. (Nov 2004 CSE) The program counter keeps track of program execution. To execute a program the starting address of the program is loaded in program counter. The PC sends out address to fetch a byte of instruction from memory and increment its content automatically.

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9. How the data and address lines are de-multiplexed?

(Nov 2004 CSE)

The lower order address and data lines of 8085 are de multiplexed using an external 8-bit D- latch (74LS373) and the ALE signal of 8085,as shown in figure At the beginning of every machine cycle, ALE is asserted high and then low. Also the low byte of address is given out through AD0 AD7 lines. Since the ALE is connected to enable of latch, whenever ALE is asserted high and then low the address are latched into the output lines of the latch the lines AD0 AD7 are free for data transfer.

8085(CPU) AD0 AD7

ALE

D0 D7

8-bit D- latch (74LS373)

EN

10. What is meant by PLAs and PALs? (Apr 2004 CSE) Now days modern computers system uses programmable logic devices such as PALs , PROM or PALs to implement the glue logic between LSI devices. In programmable logic array both the AND matrix and the OR matrix are programmable by leaving in fuses or blowing them out. The two programmable matrix make PLA very flexible, but difficult to program. In programmable array logic the connection in the OR matrix are fixed and the AND matrix connection are programmable .PAL are often used to implement combinational logic and address decoder in multi computer system. 11. Why do ROM and RAM have tri-state bus outputs? (Apr 2004 CSE) In a computer system, the data signals of many memory devices (the data bus) may be connected together and also to the CPU. Tristate logic allows these devices to be connected together without causing contention or clash on the data bus. The figure below shows a noninverting tristate buffer, with an active low enable. Tristate buffer devices (the simplest example) have an input, an output and a second input, called the enable signal, which may be active high or low depending on the device in question. When the enable signal is active (low in the example above) the output follows the state of the input signal (after a short delay tpd, called the propagation delay of the device). When the enable is inactive (high in our case) the output of the buffer is effectively disconnected from the input. This is often referred to as being in the high impedance state, the high-Z state or in tristate. A typical tristate buffer is a 74HC244, and a typical bidirectional tristate buffer or transceiver is a 74HC245. Bi-directional buffers are often used in data buses to increase the drive characteristics of the memory devices. Note that al most all CPUs, RAMs and ROMs have tristate buffers on their data bus pins. When the output enable or the chip enable of the RAM, for example, is inactive, the data bus of the RAM is in the highimpedance state and is effectively disconnected from the bus. Therefore another memory device or buffer will be free to drive the bus undisturbed.

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12. When the READY signal of 8085 processor is sampled by the processor? (Apr 2005 ECE) The READY is an input signal that is can be used by slow peripherals to get extra time in order to communicate with 8085. The 8085 will work only when READY is tied to logic high. Whenever READY is tied to logic low, the8085 will enter wait state. When the system has slow peripheral devices, addition hardware is provided in the system to make the READY input low during the required extra time while executing a machine cycle, so the processor will remain in the wait state during this extra time. 13. What are the difference between 8085 and 8086? 8085 1. It has 16 bit address for memory and 8 bit address for input output mapped. 2. The flag registers are five flags. (Nov 2004 ECE) 8086 It has 20 bit address for memory So physical address space is 1 MB. All internal registers are 16 bit wide

14. What is meant by processor cycle? (Apr 2004 ECE) The processor cycle or machine cycle is the basic operation performed by the processor. To execute an instruction, the processor will run one or more machine cycles in a particular order. PART B 1. Problem (Apr/May 2011,NOV/DEC 2010,May 2010, May 2008,May 2007) a) The following block of data is stored in the memory locations from 4000H to 4005H. Transfer the data to the locations 5000H to 5005H in the reverse order. Write an ALP in 8085 to perform the block transfer. 22H, A5H, B2H, 99H, 7FH, 37H. (Apr/May 2011) b) Write a simple program to sort the given number in ascending and descending order (NOV/DEC 2010) c) Write a program to find the greatest number from the given three numbers. (8) (Nov 2009) d) Write a simple program in 8085 to perform addition of two decimal numbers (16) (May 2009) e) Write the assembly language program to find the biggest and smallest in an array of given numbers. (may 2007) f) Write a simple assemble language program in 8085 to add two 8-bit numbers (Nov 2007) g) Write an 8085 assembly language program to add two 8 bit numbers and to store the result. (5) h) Explain the operation of the following 8085 program. (6) LX1 SP, 07FFH
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PUSH B PUSH H POP B POP H HLT (may 2008) 2. Explain the interrupt structure of 8085 CPU with the required diagrams.(Apr/May2011) 3. Architecture (NOV/DEC 2010,Apr/May 2010,) a) Sketch the architecture of 8085 and explain the modules. (NOV/DEC 2010) b) Explain the architecture of 8085 CPU. Support your answer with neat block diagram c) Explain the architecture of 8085 with the required diagrams. Also write the salient feature of the same. (Apr 2010) d) Discuss the architecture of 8085. e) Draw the block diagram of 8085 and explain each block.(16) f) With neat block diagram explain the architecture of 8085 microprocessor g) Explain about the architecture of 8085 in detail. (12) h) Draw a functional block diagram of a 8085 micro processor. (11)

4. Addressing modes (Apr 2010,Nov 2009,May 2008) a) Explain the various Addressing modes used in 8085 with example for each mode. (apr 2010) b) What are the addressing modes supported in 8085 CPU? Explain each of them with minimum of 2 sample instructions c) Write the addressing modes of 8085 d) What are the different types of addressing modes available in 8085? (8) ( Nov 2009) e) What are the various types of addressing modes? (4) f) Give all the addressing modes of 8085 and explain each of them with suitable examples.(10) (May 2008) 5. Discuss in detail the instruction set of 8085 giving suitable example for each group UNIT V PART A 1. WhatistheroleoftristatebufferininterfacingofperipheralswithCPU? or Write down the primary function of Tri-state buffer in Interfacing 2011,R2008,Apr/May 2010)

(Apr/May

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Department of MECHANICAL ENGINEERING (10-14) 147406 EMP

Tristate buffer is used to set the system bus in active high state, active low state and in ideal state. 2. WritetheuseofALEsignalin8085. (Apr/May 2011,R2008) ALE=Address Latch Enabled.(pin number 30 in 8085) o 8085 has a special pin referred as ALE, which indicates whether multiplex bus functions as an address bus or a data bus. Whenever 8085 starts any new operation, ALE signal goes to logic 1 for about 1/2 clock cycle, at about the falling edge of CLK. If ALE=1 then multiplex bus functions as address bus. After that half clock cycle, it goes to logic 0 for nearly 3 or 4 clock cycles. If ALE=0 then multiplex bus acts as a data bus. o The ALE pin helps to enable the latching of lower order ADDR bus. The AD0AD7 pins, as well as other control pins such as S0, S1, IO/M-, and the other address pins A8-A15, are setup to be correct at the falling edge of ALE. 3. Memeroy I/O and I/O mapped I/O ( Nov/Dec 2010- R2008, MAY 2009, Nov/Dec 2010,R2008, Nov/Dec 2009, Apr/May 2008) a) ListthefundamentalI/Otechniques.(or) List out the basic interfacing concepts. (Nov/Dec 2010- R2008, MAY 2009) I/O mapped I/O Memory mapped I/O b) ListanytwopointscomparingmemI/OandperipheralI/O.(Nov/Dec 2010,R2008) SI.No Memory mapped I/O In this device address is 16 bit. thus A0 to A15 lines are used to generate device address MEMR and MEMW control signals are used to control read and write io operations Instructions available are LDA addr, STA addr, LDAX rp ,STAX rp, MOV M,R ,MOV R,M , ADD M ,CMP M etc. I/O mapped I/O In this i/o device address is 8 bit. Thus A0 or A7 to A15 lines are used to generate devices address. IOR and IOW control signals are used to control read and write io operations. Instructions available are IN and OUT.

1.

2.

3.

c) What is meant by memory mapped I/O? (Nov/Dec 2009) (Apr/May 2008)

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Department of MECHANICAL ENGINEERING (10-14) 147406 EMP

i) ii) iii) iv)

16-bit address is allotted to an I/O device The devices are accessed by I/O read or I/O writes cycle All instructions related to memory can be used for data transfer. A large number of I/O ports can be interfaced.

4. Application (Apr/May 2010, Nov/Dec 2009, MAY 2009, April/May-2008, Nov/Dec 2007, 2006) a) Name any two temperature sensor used in microprocessor based temperature control (Apr/May 2010) Some of the temperature sensors used in microprocessor based temperature control i) Resistance thermometer ii) Thermocouple iii) Thermisters iv) Pyrometers b) List any four application of microprocessor in Automobile industry. (Nov/Dec 2009) Microprocessors are used in many automotive systems: i) The electronic fuel injection system uses an elaborate computerized control that takes into consideration engine conditions when metering fuel, and it's based on one or more microcontrollers. The system also controls spark advance, EGR valve and other engine functions. ii) The anti-lock brake system uses a microcontroller to compare the wheel speed when brakes are applied and pulses the brakes when one or more wheel slips. iii) The radio uses specialized microcontro c) Mention the microprocessors which are used in traffic light controllers. (MAY 2009) The microprocessor which is used in traffic light controller is 8085 microprocessor. d) Discuss the role of microprocessor in a traffic light control. (April/May-2008) The role of microprocessor in traffic light controller is to control all the signals from peripherals. The microprocessor Controls the on and off of the LEDs with proper timing. So as to regulate the movement of traffic in a traffic light controller e) Write any two application of the microprocessor 8085 (Nov/Dec 2007, 2006) State the applications of microprocessors. (NOV 2006) i) It is used in all automation products. ii) It is used in robotics. iii) It is used in automobile industry Some of the applications of microprocessor were i) Stepper motor controller ii) Temperature controller

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Department of MECHANICAL ENGINEERING (10-14) 147406 EMP

iii) Traffic light controller 5. Define interfacing devices (Apr/May 2010) Interfacing devices are used to connect peripheral devices to microprocessor. 6. What is transceiver (Apr/May 2010) Transceiver is a device can able to transmit and receive data to or from peripherals to microprocessor 7. List the ports of 8085. (MAY 2007) There are no ports in 8085 microprocessor. 8. 8255 parallel peripheral interface (MAY 2007 MECH, MAY IT 2006, Nov 2004 IT, Nov 2003 IT) a) Write the control word format of 8255 PPI. (MAY 2007) Command word format: D7 D6 D5 D4 D3 D2 D1 D0 D7: EH 1=hunt mode 0=normal operation D6: IR 1=internal reset 0=normal operation D5: RTS set nRTS output value 1: nRTS='0' 0: nRTS='1' D4: ER 1=reset error flags 0=keep error flags D3: SBRK 1=send break character 0=normal operation D2: RXE 1=enable receiver 0=disable receiver D1: DTR set nDTR output value 1: nDTR='0' 0: nDTR='1' D0: TXEN 1=enable transmitter 0=disable transmitter b) List the different modes of 8255 for I/O operation. (MAY 2006) Main two modes of 8255 are BSR mode and I/O mode, in I/O mode there are three modes i) mode 0 ii) mode 1 iii) mode2 c) State the functions of the control register in INTEL 8255? (Apr 2004) It is used to select modes. It is used to select different ports. d) Specify the bit of controller word for 8255,Which differentiates between I/O mode and the BSR mode? (Nov 2004) DIAGRAM D7 is the bit used to differentiate between I/O mode and the BSR mode. e) Write the format BSR control word in 8255? (Nov 2004, Nov 2003) B0 B7 B6 B5 B4 B3 B2 B1 If B7= 0 it is BSR MODE. B6,B5,B4 are dont care
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Department of MECHANICAL ENGINEERING (10-14) 147406 EMP

B3,B2, B1 are used to select port C pin TO set or reset depending on the bit B0 B0=0 RESET, if B0=1 SET 9. 8251 serial interface (MAY 2006, Apr 2005 , Nov 2004) a) State the function of DSR and DTR pins in 8251. (MAY 2006) DSR- Data Set Ready. It is used to test the modem condition. DTE- Data Terminal Ready. It is used to check whether receiver is ready or not. b) Draw the command word format for 8251. DIAGRAM D7 D6 D5 D4 D3 D2 D1 D7: EH 1=hunt mode 0=normal operation D6: IR 1=internal reset 0=normal operation D5: RTS set nRTS output value 1: nRTS='0' 0: nRTS='1' D4: ER 1=reset error flags 0=keep error flags D3: SBRK 1=send break character 0=normal operation D2: RXE 1=enable receiver 0=disable receiver D1: DTR set; nDTR output value 1: nDTR='0' 0: nDTR='1' D0: TXEN 1=enable transmitter 0=disable transmitter (Apr 2005 ) D0

c) Name any two important methods available for error correction during serial communication? (Nov 2005) The status word can be read by the CPU to check the readiness of the transmitter or receiver and to check the character synchronization in synchronous reception .It also provides information regarding various errors in the data received. The various error conditions that can be checked from the status word are parity error overrun error and framing error. d) What is meant by baud-rates and how is it achieved? (Nov 2005) The baud rate is the. rate at which the serial data are transmitted. Baudrate is defined as l/(The time for a bit cell). In some systems one bit cell has one data bit, then the baud rate and bits/sec are same. d) Mention any two functions performed by INTEL 8251. (Nov 2004) It is used for converting parallel data to serial or vice versa. The data transmission or reception can be either asynchronous or synchronous. It is also used to interface MODEM and established serial communication through MODEM over telephone lines e) Specify the two types of serial communication. The two types are:
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Department of MECHANICAL ENGINEERING (10-14) 147406 EMP

i) Synchronous and ii) asynchronous communication

10. 8259 interrupt controller (Nov 2006,MAY 2006, Nov 2003) a) Differentiate polling and interrupt. (NOV 2006) Polling means periodically y check the need for the services. Interrupt means whenever there is a need interrupt will be given and service will be given. b) List the features of 8259. (MAY 2006) i) It manages 8 interrupts ii) Interrupts can be masked or unmasked individually. iii) It provides the status of pending interrupts. iv) It can be cascaded. c) What is 8259? What are its functions? (Nov 2003) 8259 is a programmable interrupt controller. It major functions are can manage eight interrupt according to the instruction Vector an interrupt request anywhere in the memory map. Mask each interrupt request individually. 11. 8279 display and keyboard interface (MAY 2006 , Apr 2005) a) What is meant by key de-bounce on microprocessors? (MAY 2006 ) When a key is pressed it bounces for a short time. If a key code is generated immediately after sensing a key actuation, the processor will generate the same key code a number of times; hence the processor has to wait for the key bounces to settle before reading the key code. b) List the functions performed by 8279. (Apr 2005) The functions performed by 8279 were Keyboard Scanning, Key Deboncing, Key code Generation, Informing the key entry to CPU, Storing display codes, output display codes to LEDs and Display refreshing.

12. What are the four operations that are performed primarily by the micro processing unit (MPU)? (MAY 2006 ) Op-code fetch, decode, execute, control and decision making 13. 8257-DMA controller a) What is cycle stealing in DMA? (Apr 2005) In cycle stealing DMA the DMA controller will perform one DMA transfer in between instruction cycles b) How DMA is initiated?
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(Nov 2004)

Department of MECHANICAL ENGINEERING (10-14) 147406 EMP

When the input output device needs a DMA transfer, it will send a DMA request signal to DMA controller. The DMA controller in turn sends a HOLD requests to the processor. When the processor receives a HOLD request it will drive its tri-stated pins to high impedance state at the end of current instruction execution and send an acknowledge signal to DMA controller. Now DMA controller will perform DMA transfer. c) List the four possible modes of operation of 8237 DMAcontrollers. (Nov 2003 ) The possible modes are: i) Demand mode (00) ii) Single mode (01) iii) Block mode (10) iv) cascade mode (11)

PART B 1. Traffic controller (Apr/May 2011-R2008, Nov/Dec 2010-R2008, Nov 2009, May 2009, May 2007) a) Design an 8085 CPU based traffic monitoring and control system to controlthetrafficat4cornerjunction. (Apr/May 2011-R2008)

b) c) d)

Explainindetailthe8085microprocessorbasedtrafficlightcontrol (Nov/Dec 2010-R2008) Write a short notes on traffic light control.(8) (Nov 2009) Explain the application of microprocessor as a traffic light controller. (16) (May 2009) e) Describe the operation of 8085 based traffic light control using suitable diagrams, flow chart and assembly language program. (May 2007) f) Design a traffic light control system using 8085 cpu. Write its sequence of operation with neat block diagram of the system. Support your answer with the software flowchart. g) Write an ALP for a simple 4 cross traffic light signaling system using 8085. Support your answer with a flow diagram 2. Stepper motor (Apr/May 2011-R2008, Nov 2007) a) Suggest the methods to vary the speed of shaft of a machine using stepper motor. Design the microprocessor based system interface to controlthespeedofsteppermotor.(Apr/May 2011-R2008) b) How to control the speed of stepper motor with 8085 cpu and its interfacing? Draw the neat interfacing diagram and explain its operation. c) Explain about the interfacing of the stepper motor.(Nov 2007) d) Design an I/O interface for stepper motor controller using 8085 (16)
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Department of MECHANICAL ENGINEERING (10-14) 147406 EMP e)

Discuss with the necessary hardware diagram, flow chart and assembly language program, stepper motor control using 8085 f) How do you interface the stepper motor with 8085 processor? Give the schematic diagram and program. 3. Temperature controller (Nov/Dec 2010-R2008, Nov 2009, May 2008) a) Explainindetailthe8085microprocessorbased temperature control system. (Nov/Dec 2010-R2008) b) Briefly explain microprocessor based temperature controller.(8)(Nov 2009) c) Explain the application of microprocessors in temperature control (10) d) Show a block diagram scheme of microprocessor based temperature control system and explains its function with a flow chart. (16) (May 2008) 4. Interfacing a) explain about the interfacing I/O devices in 8085 by the technique I/O mapped I/O b) Explain about the basic interfacing concepts. (6) c) Show a interface circuit of 8 bit input port with switches and 8 bit output port with LEDs to a 8085 microprocessor. (16)

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