D.Module.

C6x01
Board Revision 2.0 SUMMARY Highest Performance Floating Point (C6701) and Fixed Point (C6201) DSP Computer Module Peak Performance 200 MHz 1600 MIPS (C6201), 167 MHz 1GFOLPS (C6701) Stand-alone Operation Watchdog and Power Supply Supervisor 512 Kbytes SRAM, 2 Mbytes non-volatile Flash Memory, and optionally 16 Mbytes SDRAM 3.3V Single Supply Two 5V tolerant Serial Ports External Bus Interface for memory and I/O expansion (5V tolerant) Wait State Logic

Technical Data Sheet

Document Revision 2.1 June 2002

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Two pre-decoded Memory Select Signals UART with FIFOs and Auto-Flow Control, RS232 line interface User configurable 72 macrocell CPLD for I/O expansion and interface adaptation, 16 free I/Os (42 if HPI not used) 16 Bit wide, 5V tolerant Host Port Interface D.Module.BIOS, Configuration and Set-Up Utility Two 32 bit Timers Four external Interrupts JTAG Emulator Port Small Size: only 85 x 59 mm

Oscillator

JPBOOT JPMAP JPEND CLKIN

TMS320C6701/ TMS320C6201

512 kBytes SBSRAM

JPOSC DSPCLK McBSP0 McBSP1 TIMER0, FLAG0 TIMER1, FLAG1 JPH2 Level Shifter ADDR McBSP0 McBSP1 TIMER0 TIMER1 16 MBytes SDRAM CTRL DATA 2 MBytes Flash Memory

HPI CTRL HPI DATA Bus-Switch/ Level Shifter

HPI CTRL HPI DATA INT JPH1

nIOSEL, nMEMSEL nRD, nWR, BUSCLK

A0..A19 Bus-Switch/ Level Shifter D0..D31

User-Programmable, Reconfigurable CPLD PRGIO_0..15 nWAIT Board Logic, Board Configuration UART nSETUP, IN1 JPWD internal supply voltages System Reset nRESIN Power Supply, Supervisor VCC/GND nINT0..3 nRESOUT

JTAG in-system

programming

TxD,RxD,CTS,RTS

RS232

The D.Module family of DSP based Computer Modules offers a standardised hardware platform for embedded DSP applications. Mechanics and pinout are identical throughout the family members. 111 signals are reserved and provide identical functional-

ity. In combination with the D.Module.BIOS - a hardware independent application programming interface for onboard components UART, Flash Memory etc. portability is maintained. Re-engineering is reduced to a minimum if your system's requirements change.

D.SignT 2002 Doc #2.1

D.Module.C6x01

D.SignT
Digital Signalprocessing Technology

DSP The heart of the D.Module.C6x01 is the advanced VLIW architecture digital signal processor TMS320C6201 rsp. C6701 from Texas Instruments. This RISC architecture DSP offers 8 instruction units which operate in parallel, yielding a maximum performance of 1600 MIPS rsp. 1GFLOPS, 16/32 bit fixed point arithmetic (32bit floating point on C6701), 64 Kbytes internal program memory or cache, 64 Kbytes internal data memory, two multichannel buffered synchronous serial ports, two timers, a four channel DMA controller and a 16 bit wide Host Interface. The multichannel buffered serial ports provide a direct connection to T1/E1, SCSA, MVIP, AC-97, STBus and SPI interfaces and industry standard Codecs, A/D and D/A converters. High Speed data transfer up to 50 MBits/sec is possible. This also provides an efficient data path for multiprocessor communications. Data transfer between the McBSPs, the Host Interface and internal and external memory is possible under DMA control. The four channel DMA controller provides enhanced features which allow to maintain circular and ping-pong buffers without any CPU intervention. MEMORY The DSP itself provides 64 Kbytes internal program memory, organised as 2k x 256 bit to achieve single cycle access to the VLIW instruction fetch packets. This memory can also be configured as instruction cache for applications requiring a large (external) program memory. The 64 Kbytes internal data memory are divided in two blocks which allow simultaneous access. Byte, Halfword (16 bit) and 32 bit Word transfers are supported. The 512 Kbytes synchronous SRAM operate at full DSP clock speed providing single cycle access. The SBSRAM supports Byte, Halfword and Word data formats. It can be used as program and data memory. Additionally 16 Mbytes on-board SDRAM can be used for large data buffers as commonly required by image processing applications. Byte, Halfword and Word data is supported. SDRAM operates at half the DSP clock. 2 Mbytes Flash Memory are integrated for nonvolatile data and program storage. The Flash Memory is divided in multiple sectors of 64 Kbytes. Each sector can be erased individually and (re-)programmed on a Byte basis. The DSP has direct ac D.SignT 2002 Doc #2.1

cess to the Flash Memory: Identification, SectorErase and Programming is handled by BIOS functions which effectively encapsulate the programming algorithms. The onboard wait state logic generates the required wait states for Flash Memory accesses while retaining fast access to other asynchronous memory devices or expansions. Further external memory expansion is possible using the two pre-decoded select signals. The IOSEL memory range is primarily intended for connection of parallel interface data acquisition and communication devices, it can be used for asynchronous static SRAM expansion and/or additional Flash Memory too. The MEMSEL area supports Byte, Halfword and Word access to asynchronous and SDRAM memory. SDRAM is directly supported, the control signals are available on the external bus connectors CLOCKS An on board oscillator generates the DSP master clock. Additional clocks for external peripherals can be generated using the two 32 bit timers. The Serial Ports feature their own clock generation circuitry based on the DSP clock or an external master clock. POWER SUPPLY The D.Module.C6x01 requires a 3.3V single voltage power supply only. Secondary voltages for RS232 and CPU core are generated on board using PWM regulators and charge pumps. A micro-processor supervisor circuit controls the power supply sequencing and holds the board in reset if the supply voltage is below it's limit. EXTERNAL BUS INTERFACE The external bus interface is fully 5V tolerant to support a direct connection to 5V environments. The data bus is 32 bit wide, 20 address lines and four byte select outputs provide access to a linear 16 Mbytes address range (MEMSEL) and a 1 Mbyte linear address range for I/O expansion (IOSEL). Peripherals connected to the I/O memory area can request additional wait states or delay a bus cycle using the nWAIT input. The minimum I/O cycle time is 25 nsecs. UART The UART offers powerful features: 32 word receive and transmit FIFOs, automatic flow control (RTS/CTS and Xon/Xoff), and DMA support relieve the DSP from time-consuming interrupt driven data 2

D.Module.C6x01

D.SignT
Digital Signalprocessing Technology

transfers. Baud rates up to 460 kBaud are possible. The line interface is RS232, optionally RS422/485 is available. The onboard wait state logic generates the required wait states for UART accesses while retaining fast access to other asynchronous memory devices or expansions. The UART is fully supported by the D.Module.BIOS: initialisation and communication functions are provided USER-CONFIGURABLE CPLD One of the major challenges in DSP design is the integration into a host system and interfacing peripherals. To facilitate this the D.Module.C6x01 integrates a high speed 72 macrocell in-system programmable CPLD. 16 bit databus, address lines, control and clock signals are pre-connected to the DSP. The CPLD can be re-programmed via the module's Set-Up Utility by uploading the programming file. Additional I/O ports, serial interfaces like !C, bus interface adaptation, PWM and clock generation are some of the most typical applications. 16 I/Os are available and can be configured as input, output, or bi-directional signals. If the Host Port Interface is not used 26 additional signals can be used for userdefined I/O. HOST INTERFACE The 16 bit wide TMS320C6x01 Host Port Interface is fully accessible on the D.Module. A host controller has direct access to the entire memory range of the DSP. The HPI is 5V tolerant and multiplexed with User-CPLD signals. This configuration also allows the User-CPLD to control the HPI, or expand the number of user-programmable I/O if the HPI is not used. BOOT OPTIONS By default the D.Module.C6x01 is bootloaded from the Flash Memory. In this mode the BIOS, Configuration Utility and the Set-Up Utility are loaded first. The nSETUP signal (IN0) is sampled, if low Set-Up Mode is entered which allows to store programs and data in the Flash Memory, program the CPLD and execute diagnostic functions via a RS232 terminal connection. If nSETUP is not asserted, the BIOS bootloader loads the application program and executes it. . MODULE CONFIGURATION A module configuration register controls additional I/O signals on the D.Module.C6x01: Watchdog D.SignT 2002 Doc #2.1

Trigger, Reset-Output and Interrupt Multiplexer. Solder links are used to set the boot mode. The D.Module.C6x01 provides a unique Module Configuration File which is permanently stored in the Flash Memory. The Configuration File allows to store human-readable ASCII data for configuration such as communication parameters, signal-processing coefficients, temperature compensation tables etc. Maintenance and modifications of installations is greatly simplified: Edit the configuration file and upload the modified version in Set-Up mode. The Module Configuration File also provides scripting mechanisms to control system start-up: selftest and calibration programs can be bootloaded and executed prior to the main application. RESET and WATCHDOG A micro-processor supervisor circuit monitors the power supply and resets the module during powerup, power-down and brown-out conditions. A retriggerable single-shot guarantees a minimum reset pulse width of 140 msec. A debounced external reset input can be used to connect a system reset signal or a push-button for manual reset. An open drain reset output is controlled via the module configuration register and can be used to initialise external peripherals. A watchdog provides security against program lock-ups and hardware failures as required by most embedded applications. The watchdog timer must be re-triggered at least every 1.6 seconds, otherwise a reset is generated. The watchdog trigger is generated by the module configuration register. A status bit in the module configuration register reflects the cause of the last system reset. This allows to distinguish normal power-on or manual reset from a watchdog timeout. EXTERNAL INTERRUPTS The D.Module.C6x01 provides four external 5V tolerant interrupt inputs. Interrupts are edge triggered and can be configured for falling or rising edge. These inputs are multiplexed with CPLD and UART interrupts and UART DMA requests, controlled via the module configuration register. BIOS The D.Module.BIOS is an application programming interface for all on board resources. It encapsulates the hardware dependencies and provides functions for Module initialisation 3

D.Module.C6x01

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Digital Signalprocessing Technology

UART initialisation , send and receive functions Flash Memory programming support: identify device, erase a sector, programming and reading bytes, halfwords and words Module configuration: set and clear bits and bitfields in the module configuration register Miscellaneous functions: bootload and delay. Low-Level device drivers for stdio access (fprintf, fscanf etc.) to the UART and Flash Memory Functions to read parameters and settings from the Module Configuration File These functions are identical on all D.Modules and help to maintain program portability throughout the

D.Module family. The BIOS is written in hand-coded Assembler language to achieve optimum performance. All functions are C callable. SET-UP MODE By holding the nSETUP input low at system reset the module will enter Set-Up mode. In this mode the board communicates via a terminal connection and provides several options to upload programs, parameters and configuration files to the Flash Memory, re-program the User-CPLD, invoke test programs and basic debugging features - without the need for special programming or emulation equipment.

BOARD CONFIGURATION REGISTER RESETS Bit 0 Function Reset State Description source of the last system reset, read only 1 - Reset by watchdog timeout 0 - Reset by power-on or manual reset controls the nRESOUT pin U7 1 - nRESOUT = high 0 - nRESOUT = low enable external wait state requests via nWAIT on access to the User-CPLD 1 - read nWAIT on CPLD access 0 - ignore nWAIT on CPLD access reset the UART 1 - UART in reset 0 - UART in normal operation reset the User-CPLD 1 - User-CPLD in normal operation 0 - User-CPLD in Reset watchdog trigger 1 - toggle watchdog trigger 0 - watchdog trigger remains unchanged

RES_SOURCE see text

nRESOUT

CPLD_WAIT

UART_RESET

CPLD_RESET

WDOG_TRIG

INTERRUPT MULTIPLEXER Bit 0 Function INT5_MUX Reset State Description

2,1

INT6_MUX

4,3

INT7_MUX

0 mapping of DSP interrupt INT5 0 - external interrupt nINT1 (Pin U4) 1 - User-CPLD interrupt 00 mapping of DSP interrupt INT6 00 - external interrupt nINT2 (Pin A19) 01 - User-CPLD interrupt 10 - UART interrupt 11 - UART receive DMA request 00 mapping of DSP interrupt INT7 00 - external interrupt nINT3 (Pin A20) 01 - User-CPLD interrupt 10 - UART interrupt 11 - UART transmit DMA request

D.SignT 2002 Doc #2.1

D.Module.C6x01
MEMORY MAP MAP 0 DSP Address 0x0000.0000..0x0000.0BFF 0x0000.0C00..0x0000.0E5F 0x0000.0E60..0x0000.0FFF 0x0000.1000..0x0007.FF7F 0x0007.FF80..0x0007.FFFF 0x0100.0000..0x011F.FFFF 0x0120.0000..0x0127.FFFF 0x0128.0000..0x0128.000F 0x012C.0000..0x012C.001F 0x0130.0000..0x013F.FFFF 0x0140.0000..0x0140.FFFF 0x0180.0000..0x01FF.FFFF 0x0200.0000..0x02FF.FFFF 0x0300.0000..0x03FF.FFFF 0x8000.0000..0x8000.7FFF 0x8000.8000..0x8000.FFFF Memory SBSRAM 0 Wait States Description

D.SignT
Digital Signalprocessing Technology

Flash Memory User CPLD Module Configuration Registers UART IOSEL IPRAM DSP internal peripherals MEMSEL SDRAM IDRAM

SBSRAM, D.Module.BIOS functions SBSRAM, interrupt vector table default SBSRAM, D.Module.BIOS functions SBSRAM, 520064 Bytes free for user SBSRAM, D.Module.BIOS data area CE1, auto Flash Memory, direct access not possible, use BIOS functions CE1 address lines EA2..EA5 are pre-connected, alias images above 0x120.003F CE1 CE1, auto CE1 IOSEL memory area, nIOSEL is driven low if access inside this memory area 0 internal program memory, mapped or cache 0 DSP internal peripherals CE2 CE3 0 MEMSEL memory area, nMEMSEL is drivenn low if access inside this area SDRAM, on modules without SDRAM nSDCS is driven low if access inside this area. internal data memory bank 0 internal data memory bank 1

MAP1 (default) DSP Address 0x0000.0000..0x0000.0BFF 0x0000.0C00..0x0000.0E5F 0x0000.0E60..0x0000.0FFF 0x0000.1000..0x0000.FFFF 0x0040.0000..0x0047.FF7F 0x0047.FF80..0x0047.FFFF 0x0140.0000..0x015F.FFFF 0x0160.0000..0x0167.FFFF 0x0168.0000..0x0168.000F 0x016C.0000..0x016C.001F 0x0170.0000..0x017F.FFFF 0x0180.0000..0x01FF.FFFF 0x0200.0000..0x02FF.FFFF 0x0300.0000.. 0x03FF.FFFF 0x8000.0000.. 0x8000.7FFF 0x8000.8000.. 0x8000.FFFF Memory IPRAM 0 Wait States Description

SBSRAM Flash Memory User CPLD Module Configuration Registers UART IOSEL DSP internal peripherals MEMSEL SDRAM IDRAM

internal program mem, BIOS functions internal program mem, interrupt vectors internal program mem, BIOS functions internal program mem, 60 Kbytes free for user 0 or 1 SBSRAM, code or data, 524160 Bytes free SBSRAM, BIOS data area CE1, auto Flash Memory, direct access not possible, use BIOS functions CE1 address lines EA2..EA5 are pre-connected, alias images above 0x160.003F CE1 CE1, auto CE1 IOSEL memory area, nIOSEL is driven low if access inside this memory area 0 DSP internal peripherals CE2 CE3 0 MEMSEL memory area, nMEMSEL is drivenn low if access inside this area SDRAM, on modules without SDRAM nSDCS is driven low if access inside this area. internal data memory bank 0 internal data memory bank 1

D.SignT 2002 Doc #2.1

D.Module.C6x01
SIGNAL DESCRIPTION POWER SUPPLY Signal Pin VCC GND +AVCC AGND -AVCC A1, B32 B1, A32 C17, U1 C16, U30 C15, U31

D.SignT
Digital Signalprocessing Technology

Type PWR PWR -

Description positive power supply, 3.3V ground, 0V these signals are not connected on the D.Module.C6x01, use to route analogue supply voltage to daughter cards

DSP PERIPHERALS Signal Pin TIMER0 TIMER1 FLAG0 FLAG1 CLKS0 DAT_RX0 CLK_RX0 FS_RX0 DAT_TX0 CLK_TX0 FS_TX0 CLKS1 DAT_RX1 CLK_RX1 FS_RX1 DAT_TX1 CLK_TX1 FS_TX1 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 B25 B26 B27 B28 B29 B30 B31

Type O O I I I I I/O I/O I I/O I/O I I I/O I/O I I/O I/O

Description Timer 0 output Timer 1 output Timer 0 input Timer 1 input McBSP 0 external master clock input McBSP 0 receiver data input McBSP 0 receiver clock McBSP 0 receiver frame sync McBSP 0 transmitter data output McBSP 0 transmitter clock McBSP 0 transmitter frame sync McBSP 0 external master clock input McBSP 1 receiver data input McBSP 1 receiver clock McBSP 1 receiver frame sync McBSP 1 transmitter data output McBSP 1 transmitter clock McBSP 1 transmitter frame sync

EXTERNAL INTERRUPTS Signal Pin nINT0 nINT1 nINT2 nINT3 U3 U4 A19 A20

Type I I I I

Description on-board pull-up 10K via Interrupt Multiplexer in Module Config Register, on-board pull-up 10K via Interrupt Multiplexer in Module Config Register, on-board pull-up 10K via Interrupt Multiplexer in Module Config Register, on-board pull-up 10K

MISCELLANEOUS SIGNALS Signal Pin Type DSPCLK IN0(nSETUP) IN1 nRESIN nRESOUT UART Signal RTS TxD CTS RxD GND A7 A11 A12 A9 U7 I I I I O

Description external clock if JPOSC closed UART DSR, on-board 10K pull-up UART RI, on-board 10K pull-up debounced manual reset, on-board pull-up 10K reset output, active low NOT 5V TOLERANT! NOT 5V TOLERANT! NOT 5V TOLERANT!

Pin A2 A3 A4 A5 A6

Type O O I I PWR

Description RS232 Request To Send (Handshake), Transmit Data RS232 Clear To Send (Handshake), Receive Data RS232, RS422 Signal Ground RS422 Transmit Data inverted RS422 Receive Data inverted

D.SignT 2002 Doc #2.1

D.Module.C6x01
USER-PROGRAMMABLE CPLD Signal Pin Type PRG_IO0 PRG_IO1 PRG_IO2 PRG_IO3 PRG_IO4 PRG_IO5 PRG_IO6 PRG_IO7 PRG_IO8 PRG_IO9 PRG_IO10 PRG_IO11 PRG_IO12 PRG_IO13 PRG_IO14 PRG_IO15 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O

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Digital Signalprocessing Technology

Description user-configurable CPLD I/O user-configurable CPLD I/O user-configurable CPLD I/O user-configurable CPLD I/O user-configurable CPLD I/O user-configurable CPLD I/O user-configurable CPLD I/O user-configurable CPLD I/O user-configurable CPLD I/O user-configurable CPLD I/O user-configurable CPLD I/O user-configurable CPLD I/O user-configurable CPLD I/O user-configurable CPLD I/O user-configurable CPLD I/O user-configurable CPLD I/O

HOST PORT INTERFACE Signal Pin HD0..HD15 nHCS HHWIL HCNTL0 HCNTL1 nHRDY nHINT nHAS nHDS HRnW nHBE0 nHBE1 T15..T30 T31 T12 T13 T14 B18 B19 B20 B21 B22 B23 B24

Type I/O I I I I O O I I I I I

Description Host Port D0 .. D15 or User-CPLD I/O Host Chip Select or User-CPLD I/O Host 1st/2nd Halfword or User-CPLD I/O Host Register Select Line 0 or User-CPLD I/O Host Register Select Line 1 or User-CPLD I/O Ready to Host or User-CPLD I/O Interrupt to Host Host Address Strobe or User-CPLD I/O Host Data Strobe or User-CPLD I/O Host Read/Write Direction or User-CPLD I/O Host Byte Enable 0 or User-CPLD I/O Host Byte Enable 1 or User-CPLD I/O

EXTERNAL BUS INTERFACE Signal Pin Type D0..D15 D16..D31 D17 A0..A5 A6..A18 A19 nRD nWR nIOSEL nMEMSEL BUSCLK nWAIT SDCLK nSDRAS nSDCAS nSDWE SDA10 nSDCS nBE0..nBE3 V15..V30 U15..U30 U16 U9..U14 V2..V14 A14 U2 U5 U8 V31 U7 A10 T2 T3 T4 T5 T6 T7 T8..T11 I/O I/O I/O O O O O O O O O I O O O O O O O

Description ext. Data Bus D0 .. D15 ext. Data Bus D16 .. D31 ext. Data Bus D17 ext. Address Bus , DSP EA2 .. EA7 ext. Address Bus , DSP EA8 .. EA20 ext. Address Bus , DSP EA21 Read Strobe, active low Wrie Strobe, active low IOSEL Memory Select, active low MEMSEL Memory Select, active low DSP CLKOUT2 ext. Wait State Request, active low ext. SDRAM Clock ext. SDRAM Row Addr Strobe ext. SDRAM Column Addr Strobe ext. SDRAM Write Enable ext. SDRAM Address Line A10 ext. SDRAM Chip Select = DSP /CE3 Byte Enable 0 .. 3, active low

D.SignT 2002 Doc #2.1

D.Module.C6x01
PINOUT Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 A VCC RTS / nTxD TxD nc / nRxD RxD GND DSPCLK GND nRESIN nWAIT IN0 / nSETUP IN1 GND A19 nc nc nc nc nINT2 nINT3 TIMER0 TIMER1 FLAG0 FLAG1 CLKS0 DAT_RX0 CLK_RX0 FS_RX0 DAT_TX0 CLK_TX0 FS_TX0 GND B GND PRG_IO0 PRG_IO1 PRG_IO2 PRG_IO3 PRG_IO4 PRG_IO5 PRG_IO6 PRG_IO7 PRG_IO8 PRG_IO9 PRG_IO10 PRG_IO11 PRG_IO12 PRG_IO13 PRG_IO14 PRG_IO15 nHRDY nHINT nHAS nHDS HRnW nHBE0 nHBE1 CLKS1 DAT_RX1 CLK_RX1 FS_RX1 DAT_TX1 CLK_TX1 FS_TX1 VCC (3.3V) C T nc SDCLK nSDRAS nSDCAS nSDWE SDA10 nSDCS nBE0 nBE1 nBE2 nBE3 HHWIL HCNTL0 HCNTL1 HD0 HD1 HD2 HD3 HD4 HD5 HD6 HD7 HD8 HD9 HD10 HD11 HD12 HD13 HD14 HD15 nHCS GND U +AVCC nRD nINT0 nINT1 nWR BUSCLK nRESOUT nIOSEL A0 A1 A2 A3 A4 A5 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 -AVCC AGND V

D.SignT
Digital Signalprocessing Technology

-AVCC AGND +AVCC

nc A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 nMEMSEL GND

D.SignT 2002 Doc #2.1

D.Module.C6x01
MECHANICAL DIMENSIONS
Emulator Connector 8,89 mm max component height on top 1,59 mm max component height on bottom: 2,50 mm 4,76 mm 7,96 mm : 4,50 mm 4,85 mm

D.SignT
Digital Signalprocessing Technology

78,74 mm 2,54 mm1,27 mm 7,62 mm 2,54 mm 12,70 mm A B C

21 3, m m

53,34 mm

35,56 mm

2,54 mm 2,54 mm T U V 1 76,20 mm 83,82 mm 32

Size: Weight:

max. 85 x 59 x 15 mm 58g (2.05oz)

ELECTRICAL CHARACTERISTICS OPERATING CONDITIONS, DC PARAMETERS Supply Voltage VCC Power Consumption 3.3V +/- 5% idle 380mA, typ. 600mA, max. 2A Operating Temperature 0..+70C High Level Input Voltage min. 2V, max. VCC+0.2V Low Level Input Voltage min. -0.2V, max. 0.8V Power Consumption largely depends on the application program, i.e the amount and frequency of external bus and memory accesses and the utilisation of DSP resources. The idle power consumption is measured while the module is held in reset, the maximum value is calculated based on Texas Instruments data sheet information and experimental results.

D.SignT 2002 Doc #2.1

58,42 mm

D.Module.C6x01
TIMINGS The external bus timings are shown in the following diagrams. For Serial Port and Host Port Interface timings please refer to the Texas Instruments TMS320C6201 and TMS320C6701 data sheet. EXTERNAL BUS TIMINGS READ

D.SignT
Digital Signalprocessing Technology

nCE1, nCE2 ADDR

< 5ns < 5ns

nIOSEL nMEMSEL
TRS TRSTRB TRH

nRD DATA
to DSP TW TWAIT >5ns >0ns

nWAIT

WRITE

nCE1, nCE2 ADDR

< 5ns < 5ns

nIOSEL nMEMSEL
TWS TWSTRB TWH

nWR DATA
from DSP 0..5 ns TW TWAIT 0..1ns

nWAIT

TRS, TWS: TRH, TWH: TRSTRB, TWSTRB: TW: TWAIT:

read, write setup value programmed in CE1 rsp. CE2 Control Register read , write hold value programmed in CE1 rsp. CE2 Control Register read, write strobe value programmed in CE1 rsp. CE2 Control Register if ext. wait states should be requested, nWAIT must be driven low max. 4 * TDSP Clock - 7.5 ns after nCEx fallng edge if ext. wait states should be requested: nWAIT must be driven low for the desired strobe width

Restrictions for CE1 (nIOSEL) : TRS >= 1, TRH >= 1, TRSTRB >= 4, TWS >= 1, TWH >= 1, TWSTRB >= 4 D.SignT 2002 Doc #2.1 10

D.Module.C6x01
ORDERING INFORMATION D.Module.C6201-200-S1 D.Module.C6701-167-S1 D.Module.C6701-150-S1 Option -D0 Option -422 DS.C6000

D.SignT
Digital Signalprocessing Technology

TMDS324685C-07 XDS510pp_PLUS-JTAG SPI525

TMS320C6201 Fixed Point DSP Computer Module 200 MHz operation, 512 Kbytes SBSRAM, 2 Mbytes Flash Memory TMS320C6701 Floating Point DSP Computer Module 167 MHz operation, 512 Kbytes SBSRAM, 2 Mbytes Flash Memory as above, but 150 MHz processor speed, minimum order quantity 25 additional 16 Mbytes SDRAM RS422 UART Line Interface Development Board Support Package Support Software, BIOS license, CPLD library, Boot-Code Generation Utility, Base Board, Power Supply, User's Guide and BIOS Reference Manual Texas Instruments TMS320C6000 Code Composer Studio IDE (Code Generation Tools, Debugger, and Utilities) Spectrum Digital portable JTAG Emulator, connected via PC parallel port Spectrum Digital PCI card JTAG Emulator

ADDITIONAL OPTIONS ON VOLUME PURCHASE For volume purchase D.SignT offers customerspecific modifications of the hardware either to reduce costs through reduced functionality or to increase functionality to meet the customers application requirements. Extensive experience in custom designs and the powerful engineering tools of our development department bring your application and our DSP know how together for your solution. Please contact D.SignT directly. TECHNICAL SUPPORT Our products include free of charge technical support. You can reach the technical support by e-mail (support@dsignt.de) phone or fax.

PRICING Please ask for our current price list and volume discounts. AVAILABLITY Our standard D.Modules are available typically exstock. For special modifications or non-standard D.Modules please consult our sales department. WARRANTY All D.Modules come with a warranty of 12 month.

For additional information contact your local distributor who will also support you after your purchase or contact D.SignT directly. Distributed and supported locally by

D.SignT
Digital Signalprocessing Technology

Kane Computing Ltd 7 Theatre Court, London Road, Northwich, Cheshire, CW9 5HB, UK Tel: +44(0)1606 351006 Fax: +44(0)1606 351007/8 Email: sales@kanecomputing.com Web: www.kanecomputing.com

D.SignT 2002 Doc #2.1

11