Augusto J.

Vega
curriculum vitae

23-35 Broadway, Apt. 4G Astoria, NY 11106 H +1 (914) 481 7982 B augustojv@gmail.com

Education
2013 Ph.D. Degree in Computer Architecture, Universitat Politcnica de Catalunya, Spain.
Thesis Title: Performance and Power Optimizations in Chip Multiprocessors for ThroughputAware Computation Thesis Advisors: Prof. Alex Ramrez and Prof. Mateo Valero Grade: Summa Cum Laude ("with highest honor")

2009 M.Sc. Degree in Computer Architecture, Networks and Systems, Universitat Politcnica de Catalunya, Spain.
Thesis Title: Performance, Power and Thermal Modeling in 3D Die-Stacking Architectures Thesis Advisors: Prof. Alex Ramrez and Prof. Mateo Valero

2007 Computer Engineering Degree, Universidad de Buenos Aires, Argentina.

Thesis Title: A Framework for the Evaluation of Memory Organizations in Simultaneous Multithreading Environments Thesis Advisor: Prof. Jos Luis Hamkalo

Professional Experience
2010present Student Intern / Sta Engineer, IBM Research, Yorktown Heights, NY.
with Dr. Pradip Bose and Dr. Alper Buyuktosunoglu Developed techniques to reduce chip power consumption in multicore/manycore chips for multi-threaded applications, exploiting core folding, frequency/voltage scaling and lowpower (sleep) modes. Developed an infrastructure to evaluate these power-reduction techniques in real POWER processors. Worked on applications for Unmanned Aerial Vehicles (UAVs) to adapt them to operate under harsh conditions such as high performance requirements and tight power budgets. Worked and developed the processor-in-regle (PIR) technique which consists of computation logic embedded in a register le to accelerate parallel programs.

20072010 Junior Researcher / Resident Student, Barcelona Supercomputing Center (BSC), Spain.
with Dr. Mateo Valero and Dr. Alex Ramrez Devised a last-level cache (LLC) organization to improve bandwidth in multicore/manycore chips. Developed TaskSim, a modular CMP-architecture performance modeling tool.

20022007 Undergraduate Research Assistant, Universidad de Buenos Aires, Argentina.

with Dr. Jos Luis Hamkalo Devised a rst-level cache (L1) optimized for SMT-enabled chip multiprocessors. Developed a performance model to study rst-level caches in SMT-enabled chip multiprocessors.

20002007 Teaching Assistant, Universidad de Buenos Aires, Argentina.

Introductory and advanced undergraduate courses on computer architectures and programming. 1/4

Publications
Conference Papers
{ A. Vega, A. Buyuktosunoglu, H. Hanson, P. Bose, S. Ramani. Crank It Up or Dial It Down: Coordinated Multiprocessor Frequency and Folding Control. Under review for the 46th International Symposium on Microarchitecture (MICRO 2013). Davis, California (USA). December 2013. { A. Vega, A. Buyuktosunoglu, P. Bose. SMT-Centric Power-Aware Thread Placement in Chip Multiprocessors. In Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques (PACT 2013). Edinburgh (Scotland). September 2013. Accepted May 2013 to appear. Nominated for Best Paper. { D. Sreedhar, J. Derby, A. Vega, B. Rogers, C. Johnson, R. Montoye. Processor Architecture for Software Implementation of Multi-sector G-Rake Receivers for HSUPA Wireless Infrastructure. In Proceedings of the 38th International Conference on Acoustics, Speech, and Signal Processing (ICASSP 2013). Vancouver (Canada). May 2013. { P. Bose, A. Buyuktosunoglu, J. Darringer, M. Gupta, M. Healy, H. Jacobson, I. Nair, J. Rivers, J. Shin, A. Vega, A. Weger. Power Management of Multi-Core Chips: Challenges and Pitfalls. In Proceedings of the 2012 Conference on Design, Automation and Test in Europe (DATE 2012). Dresden (Germany). March 2012. { A. Vega, P. Bose, A. Buyuktosunoglu, J. Derby, M. Franceschini, C. Johnson, R. Montoye. Architectural Perspectives of Future Wireless Base Stations based on the IBM PowerEN Processor. In Proceedings of the 18th International Symposium on High-Performance Computer Architecture (HPCA 2012). New Orleans (USA). February 2012. { A. Rico, F. Cabarcas, C. Villavieja, M. Pavlovic, A. Vega, Y. Etsion, A. Ramrez, M. Valero. On the Simulation of Large-scale Architectures Using Multiple Application Abstraction Levels. In Proceedings of the 7th International Conference on HighPerformance and Embedded Architectures and Compilers (HIPEAC 2012). Paris (France). January 2012. { J. Derby, T. Heil, M. Franceschini, A. Krishna, R. Montoye, D. Sreedhar, A. Vega, H. Yeo, C. Johnson. Vector-Based Acceleration in the IBM PowerEN Processor To Enable Software-Dened Radio. In Proceedings of the 2011 Software Dened Radio Technical Forum (SDR 2011). Washington DC (USA). November 2011. { A. Vega, F. Cabarcas, A. Ramrez, M. Valero. Breaking the Bandwidth Wall in Chip Multiprocessors. In Proceedings of the Eleventh International Conference on Embedded Computer Systems: Architectures, MOdeling, and Simulation (SAMOS 2011). Samos (Greece). July 2011.

Journals
{ P. Tembey, A. Vega, A. Buyuktosunoglu, D. Da Silva, P. Bose. SMT switch: Software Mechanisms for Power Shifting. In IEEE Computer Architecture Letters, 1, IEEE, 2012. { V. Desmet, S. Girbal, A. Ramrez, O. Temam, A. Vega. ArchExplorer for Automatic Design Space Exploration. In IEEE Micro Special Issue: European Multicore Processing Projects. September/October 2010.
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Workshop Papers
{ A. Vega, P. Bose, A. Buyuktosunoglu. Power Management for CMP/SMT Processors: Some Decision Control Pitfalls. In Proceedings of the Third Tutorial/Workshop on Energy-Secure System Architectures (ESSA 2013). Tel Aviv (Israel). June 2013. { A. Vega, P. Bose, A. Buyuktosunoglu. Power-Aware Thread Placement in SMT/CMP Architectures. In Proceedings of the Fourth Workshop on Energy Ecient Design (WEED 2012). Portland (USA). June 2012. { A. Vega, A. Rico, F. Cabarcas, A. Ramrez, M. Valero. Comparing Last-level Cache Designs for CMP Architectures. In Proceedings of the Second International Forum on Next-Generation Multicore/Manycore Technologies (IFMT 2010). SaintMalo (France). June 2010.

Technical Reports and Other Publications

{ A. Rico, F. Cabarcas, A. Quesada, M. Pavlovic, A. Vega, C. Villavieja, Y. Etsion, A. Ramrez. Scalable Simulation of Decoupled Accelerator Architectures. In Technical Report UPC-DAC-RR-2010-14. Universitat Politcnica de Catalunya. June 2010. { A. Vega. Performance, Power and Thermal Modeling in 3D Die-Stacking Architectures. Master Thesis. Department of Computer Architecture, Universitat Politcnica de Catalunya. Barcelona (Spain). January 2009.

Posters
{ A. Vega, A. Ramrez, M. Valero. 3D Die-Stacking Architectures: State of the Art. In Advanced Computer Architecture and Compilation for Embedded Systems (ACACES 2008). LAquila (Italy), July 2008.

Patents
{ A. Vega, A. Buyuktosunoglu, P. Bose, H. Jacobson. Methods of Delaying and/or Clustering Execution to Increase Power Savings Potential. Patent application led July 2013. Patent pending. { A. Vega, A. Buyuktosunoglu, P. Bose, K. Ryu, B. Rosenburg. Method and System of Thread Consolidation and Core Folding for Power Savings in an AcceleratorEnabled Computational Node. Patent application led December 2012. Patent pending. { A. Vega, A. Buyuktosunoglu, M. Franceschini, R. Montoye, J. Derby, P. Bose. Local Computation Logic Embedded in a Register File to Accelerate Programs. Publication number US20130046955 A1. Filed 08/17/2011. Published 02/21/2013.

Research Interests
{ { { { { High performance, power- and reliability-aware computer architectures. Embedded and mobile processors. Hardware acceleration. Harsh environment-capable embedded processors. Defense/aerospace applications and unmanned aerial vehicles (UAVs). Highly parallel computing and performance analysis techniques.
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Professional Activities
{ Guest Editor, IEEE Micro Special Series on Harsh Chips, IEEE Micro Magazine, publication date: beginning in 2014. { Technology Transfer Facilitator, SRC Global Research Collaboration (GRC) Industry Liaison Program. { Organizer of the Third Tutorial/Workshop on Energy-Secure System Architectures (ESSA 2013). { Organizer of the First Workshop on Highly-Reliable Power-Ecient Embedded Designs (HARSH 2013). { Member of the Institute of Electrical and Electronics Engineers (IEEE), the IEEE Computer Society and the Association for Computing Machinery (ACM).

Skills and Abilities

Processor Architectures O/S Programming Simulation and Modeling Other Tools Languages IBM PowerPC, Intel x86, IBM Cell/B.E., MIPS Unix/Linux, Windows C/C++, Perl, Assembly (PowerPC, x86, MIPS), Java Wattch / HotLeakage (power dissipation modeling), HotSpot (thermal modeling), CACTI (cache and memory modeling), SimpleScalar, SMTSim A OProle, PAPI, SPEC and PARSEC Benchmarks, L TEX English (uent), Spanish (native), Italian (basic)

References
{ Pradip Bose Reliability- and Power-Aware Microarchitectures Group Manager (IBM) Tel. +1 914 945 3478 Email: pbose@us.ibm.com { Alper Buyuktosunoglu Research Scientist (IBM) Tel. +1 914 945 3469 Email: alperb@us.ibm.com { Mateo Valero Barcelona Supercomputing Center (BSC) Director Tel. +34 934 134 053 Email: mateo.valero@bsc.es { Alex Ramrez Heterogeneous Architectures Group Manager (BSC) Tel. +34 934 137 947 Email: alex.ramirez@bsc.es

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