(B8-6261)
020220TWJ/MH/EX BMLA004 No. 1
LV23100V
6. PLL block Allowable Operating Range at Ta=-20 to +70°C, Vss=0V
Parameter Symbol Conditions Min Typ Max Unit
Supply voltage Vdd 2.0 - 3.6 V
Input high level voltage VIH CE,CL,DI 0.7VDD - 6.0 V
Input low level voltage VIL CE,CL,DI 0 - 0.3VDD V
Vo1 DO 0 - 6.0 V
Output voltage
Vo2 BO1,BO2,AOUT 0 - 10 V
fIN1 XIN; VIN1 - 75 - kHz
fIN2 FMIN; VIN2 10 - 160 MHz
Operating frequency
fIN3 AMIN(SNS=1); VIN3 2 - 40 MHz
fIN4 AMIN(SNS=0); VIN4 0.5 - 10 MHz
Note: Due attention must be paid on leak because the XIN pin has an extremely high input impedance.
(B8-6261) No. 2
LV23100V
(B8-6261) No. 3
DI
DI
(1) IN mode
0 P0
Address
Address
(5)IFSW IFSW P5
(6)BDSW BDSW P6
1 0 0 1 0 1 0 0
0 0 0 1 0 1 0 0
(7)STSW STSW P7
(8)SD-C SDC P8
DOC0 (1)P-CTR P9
(9)DO-C DOC1 P10
DOC2 P11
Composition of DI control data (serial data input)
UL0 P12
(10)UNLOCK
UL1 P13
(11)DZ-C DZ P14
(4)O-PORT BO1SW P15
GT0 SNS
(B8-6261)
(3)IF-CTR
GT1 DVS
(12)PD-C DLC (3)IF-CTR CTE
(2)R-CTR XS 0
1 R0
TEST0 R1
(2)R-CTR
(13)TEST TEST1 R2
TEST2 R3
No. 4
LV23100V
LV23100V
Description of DI control Data
Related
No. Control block data Description
data
• Data to set the dividing number of programmable divider
Binary value with P15 assumed to be MSB. LSB varies according to DVS and SNS.
(*: don’t care)
R3 R2 R1 R0 Reference frequency
0 0 0 0 25 kHz
0 0 0 1 25
0 0 1 0 25
0 0 1 1 25
0 1 0 0 12.5
0 1 0 1 6.25
0 1 1 0 3.125
0 1 1 1 3.125
Reference 1 0 0 0 5
divider data 1 0 0 1 5
1 0 1 0 5
(2)
1 0 1 1 1
R0 to R3 1 1 0 0 3
XS 1 1 0 1 15
1 1 1 0 PLL INHIBIT + X’tal OSC STOP
1 1 1 1 PLL INHIBIT
* PLL INHIBIT
• The programmable divider and IF counter stop, with FMIN,AMIN, and IFIN
inputs being in the pull-down condition (GND), and the charge pump has the
high impedance.
• XS must be zero.
(B8-6261) No. 5
LV23100V
Related
No. Control block data Description
data
• IF counter counting start data
CTE=1: Counting start
IF counter =0: Counting reset
control data • Determines the counting time of universal counter
(3) GT1 GT0 Counting time Wait time
CTE 0 0 4 ms 3 to 4 ms
0 1 8 3 to 4
GT0,GT1 1 0 16 3 to 4
1 1 32 3 to 4
IFSW
FM/AM BAND • Data to determine the output of output port BDSW, controlling selection of BAND.
selection “Data”=0: AM
(6)
control data 1: FM
BDSW
Forced monaural • Data to determine the output of output port STSW, controlling the forced stereo
functions.
control data
(7) “Data”=0: MONO
1: STEREO
STSW
• Data to determine the output of output port SDC, controlling the FM-SD
sensitivity (at IF input).
SD sensitivity
• Data to determine the output of output ports SDC0 and SDC1, controlling the SD
control data
(8) sensitivity
SDC FM-SD sensitivity
SDC
0 38dBuV
1 48dBuV
(B8-6261) No. 6
LV23100V
Related
No. Control block data Description
data
• Data to control DO pin output
DOC2 DOC1 DOC0 DO pin condition
0 0 0 Open
0 0 1 Low when unlock is detected.
0 1 0 end-UC(See the item with asterisk below)
0 1 1 Open
1 0 0 Open
1 0 1 Low when stereo
1 1 0 Low when SDON
1 1 1 Open
UL0,UL1
∼
∼
(9) DO pin
DOC0 CTE
∼
∼
DOC1 Counting end CE: HI
Counting start
DOC2
With end-UC set and IF counter starting (CTE=0→1), DO pin opens
automatically.
At end of counting of the IF counter, DO pin goes LOW and check on counting
end can be made.
DO pin opens when serial data is entered/output (CE pin: Hi)
Note: DO pin is always in the open condition during data input (IN1 and IN2
modes, during CE: Hi period), regardless of DO pin control data (DOC0 to 2).
In the DO pin condition during data output (OUT mode, CE-Hi period), the
content of internal DO serial data is output in synchronization with CL,
regardless of DO pin control data (DOC).
• Phase error (φE) detection width selection data to judge if PLL is locked.
Phase error exceeding the detection width is judged that PLL is locked
(B8-6261) No. 7
LV23100V
Related
No. Control block data Description
data
• Data to enforce control of charge pump output
DLC Charge pump output
Charge pump
0 Normal
control data 1 Forced to LOW
(12)
In case of dead lock because of VCO oscillation stop when the VCO control
DLC
voltage (Vtune) is 0 V, it is possible to clear dead lock by setting the charge
pump output to LOW and V tune to Vcc. (Dead lock clear circuit)
• LSI test data
LSI test data TEST0
(13) TEST1 All to be set to “0”
TEST2
TEST0 to 2
All set to zero at power ON/reset
DI 0 1 0 1 0 1 0 0
SDIND
STIND
DO
C19
C18
C17
C16
C15
C14
C13
C12
C11
C10
0
UL
C9
C8
C7
C6
C5
C4
C3
C2
C1
C0
(3)IF-CTR
(1)IN-PORT
(2)UNLOCK
(B8-6261) No. 8
LV23100V
Serial data input (IN1/IN2)tSU, tHD, tEL, tES, tEH 0.75μs tLC < 0.75μs
CL: Normally HI
t EL t ES t EH
CE
CL
t SU t HD
DI B0 B1 B2 B3 A0 A1 A2 A3 P0 P1 P2 P3 R0 R1 R2 R3
t LC
Internal data
CL
t SU t HD
DI B0 B1 B2 B3 A0 A1 A2 A3 P0 P1 P2 P3 R0 R1 R2 R3
t LC
Internal data
Serial data output (OUT) tSU,tHD,tEL,tES,tEH 0.75μs tDC, tDH < 0.35μs
CL: Normally Hi
t EL t ES t EH
CE
CL
t SU t HD
DI B0 B1 B2 B3 A0 A1 A2 A3
t DC t DC t DH
DO I2 I1 UL C3 C2 C1 C0
CL
t SU t HD
DI B0 B1 B2 B3 A0 A1 A2 A3
t DC t DC t DH
DO I2 I1 UL C3 C2 C1 C0
(Note) DO pin is an Nch open drain pin, so that the data varying time (tDC and tDH) differs depending on the pull-up resistance
and substrate capacity.
(B8-6261) No. 9
LV23100V
Serial data timing
∼
∼
CE VIH
VIL
∼ ∼
∼
tCH tCL
∼
V IH VIH VIH
CL VIL VIL VIL
∼ ∼
∼
V IH VIH tEL tES tEH
∼ ∼
∼
∼ ∼
DI
∼ ∼
∼ ∼
VIL VIL
tSU tHD tDC tDC tDH
∼ ∼
∼ ∼
DO
∼ ∼
∼ ∼
tLC
∼ ∼
∼ ∼
Internal data latch Old New
∼
<< When CL stops at the “L” level >>
CE VIH
∼
∼ VIL
tCH tCL
∼
∼
CL V IH VIH VIH
V IL VIL ∼
∼
VIH VIH ∼
∼ tEL tES tEH
DI ∼
∼ ∼
∼
VIL V IL∼
tSU tHD ∼ tDC ∼
∼ tDH
DO ∼
∼ ∼
∼
∼
∼ ∼
∼ tLC
Internal data latch ∼
∼ ∼
∼ Old New
∼∼ ∼
∼
<< W hen C L stops at the H level >>
(B8-6261) No. 10
Vt=8V
1000p
SVC226
4.7u
680p
GFWB3 10k +
1p 6p 10p 10p
SA-181
+ 4.7k
0.01u
22u
0.047u
100k
CFV-206
36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19
SVC347
0.047u
BO2 BO1
GND2 Vcc2 LPF POWER ON
VDD RESET
FM AM
FM OSC OSC
RF PHASE DETECTOR REFERENCE
CHARGE PUMP DIVIDER
OSC
BUFFER
SD ST TRIG ST FF VCO
SW PROGRAMMABLE SWALLOW
DIVIDER COUNTER
(B8-6261)
RF MIX DET
AM
DET
FM FM IF UNIVERSAL
MIX IF BUFFER COUNTER
AM
IF
REG GND1 Vcc1 DECODER VSS CCB
I/F
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
3.3k
C8E-A0105 0.047u L-OUT R-OUT CE DI CL DO 10k
+ 1u 0.15u
micro-controller
10p 10u + 0.01u 0.01u
SA-164
SFULA450KU2B
0.33u
CDALA10M7GA121
SFELA10M7GA00 +
0.047u 100u
Vcc=3V
Unit
LV23100V ブロック図および応用回路例 Capacitance: F
LV23100V Block Diagram and Sample Application Circuit Resistance: Ω
No. 11
LV23100V
Vt=8V VDD=3V
1000p
SVC226
4.7u
51k
51k
680p
10k +
100k
GFWB3 1p 6p
SA-181
+ 0.01u
22u
0.047u
4.7k CFV-206
36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19
SVC347
0.047u
BO2 BO1
GND2 Vcc2 LPF POWER ON
VDD RESET
FM AM
FM OSC OSC
RF PHASE DETECTOR REFERENCE
CHARGE PUMP DIVIDER
OSC
BUFFER
SD ST TRIG ST FF VCO
SW PROGRAMMABLE SWALLOW
DIVIDER COUNTER
(B8-6261)
AM
DET
FM FM IF UNIVERSAL
MIX IF BUFFER COUNTER
AM
IF
REG GND1 Vcc1 DECODER VSS CCB
I/F
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
3.3k
0.047u 0.047u CE DI CL DO 51k
AM IN L-OUT R-OUT
+ 1u 0.15u
micro-controller
10u + 0.01u 0.01u
SA-164
51 39m
SFULA450KU2B
CDALA10M7GA001
0.33u
SFELA10M7GA00 +
0.047u 100u A
FM IF
300 0.047u Unit Vcc=3V
51
Capacitance: F
LV23100V 測定回路図
LV23100V Test Circuit Resistance: Ω
No. 12
LV23100V
LV23100V
Coil specifications (bottom view)
• FM-BPF : GFWB3 (Soshin) 76MHz to 108MHz
• FM-RF : SA-149 (Sumida) 3.6mm diameter, air core, 0.6mm wire, 4.5 T
• FM-OSC : SA-151 (Sumida) 3.6mm diameter, air core, 0.6mm wire, 3.5 T
• FM-IF Filter : SFELA10M7GA00 (Murata)
• FM-Discriminator : CDALA10M7GA121 (Murata)
• AM-OSC : SA-181 (Sumida)
S 6 - 4 37T
V.D. 3 4 pin31
3 - 1 74T
0.06UEW
2
fo=796kHz
GND 1 6 Vcc Qo 80
S L=140µH
• AM-MIX : SA-164 (Sumida)
S 1−2 122T
pin5 3 4 C.F.
4−6 9T
Vcc 2 2−3 62T
0.06UEW
1 6 GND fo=450kHz, Qo 65
S C=180pF
• AM-IF Filter : SFULA450KU2B (Murata)
• MW Bar-antenna : C8E-A0105 (Toko)
1 - 2 67T
3-4 9T
fo=796kHz
1 S1 2 3 S2 4 Qu=180min
V.D. GND Pin1 Pin2 L=260µH
(B8-6261) No. 13