Moores Law The number of transistors in an integrated circuits doubles approximately every two years (or 18 months).

General flow of IC Fabrication. 1. Wafer Preparation Silicon is purified and prepared into semiconductorgrade/electronic-grade silicon to form wafers. The ultra-high purity of semiconductor-grade silicon is obtained from multi-step process referred to as Siemens process. The cylindrical single-crystal ingot undergoes four steps including machinery operations, chemical operations, surface polishing and quality checks before being packaged as wafer. 2. Wafer fabrication The technology used in this step is CMOS technology. The major process areas are diffusion, photolithography, etching, ion implantation, thin film deposition and wafer polishing. The final output of wafer fabrication is individual die. 3. Testing/Sorting The measurement of electrical parameter on ICs at the wafer level is to verify conformance to specifications. Each individual die is probed and electrically tested to sort for good or bad chips. Two types of tests done for wafer-level electrical test are in-line parametric test (or wafer electrical test (WET)/DC test) and wafer sort (probe). 4. Assembly and packaging The chips that passed the wafer sort test undergoes final assembly and packaging. IC final assembly separates each good die from the wafer and attaches the die to a metal lead frame or substrate. IC packaging encloses the die in a protective package. There are two packaging level; the first level involves the IC and the second level is placing the IC on the circuit board. 5. Final Test Each packaged IC undergoes final electrical test.

IC Testing IC testing is one of many important steps in IC fabrication process. The test associated with the stage of IC fabrication. 1. Stage of IC manufacturing: Pre-production stage Test: IC design verification Wafer/Chip level: Wafer level Test description: Characterize, debug and verify new chip design to ensure it meets specification. 2. Stage of IC manufacturing: Wafer fabrication test stage (test1) Test: in-line parametric test Wafer/Chip level: Wafer level Test description: Production process verification test performed early in the fabrication cycle (near frontend of line) to monitor process. 3. Stage of IC manufacturing: Wafer fabrication stage (test2) Test: Wafer sort (probe) Wafer/Chip level: Wafer level Test description: Product functional test to verify each die meets product specifications. 4. Stage of IC manufacturing: Package IC (test1) Test: Burn-in reliability Wafer/Chip level: Package chip level Test description: IC powered up and test at elevated temperature to stress product to detect early failures (in some cases, reliability testing is also done at the wafer level during in-line parametric testing). 5. Stage of IC manufacturing: Packaged IC (test2) Test: Final test Wafer/Chip level: Package chip level Test description: Product functionality test suing the product specifications.

The bathtub curve in IC manufacturing

The characteristics of IC package that has to be considered in designing on mobile application: 1. Higher power density 2. Better thermal efficiency 3. Less space (smaller device) 4. Low inductance and capacitance 5. More input/output pins Two types of oxidation method

1. Infant mortality The infant mortality period is a time when the failure rate is dropping but is undesirable because a significant number of failures occurs in a short time causing early customer dissatisfaction and warranty expenses. 2. Useful life 3. Wear-out Oxidation o The different layers used to fabricate devices for IC: thermal oxides, dielectric layers, polycrystalline silicon, and metal film. Silicon dioxide and silicon nitride are dielectric materials and are used in IC processing for electrical insulation purposes and for passivation (final covering of all exposed areas of silicon). Silicon dioxide and silicon nitride also used as dopant masks, and as dielectrics in capacitors. The layers are formed by deposition or by heating the wafer at temperatures up to around 1,000oC in the presence of relevant gases. Various methods to form the oxidation layer: thermal oxidation, electrochemical anodization, plasma-enhanced chemical vapour deposition. Thermal oxidation is most important in fabrication of silicon devices. Thermal oxidation provide highest quality oxide. Gate oxide and field oxide are grown by thermal process. Thermal oxidation are rarely used in GaAs technology. Results in poor oxide quality, poor electrical isolation, poor surface protection.

Dry oxidation: Si (solid) + O2 (gas) SiO2 (solid) Wet Oxidation: Si (solid) + 2H2O (gas) SiO2 (solid) + 2H2 (gas) 1. Wet oxidation Usually done by inserting water vapor in a furnace at high temperature. High growth rate Suitable for thick oxide layer Oxide quality is lower than that of dry oxidation

2. Dry oxidation Usually done by inserting oxygen gas in furnace at high temperature. Low growth rate Produce decreasing and high quality each layer

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Two types of Etching method 1. Wet Etching Wet etching is usually to perform isotropic Wet etching is more likely to perform isotropic etching since the liquid etchant (Chemical - HF, HCL, H2SO4) can penetrate underneath the mask. 2. Dry Etching Dry etching is usually to perform anisotropic Dry etching is more likely to perform anisotropic since the beam or plasma energy (FIB, RIE, plasma) is used to pattern the mask.

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Why we do packaging? 1. Protection from the environment and handling damage. 2. Interconnection for signals into and out of the chip 3. Physical support for the chip 4. Heat dissipation IC Assembly IC assembly is the first processing step after wafer fabrication and insulation that enables the ICs to be packaged for system use. The purpose of IC assembly are: 1. To provide signal and power distribution of the packaged IC to the system 2. To provide mechanical support to fragile IC 3. To provide environment protection of the IC 4. To interconnect with the rest of the system (other ICs, passive devices, display, keyboard, sensors, etc) 5. To enable an IC to be electrically interconnected to the package and allow that IC to be handled, tested and burnt-in

Wafer electrical test (WET) and wafer probe test WET also known as in-line parametric test, performed in fabrication cycle (after metallization) to monitor process. Also referred as DC test. Wafer probe test also known as wafer sort, to test functionality of each die in a wafer. We have to conduct both test because: 1. Both tests need to be done to verify the process and functionality of the dies after undergone the fabrication process whether they meet the product specification before going to the back-end processes (assembly and packaging). 2. WET equipment consists of an automated tester designed to interface with the test structure in the wafer to sophisticated hardware and software that performed the electrical test. 3. The system includes probe card interface, wafer positioning, tester instrumentation and computer as host server.

What is the flip-chip technology? Basic Process in the fabrication of NMOS 1. 2. 3. 4. 5. Oxidation (dielectric layer) ; SiO2, nitrogen Si3N4 Doping (diffusion/ion implantation) Deposition (include epitaxial growth of thin film) Lithography (include etching) Metallization

Flip-chip is the connection of an IC to a carrier or substrate with the active face of the chip facing forward the substrate. The basic structure of flip-chip consists of an IC or chip on interconnection system and a substrate. What is the advantages and disadvantages of flip-chip technology? Advantages: a) Can give greater number of high quality I/Os b) Very low capacitance and inductance Disadvantages: a) Difficult to remove heat b) Potential thermal strain between die and package

Deep buried layer To control latch-up (reliability problem in CMOSlatch-up occurs when the parasitic transistors cause the device to turn on unintentionally leading to chip failure). To serve as impurity getter. Method: using high energy implanter ( >200 keV)

Lightly-doped drain To define the source and drain regions of the transistor (source and drain extension) Method: to do in two separate masking and implant processes.

Source and drain To form the highly doped SiO2 regions for the well that interface with the lightly doped active channel and well regions. Method: Source and drain are doped with high concentration (1020 to 1021 ions/cm2) of dopant having opposite conductivity type as the well surrounding them.

Poly-silicon gate Poly-Si gate must be doped to make it conductive Method: for traditional devices, Poly-Si gate is doped with n+ dopant for both n-channel and pchannel device prior to gate patterning Problems with electrical performance with short channel devices (sub-0.25m) To solve problem, create separate n+ gate for nchannel device and p+ gate for p-channel device. Poly-Si gate is first patterned and then doped with source or drain of each type.