Advanced Verification Topics

Bishnupriya Bhattacharya John Decker Gary Hall Nick Heaton Yaron Kashai Neyaz Khan Zeev Kirshenbaum Efrat Shneydor

Contents
Preface 1 Introduction to Metric-Driven Verification
1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 1.10 1.11 1.12 Introduction Failing to Plan = Planning to Fail Metric-Driven Verification Building Strong Testbench Foundations Simulation Isn't the Only Way Low Power isn't Just the Designer's Problem Reuse Isn't Just About Testbench Components Does Speed Matter? What About Scalability? Is Metric-Driven Verification Just for RTL Hardware? How Do I Get Up to Speed with All this New Stuff? Summary

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UVM and Metric-Driven Verification for Mixed-Signal

2.1 2.2 2.3 Why Metric-Driven Verification for Analog? Approach and Scope Planning for Analog Verification 2.3.1 Including Analog Properties 2.3.2 Verification Plan Structured for Reuse Constructing a UVM-MS Verification Environment 2.4.1 Analog Verification Blocks 2.4.2 Analog Configuration Interface 2.4.3 Threshold Crossing Monitor Architecture of a Sample Testbench

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15 16 20 20 22 23 23 24 24 25

2.4

2.5

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Contents

2.6

Collecting Coverage 2.6.1 2.6.2 2.6.3 Direct and Computed Coverage Collection Deciding on Coverage Ranges Trading Off Speed and Visibility Dealing with Configurations and Settings Generating and Driving Digital Control Comparing Two Values Triggering a Check on Control Changes Measuring Signal Timing Comparing a Value to a Threshold Checking Frequency Response Checking Input Conditions Verifying Local Invariants Limitations on Assertion Checking of Analog Properties Dealing with Different Modeling Styles Driving Clocks Resets Power-Up and Power-Down Sequences

26 27 30 30 32 32 33 38 38 40 43 45 47 49 49 50 50 50 51 51 51 51 53 54 54 55 56 57 59 61 62 63 63 64 65 65 67 69 69 70

2.7

Generating Inputs 2.7.1 2.7.2

2.8

Checking Analog Functionality 2.8.1 2.8.2 2.8.3 2.8.4 2.8.5

2.9

Using Assertions 2.9.1 2.9.2 2.9.3 2.9.4

2.10

Clocks, Resets and Power Controls 2.10.1 2.10.2 2.10.3

2.11 2.12

Analog Model Creation and Validation Integrating the Test Environment 2.12.1 2.12.2 2.12.3 2.12.4 2.12.5 2.12.6 2.12.7 Connecting the Testbench Connecting to Electrical Nodes System-Level Parameters and Timing Supporting Several Model Styles In A Single Testbench Interfacing Between Real and Electrical Signals Creating Run Scripts and Other Support Files Recommended Directory Structure Implementation of Coverage for Analog Updating the Verification Plan With Implementation Data Single Simulation Runs RegressionsRunning Multiple Test Cases Mix-and-Match SoC-Level Simulation Updating the SoC-Level Test Plan

2.13

Closing the Loop Between Regressions and Plan 2.13.1 2.13.2

2.14

Regression Runs for Analog IP 2.14.1 2.14.2

2.15

Moving Up to the SoC Level 2.15.1 2.15.2

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Advanced Verification Topics

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2.16

2.17

2.15.3 Integrating Into the SoC-Level Testbench UVM-MS Universal Verification Blocks 2.16.1 Wire Verification Component 2.16.2 Simple register UVC 2.16.3 Analog to Digital Converter (ADC) UVC 2.16.4 Digital to Analog Converter (DAC) UVC 2.16.5 Level Crossing Monitor 2.16.6 Ramp Generator and Monitor Summary

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Low-Power Verification with the UVM

3.1 Introduction 3.1.1 What is Unique about Low-Power Verification 3.1.2 Understanding the Scope of Low-Power Verification 3.1.3 Low-Power Verification Methodology 3.1.4 Understanding Low-Power Verification Understanding Low-Power Design and Verification Challenges 3.2.1 How Low-Power Implementations Are Designed Today 3.2.2 Challenges for Low-Power Verification 3.2.3 Low-Power Optimization 3.2.4 Low-Power Architectures 3.2.5 Low-Power Resources Low-Power Verification Methodology Low-Power Discovery and Verification Planning 3.4.1 Low-Power Discovery 3.4.2 Verification Planning 3.4.3 System-Level Planning 3.4.4 Hierarchical Planning 3.4.5 Domain-Level Verification Planning 3.4.6 A Note on Verifying Low-Power Structures 3.4.7 Recommendations for Designs with a Large Number of Power Modes Creating a Power-Aware UVM Environment 3.5.1 Tasks for a Low-Power Verification Environment 3.5.2 Solution: Low-Power UVC 3.5.3 UVC Monitor 3.5.4 LP Sequence Driver 3.5.5 UVM-Based Power-Aware Verification Executing the Low-Power Verification Environment 3.6.1 LP Design and Equivalency Checking 3.6.2 Low-Power Structural and Functional Checks

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97 98 99 100 102 102 102 103 104 105 Ill Ill 113 113 113 113 117 118 119 119 121 121 122 124 126 128 128 128 129

3.2

3.3 3.4

3.5

3.6

Advanced Verification Topics

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3.7

3.8

3.6.3 Requirements for Selecting a Simulator and Emulator 3.6.4 Advanced Debug and Visualizations 3.6.5 Automated Assertions and Coverage 3.6.6 Legal Power Modes and Transitions 3.6.7 Automatic Checking of Power Control Sequences 3.6.8 Verification Plan Generated from Power Intent Common Low-Power Issues 3.7.1 Power-Control Issues 3.7.2 Domain Interfaces 3.7.3 System-Level Control Summary

130 132 135 135 135 136 138 138 139 140 141

Multi-Language UVM
4.1 4.2 Overview of UVM Multi-Language UVC Requirements 4.2.1 Providing an Appropriate Configuration 4.2.2 Exporting Collected Information to Higher Levels 4.2.3 Providing Support for Driving Sequences from Other Languages 4.2.4 Providing the Foundation for Debugging of All Components 4.2.5 Optional Interfaces and Capabilities Fundamentals of Connecting e and SystemVerilog 4.3.1 Type Conversion 4.3.2 Function Calls Across Languages 4.3.3 Passing Events Across Languages Configuring Messaging e Over Class-Based SystemVerilog 4.5.1 Environment Architecture 4.5.2 Configuration 4.5.3 Generating and Injecting Stimuli 4.5.4 Monitoring and Checking SystemVerilog Class-Based over e 4.6.1 Simulation Flow in Mixed e and SystemVerilog Environments 4.6.2 Contacting Cadence for Further Information UVM SystemC Methodology in Multi-Language Environments 4.7.1 Introduction to UVM SystemC 4.7.2 Using the Library Features for Modeling and Verification 4.7.3 Connecting between Languages using TLM Ports 4.7.4 Example of SC Reference Model used in SV Verification Environment 4.7.5 Reusing SystemC Verification Components Summary

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143 146 146 146 146 146 147 147 147 150 153 154 154 155 156 160 168 171 173 173 174 174 175 182 188 191 193

4.3

4.4 4.5

4.6

4.7

4.8

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Developing Acceleratable Universal Verification Components (UVCs) 195

5.1 5.2 Introduction to UVM Acceleration 195 UVC Architecture 196 5.2.1 Standard UVC Architecture 196 5.2.2 Active Agent 196 5.2.3 Passive Agent 197 5.2.4 Acceleratable UVCs 197 UVM Acceleration Package Interfaces 201 5.3.1 uvm_accel_pipe_proxy_base Task and Function Definitions (SystemVerilog) .. .202 5.3.2 uvm_accel_pipe_proxy_base Task and Function Definitions (e) 204 SCE-MI Hardware Interface 205 5.4.1 SCE-MI Input Pipe Interface 206 5.4.2 SCE-MI Output Pipe Interface 206 Building Acceleratable UVCs in System Verilog 207 5.5.1 Data Items 207 5.5.2 Acceleratable Driver (SystemVerilog) 209 Building Acceleratable UVCs in e 215 5.6.1 Data Items 215 5.6.2 Acceleratable Driver (e) 216 Collector and Monitor 219 Summary 219

5.3

5.4

5.5

5.6

5.7 5.8

Summary

221 223 227

The Authors Index

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