International Journal of Electronics and Computer Science Engineering Available Online at www.ijecse.

org

411

ISSN- 2277-1956

Design of A Novel High Speed Dynamic Comparator with Low Power Dissipation for High Speed ADCs
Sougata Ghosh 1 ,Samraat Sharma 2 Department of Electronics and Communication Engineering 1 Assistant Professor, IFTM University, Moradabad, Uttarpradesh-244102 2 Department of Electrical Engineering 2 Assistant Professor, IFTM University, Moradabad, Uttarpradesh-244102 Email- sougata.vlsi@gmail.com , samraat3@gmail.com
1

Abstract- A new CMOS dynamic comparator using dual input single output differential amplifier as latch stage suitable for high speed analog-to-digital converters with High Speed, low power dissipation and immune to noise than the previous reported work is proposed. Back to-back inverter in the latch stage is replaced with dual-input single output differential amplifier. This topology completely removes the noise that is present in the input. The structure shows lower power dissipation and higher speed than the conventional comparators. The circuit is simulated with 1V DC supply voltage and 250 MHz clock frequency. The proposed topology is based on two cross coupled differential pairs positive feedback and switchable current sources, has a lower power dissipation, higher speed, less area, and it is shown to be very robust against transistor mismatch, noise immunity. Previous reported comparators are designed and simulated their DC response and Transient response in CadenceVirtuoso Analog Design Environment using GPDK 90nm technology. Layouts of the proposed comparator have been done in Cadence Virtuoso Layout XL Design Environment. DRC and LVS has been checked and compared with the corresponding circuits and RC extracted diagram has been generated. After that post layout simulation with 1V supply voltage has been done and compared the speed, power dissipation, Area, delay with the results before layout and the superior features of the proposed comparator are established. Keywords CMOS comparator, low power, High Speed, Analog-to-Digital Converter and Cadence

1. INTRODUCTION Comparators are most probably second most widely used electronic components after operational amplifiers in this world. Comparators are known as 1-bit analog-to digital converter and for that reason they are mostly used in large abundance in A/D converter. In the analog-to-digital conversion process, it is necessary to first sample the input. This sampled signal is then applied to a combination of comparators to determine the digital equivalent of the analog signal [16]. The conversion speed of comparator is limited by the decision making response time of the comparator. As the comparator is one which limits the speed of the converter, its optimization is of utmost importance. In todays world, where demand for portable battery operated devices is increasing, a major thrust is given towards low power methodologies for high speed applications. This reduction in power can be achieved by moving towards smaller feature size processes. However, as we move towards smaller feature size processes, the process variations and other non-idealities will greatly affect the overall performance of the device. One such application where low power dissipation, low noise ,high speed, less hysteresis, less Offset voltage are required is Analog to Digital converters for mobile and portable devices. The performance limiting blocks in such ADCs are typically inter-stage gain amplifiers and comparators. The accuracy of such comparators, which is defined by its offset, along with power consumption, speed is of keen interest in achieving overall higher performance of ADCs. In the past, pre-amplifier based comparators [1] have been used for ADC architectures such as flash and pipeline. The main drawback of preamplifier based comparators is the more offset voltage. To overcome this problem, dynamic comparators are often used that make a comparison once every clock period and require much less offset voltage. However, these dynamic comparators suffer from large power dissipation compared to pre-amplifier based comparators. The main problem with all these dynamic comparators is the output signal of the latch stage is fluctuating during clock transition. This is happening due to the presence of noise in input terminals. In this paper we have designed all type of comparators

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412 Design of A Novel High Speed Dynamic Comparator with Low Power Dissipation for High Speed ADCs

and proposed a circuit which removes the noise from the output and dissipates less power and provides high speed. Keeping these things in mind we have designed a new differential amplifier based comparator. 2. ANALYSIS OF DIFFERENT TYPE OF COMPARATORS: Table 1: INPUT SPECIFICATIONS SUPPLY VOLTAGE (VDD) 1V TECHNOLOGY INPUT VOLTAGE RANGE CLOCK FREQUENCY CLOCK RISE TIME CLOCK FALL TIME CLOCK DELAY CLOCK PULSE WIDTH TEMPARATURE REFERENCE VOLTAGE CADENCE GPDK 90 nm 0V0.9V 250 KHz 100 ps 100 ps 1 ns 2 ns 27 C 0.2V0.7V

Table 2:TRANSISTOR DIMENSIONS(m)

(In above table for Preamplifier Based Comparator[1], Latch Type Voltage Sense Amplifier[2] Double Tail Latch Type Voltage SA[3] Dynamic Comparator without Calibration [4] Double Tail Dual Rail Dynamic Latched Comp.[5])

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2.1 PREAMPLIFIER BASED COMPARATOR: 2.1.1 CIRCUIT DIAGRAM: Figure 4.1 shows the schematic (designed in Cadence) of the Preamplifier based comparator circuit. The supply voltage of this comparator is 1 V. Input voltage is .9 V and Reference voltage is .5 V. The temperature is 27C. The input specifications are specified in detail in Table 1.

Fig:1 Preamplifier Based Comparator. 2.1.2 DC ANALYSIS: Figure 2. shows the DC analysis of the preamplifier based comparator. For calculating DC analysis, both input and reference voltage is taken as the DC voltage source. DC analysis states that the above comparator works perfectly. Back-to-back NMOS transistors in preamplifier stage keep the PMOS transistors in the preamplifier from turning off.

Figure 2. DC Response of the preamplifier based comparator.

2.1.3 TRANSIENT ANALYSIS: Figure 3. shows the Transient response of the above circuit. For calculating transient response a PULSE voltage source is used as input voltage source and reference voltage source is a DC voltage source.

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414 Design of A Novel High Speed Dynamic Comparator with Low Power Dissipation for High Speed ADCs

Figure 3. Transient response of the circuit. 2.1.4 RESULTS: Offset Voltage: 64.35 mV Static Power Dissipation: 10.89 W Dynamic Power Dissipation: 72.56 W Delay: 0.3935 nS Speed: 2.54 GHz Slew Rate: 21.23 V/nS 2.2 LATCH TYPE VOLTAGE SENSE AMPLIFIER: 2.2.1 CIRCUIT DIAGRAM: Figure 4. shows the Circuit Diagram (designed in Cadence) of Latch type voltage sense amplifier. Specifications are given in Table 1. Transistor sizes are specified in Table 2. The circuit comprises of a latch stage followed by buffer stage (which is nothing but a self biased differential amplifier followed by an inverter).

Figure 4. Circuit Diagram of Latch Type Voltage Sense Amplifier.

2.2.2 DC ANALYSIS: Figure 5. shows the DC analysis of the circuit. From Figure 4.5, we can say that the comparator is working fine. Input voltage is swept from -1V to +1V and reference voltage is taken as .2 V.

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Figure 5. DC analysis of the circuit. 2.2.3 TRANSIENT ANALYSIS: Figure 6. shows the transient response of the circuit. From transient response we can conclude that output of outp( as well as outn node) node which acts as an one of the input of the output buffer stage (which is mainly comprises of a self-biased differential amplifier followed by an inverter) is distorted by the noise present in the comparator.

Figure 6. Transient response of the circuit

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416 Design of A Novel High Speed Dynamic Comparator with Low Power Dissipation for High Speed ADCs

2.2.4 RESULTS: Before Layout Simulation: Offset Voltage: 339.6 mV Dynamic Power Dissipation: 14.84 w Delay: 1.247 nS Speed: .802 GHz Slew Rate: 11.08 V/nS After Post Layout Simulation: Dynamic Power Dissipation: 16 W Delay: 1.35 nS Speed: .735 GHz Slew Rate: 18.27 V/nS

2.3 DOUBLE TAIL LATCH TYPE VOLTAGE SENSE AMPLIFIER: 2.3.1 CIRCUIT DIAGRAM:

Figure 7. Circuit Diagram of Double Tail Latch Type Voltage Sense Amplifier. 4.3.2 DC ANALYSIS: Figure 8. shows the DC Analysis graph of the circuit. Input voltage is taken as 1 V and swept from -1V to +1V. Reference Voltage is taken as .2V. From the graph we can conclude that the comparator is working fine.

Figure 8.

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4.3.3 TRANSIENT ANALYSIS: Figure 9. shows the transient analysis of the circuit. From this analysis we can say that the output of out+ node in latch stage is affected by noise and fluctuating with the clock transition as that was in the previous comparator. For the transient analysis we have taken pulse voltage source as Input stage and a dc voltage source as reference node.

Figure 9. Transient Analysis of the comparator.

2.3.4 Results: Before Layout Simulation: Offset Voltage: 259.8 mV Dynamic Power Dissipation: 127.9 W Delay: 1.745 nS Speed: .573 GHz Slew Rate: 39.85 V/nS

After Post Layout Simulation: Dynamic Power Dissipation: 145.07 W Delay: 2.52 nS Speed: .390 GHz Slew Rate: 2.16 V/nS

2.4 DYNAMIC COMPARATOR WITHOUT CALIBRATION: 2.4.1 CIRCUIT DIAGRAM: Figure 10. shows the Dynamic Comparator without Calibration (Designed in Cadence).This figure also consists of a latch followed by a output buffer stage. Specifications are given in Table 1. Transistor sizes are specified in Table 2.

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418 Design of A Novel High Speed Dynamic Comparator with Low Power Dissipation for High Speed ADCs

Figure 10. Dynamic Comparator without Calibration. 2.4.2 DC ANALYSIS:

Figure 11. DC Analysis of Comparator. Figure 11. shows the DC response of the circuit. Input voltage is taken as 1 V and swept from -1V to +1V. Reference Voltage is taken as .4V. From the graph we can conclude that the comparator is working fine. 2.4.3 TRANSIENT ANALYSIS: Figure 12. shows the transient analysis of the circuit. From this analysis we can say that the output of out+ node in latch stage is affected by noise and fluctuating with the clock transition as that was in the previous comparator. For the transient analysis we have taken pulse voltage source as Input stage and a dc voltage source as reference node.

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Figure 12. Transient Response of Comparator. 2.4.4 RESULTS:

Before Layout Simulation: Offset Voltage: 300.1 mV Dynamic Power Dissipation: 105.33 W Delay: .61 nS Speed: 1.639 GHz Slew Rate: 3.09 V/nS

After Post Layout Simulation: Dynamic Power Dissipation: 110 W Delay: 1.95 nS Speed: .570 GHz Slew Rate: 16.37 V/nS

2.5 DOUBLE-TAIL DUAL-RAIL DYNAMIC LATCHED COMPARATOR: 2.5.1 CIRCUIT DIAGRAM: Figure 13. shows the schematic diagram of the Dynamic Comparator without Calibration (designed in Cadence). This circuit also comprises of latch stage followed by buffer stage. Specifications are given in Table 1. Transistor sizes are specified in Table 2. Figure 4.13 Schematic Diagram of Double-Tail Dual-Rail Dynamic Latched Comparator.

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420 Design of A Novel High Speed Dynamic Comparator with Low Power Dissipation for High Speed ADCs

Figure 13. Schematic Diagram of Double-Tail Dual-Rail Dynamic Latched Comparator. 2.5.2 DC CHARACTERISTICS:

Figure 14. DC Characteristics of the Comparator

Figure 14. shows the DC response of the circuit. Input voltage is taken as 1V and swept from -1V to +1V. Reference Voltage is taken as .4V. From the graph we can conclude that the comparator is working fine. 2.5.3 TRANSIENT ANALYSIS: Figure 15. shows the transient analysis of the circuit. From this analysis we can say that the output of out+ node in latch stage is affected by noise and fluctuating with the clock transition as that was in the previous comparator. For the transient analysis we have taken pulse voltage source as Input stage and a dc voltage source as reference node.

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Figure 15. Transient Response of Double-Tail Dual-Rail Dynamic Latched Comparator. 2.5.4 RESULTS:

Before Layout Simulation Dynamic Power Dissipation: 57.37 W Delay: 1.49 nS Speed: .671 GHz Slew Rate: 10.77 V/Ns

After Post Layout Simulation: Dynamic Power Dissipation: 65 W Delay: 2.15 nS Speed: .460 GHz Slew Rate: 11.07 V/nS

3. PROPOSED COMPARATOR: Circuit Diagram of Proposed Comparator is shown in Figure 16. This circuit mainly is a derived version of the [5]. The back-to-back latch stage is replaced with back-to-back dual input single output differential amplifier. Differential amplifier has so many advantages over the conventional latch which nothing but an inverter. It has higher immunity to environmental noise and it rejects common mode noise or in other words it has better CMRR. Another property of differential signaling is the increase in maximum achievable voltage swings. It also provides simpler biasing and higher linearity. Here our main purpose is to eliminate the noise that is present in the latch stage and for which output is getting fluctuated with clock transition.

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422 Design of A Novel High Speed Dynamic Comparator with Low Power Dissipation for High Speed ADCs

3.1 CIRCUIT DIAGRAM OF PROPOSED COMPARATOR:

Figure 16. Schematic of the proposed comparator. The circuit diagram drawn in Cadence Virtuoso Analog Design Environment is shown in Figure 16. Figure 17. shows the DC response of the circuit.

Figure 17. DC response of the Proposed Comparator.

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Figure 18. Transient Response. Figure 18. shows the transient response of the circuit. Input specifications are mentioned in Table 1. Table 2 shows the sizes of the transistors. From transient response it is evident that the output of the buffer stage and the output of the out+ node are almost equal which was not seen in the previous comparators either.

4. RESULTS & DISCUSSIONS: To compare the performance of the proposed comparators with previous works, each circuit was simulated in Cadence virtuoso analog design environment. Technology used is gpdk 90nm technology with VDD=1V as supply voltage. The layout diagrams and RC extracted diagrams has been given in fig. Table 3 shows the result summary before post layout simulation. Table 4 shows the result summary after post layout simulation. From table 5 we can say that though proposed comparator have highest transistor count but it still consumes less power than [2], [3], [4], [5]. We can also say that from Table 3, the speed is improved with respect to [5]. from Table 4, we can say that the power dissipation of proposed comparator, after post layout simulation is increased by 31% but it is still less than [5]. After post layout simulation the speed of proposed comparator is decreased from 0.910 GHz to 0.485 GHz but is still better than that of [5].

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424 Design of A Novel High Speed Dynamic Comparator with Low Power Dissipation for High Speed ADCs

Table 3: Result summary before layout:

COMPARATORS

Preamplifier Based Comparator[1] Latch Type Voltage Sense Amplifier [2] Double Tail Latch Type Voltage SA[3] Dynamic Comparator without Calibration [4] Double Tail Dual Rail Dynamic Latched Comp.[5]

Transistor Offset Count Voltage (mV) 22 64.35 19

22 23 27

Power Delay Dissipation (nS) (W) 83.45 0.393 14.84

127.9 105.33 57.37

Speed (GHz) 2.54 0.802

0.573 1.639 0.671

Slew Rate (V/nS) 21.23 11.08

39.85 3.09 10.77

339.6
259.8 300.1 300

1.247
1.745 0.61 1.49

Table 4: Result summary after post layout simulation:

COMPARATORS

Area(m2)

Power Dissipation (W)

16

Delay (nS)
1.35

Speed (GHz)
0.735

Slew Rate (V/nS)

18.27

Latch Type Voltage Sense Amplifier [2] Double Tail Latch Type Voltage SA[3] Dynamic Comparator without Calibration [4] Double Tail Dual Rail Dynamic Latched Comp.[5]

349.08

86.24 124.23 110.24

145.07 110 65

2.52 1.95 2.15

0.390 0.510 0.460

2.16 16.37 11.07

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5. LAYOUT OF PROPOSED COMPARATOR:

6. RC EXTRACTED

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