IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO.

9, SEPTEMBER 2012

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Buck and Boost Converters With Transmission Lines

Sverker Sander, Member, IEEE
AbstractThe switch mode power conversion circuits buck, boost, and buckboost incorporate a power inductor as an energy storage device. If the power inductor in these fundamental circuits is replaced with a transmission line, new power conversion circuits will emerge. By introducing microwave properties, such as propagation delay and characteristic impedance, new functions may be feasible in the area of power conversion. Examples of such functions could be inverting and noninverting voltage polarity abilities or circuits, which share switch components between multiple output voltages reducing the number of semiconductors needed. Alternatively, the buckboost power converter circuit may give rise to new high-efciency radio circuits in the area of microwave technology. Index TermsAC-DC power converters, dcdc power converters, radio, radio frequency (RF), transmission line (TL).

I. INTRODUCTION

OWER conversion using transmission lines (TLs) as a means of dcdc, acdc, and dcac conversion has been studied [1][7] as an alternative to the use of power inductors. The electrical circuits evaluated were mainly amplier circuits adapted to perform power conversion. An energy accumulation and discharge cycle synchronous with the TLs self-resonance frequency was completed. The TL or wave propagation medium could be a coaxial cable, a printed circuit board microstrip, or built using multiple lumped inductors and capacitors forming an LC network [8]. In this paper, energy accumulation in TLs with frequencies an order of magnitude lower than their self-resonance frequency is discussed. This mode of operation may result in high-efciency power conversion, without using any amplier variants, but instead derived directly from the original buck, boost, and buck boost circuits. II. SUBSAMPLING

A. General The low-frequency properties of a TL are studied by plotting voltage and current waves against time, when a dc voltage source is applied momentarily to its input, by means of an ideal switch. Fig. 1 shows a time-space diagram where the voltage (hatched area) and current (cross-hatched area) along the length of the TL are plotted horizontally on the vertical time axis at different time instances. The reference lines, ending with black dots,

Fig. 1. Time-space diagram of a short-circuited transmission line (TL), momentarily connected to a low impedance dc source V IN D C , by means of an ideal switch S.

Manuscript received October 5, 2011; revised December 13, 2011; accepted January 31, 2012. Date of current version May 15, 2012. Recommended for publication by Associate Editor D. Maksimovic. The author is with Ericsson Power Solutions, SE-417 56 Gothenburg, Sweden (e-mail: sverker.sander@ericsson.com). Digital Object Identier 10.1109/TPEL.2012.2188044

represent zero voltage and zero current in the vertical direction. The propagation delay, i.e., the time taken for a wave to travel from the TL input to the TL output, is denoted here as td (in seconds).

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B. Time Instance t = 0 Switch S is closed at time instance t = 0, thereby connecting a dc input voltage VINDC to the TL. The initial current step i1 into the TL will be determined by the characteristic impedance Z0 and the input voltage vINTL , according to i1 = vINTL VINDC = . Z0 Z0 (1)

For example, the dc input voltage is VINDC = 10 V, and the characteristic impedance Z0 = 10 . A positive 1 A current wave, and a positive 10 V voltage wave, will consequently start to propagate into the TL. C. Time Instance t = td The waves reach the output end of the TL at time instance t = td . According to basic microwave theory, the waves are transmitted to, or reected within, the load impedance depending on the reection coefcient [11]. The load impedance ZL connected to the output end of the TL is (see Fig. 1) a perfect short circuit, thus giving ZL a value of 0 OUT = ZL Z0 . ZL + Z0 (2)
Fig. 2. Circuit diagram for the voltage-step response analysis of a transmission line TL and an inductor L .

Inserting ZL = 0 and Z0 = 10 into (2) yields OUT = 1. The voltage wave will consequently be reected with inverted polarity, while the current wave will be reected with unchanged polarity. The voltage along the TL will now start to fall back to zero volts (half completed at time instance t = 1.5td ) since the reected negative voltage wave propagating toward the TL input will be superimposed on its positive voltage tail. The reected current wave will retain its positive polarity, thus creating an increase in current amplitude to 2 A (half completed at time instance t = 1.5td ). D. Time Instance t = 2td At time instance t = 2td the current and voltage waves will reach the TL input. Frequency f5 corresponds to the fth harmonic of the square wave-shaped waveform present at the TL input, having a fundamental frequency of f1 = 1/2td . The dc voltage source VINDC in the applications discussed in this paper represents an upstream dcdc converter or a native power converter input lter. In both the cases (assuming that frequency f5 is higher than the dcdc converters control bandwidth), the output impedance ZG of those two circuits is mainly determined by the LC lters capacitors. Typically, several capacitors of the same or mixed types are parallel-coupled to give low impedance over a wide frequency band. These capacitors may for example be of electrolytic, ceramic or tantalum types. Generally, these parallel-coupled capacitors will have an absolute impedance in the milliohm range 1 + 2f5 ESL + ESR. 2f5 C (3) The absolute value of the ZG impedance is calculated using the following typical gures corresponding to 10-parallel-coupled ceramic capacitors where C = 22 F, ESL = 0.5 nH, ESR = | ZG | XC + XESL + ESR =

3 m, and f5 = 5/2td = 5 MHz. Inserting these gures into (3) gives |ZG | = 20 m. The reection coefcient of the TL input IN can now be calculated by inserting (3) into (4). The phase is neglected in (3) and the complex variable IN has no imaginary part in this example IN = ZG Z0 . ZG + Z0 (4)

Inserting the gures gives IN = (0.02 10) / (0.02 + 10) = 0.996. As noted, the value IN is close to 1, causing a second reection of the voltage and current waves in the manner described at time instance t = td . The voltage wave will be reected with inverted polarity, tting into the positive dc voltage VINDC present at the TL input. The current wave will be reected a second time with unchanged polarity, thus creating an increase in current amplitude to 3 A (half completed at time instance t = 2.5td ). This is an imprint of the initial current step (1), but with doubled amplitude i2 = 2vINTL 2VINDC = . Z0 Z0 (5)

Assuming the TL to be lossless, the reections described earlier at t = td and t = 2td will continue to take place with td time intervals. E. Comparison of TL and Inductor Input Currents The operation described earlier, i.e., the momentary connection of a low impedance dc source to a TL short-circuited at its far end, is now analyzed a second time but with emphasis on the input current, rather than observing the inherent waves propagating inside the TL. Fig. 2 shows two circuits, the rst incorporating a TL and the second an inductor L which are compared with respect to input currents. Switches STL and SL are closed at t = 0, thus connecting the dc input voltage source VINDC to the TL, and inductor L , respectively, as seen in Fig. 3(a). By continuously plotting the current at the leftmost position along the TL in Fig. 1, a staircase shaped slope is obtained for iTL as presented in Fig. 3(b) (solid line). The current iTL

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Fig. 4. Circuit diagram for the description of energy accumulation and discharge into a load synchronous to the TLs self-resonance frequency.

Fig. 3. Accumulation of energy by using subsampling mode. (a) Switch state for switches ST L (solid line) and SL (dotted line). (b) Input current into TL iT L (solid line) and inductor iL (dotted line).

increases in amplitude at discrete time points distributed with intervals of 2td length, while the inductor current iL (dotted line) increases continuously. From a low frequency perspective, i.e., during a number of reections, the TL can be modeled as an inductor L . The inductance value of such model can be calculated using the formula L =dl (6)
Fig. 5. Energy accumulation and discharge into the substantially capacitive load X L D by using oversampling mode. (a) Switch state for switches SA (solid line) and SB (dotted line). (b) Current through switch SA iS A (solid line) and switch SB iS B (dotted line).

where d is the TL length in meters (m) and l is the inductance per meter (H/m). If the TL is designed with multiple lumped inductors and capacitors forming an LC network, the inductance value of such model can be calculated using the formula L =N L (7)

where N is the integer number of LC elements and L is the inductance value of each LC element. The operation of accumulating energy in (or discharging energy from) a TL over a time interval exceeding 2td in length is referred to, in this paper, as subsampling. III. OVERSAMPLING The option of accumulating and discharging energy synchronous to one of the TLs self-resonance frequencies is called oversampling mode in this paper. To visualize this mode of operation, a second switch SB is connected to an arbitrary load XLD as shown in Fig. 4. Energy is accumulated in the TL by briey turning ON switch SA as shown in Fig. 5(a). A current and a voltage wave will consequently start to propagate into the TL. At time instance t = td , the waves are totally reected in the TLs short-circuited output

end. At time instance t = 2td , the current and voltage waves will reach the TL input and switch SB is turned ON, thus partially or totally discharging the energy into the load XLD . Switch SA must be turned OFF before time instance t = 2td to avoid cross conduction with switch SB . The energy accumulation interval TAccOVS is consequently limited to less than 2td in length as shown in Fig. 5(b). Voltage conversion of the input voltage VINDC to a different output voltage vOUT cannot be performed by controlling the current uctuation with the low-frequency inductance L as depicted in Fig 3. On the contrary, the input to output voltage conversion in oversampling mode is not effectuated until the waves reach a mismatched load XLD (alternatively, no voltage conversion will occur at all if load XLD is perfectly matched to Z0 ). The current uctuation in oversampling mode is controlled by producing numerous reections back and forth between the TLs input and output ends, generating losses in the TLs resistive elements.

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Fig. 6. Accumulation of energy using mixed sub- and oversampling mode. (a) Switch state for switches ST L (solid line) and SL (dotted line). (b) Input current into TL iT L (solid line) and inductor L iL (dotted line). TABLE I COMPARISON OF OPERATION MODES

IV. MIXED SUB- AND OVERSAMPLING The option of operating switch STL synchronous with one of the TLs self-resonance frequencies, without the transitions from TL energy accumulation to energy discharge or vice versa, is called mixed sub- and oversampling mode. The switch state and current waveforms in Fig. 6 again refer to the circuit diagram presented in Fig. 2. One of the TLs resonance frequencies is excited, but contrary to oversampling mode, the resonance frequency is used for energy accumulation during several reections, again controlling the current uctuation by low-frequency inductance L . To summarize the three modes of operation described in Sections IIIV, a comparison of the energy accumulation interval lengths (TAccSUS , TAccOVS , and TAccM SO in Figs. 3, 5, and 6, respectively) is provided in Table I. V. VARIANT FORMATION New power conversion circuits can be derived depending on the mode of operation. To distinguish circuits using a wave propagation medium from their inductor-based counterparts, the prex prime is added before the circuit name, e.g., buck

becomes prime buck. Fig. 7 compiles variant formation in selection, where each column shows buck (U), boost (O), and buckboost (B) derived circuits, respectively. Four modes of operation are listed vertically in the following order: subsampling (s), oversampling (o), alternating sub- and oversampling (a), and mixed sub- and oversampling (m). The capital and lowercase letters in brackets are used to form reference numbers for the different prime-power conversion circuits in Fig. 7. A numerical series is assigned to all circuits sharing the same topology (U, O, or B) and mode (s, o, a, or m) thus substantially reecting the circuits complexity. Power conversion is possible using subsampling solely, but voltage and current waves will reside in the TL without introducing any new circuit options or features [9]. The number of circuits using subsampling is therefore just three (Us1, Os1, and Bs1). When using oversampling, new circuit formations are possible. The drawback of using oversampling mode solely is that voltage conversion is effectuated in the mismatched load, producing numerous reections that generate losses as described in Section III. However, features created in this mode reappear in mixed sub- and oversampling modes and in these cases are feasible with high power conversion efciency. As an example, the short-circuited end of the TL in Bo1 can be left open, thus creating circuit Bo2. The Bo1 circuit will invert the input dc voltage polarity, in the same manner as in the buck boost converter. However, because the voltage waves will be reected with unchanged polarity in an open termination, Bo2 will provide noninverting power conversion. This feature can be further controlled by adding a third switch element, located at the TLs far end, as shown in circuit Bo5. The output voltage can consequently be controlled to obtain dcac, acdc, or acac power conversion. Oversampling also introduces the possibility of sharing switch elements between multiple output voltages (Uo3, Oo2, Bo3, and Bo4). Two independently controlled output voltages, which are higher than the input voltage, normally require two boost converters incorporating a total of four semiconductors (two switches and two diodes). Circuit Oo2 can perform the same task with just three semiconductors since the low side switch (and common TL) are used by both output voltages. The third mode is obtained by sequentially alternating suband oversampling modes. As an example, energy can be accumulated in the Ba1 circuit TL over a long (e.g., T = 10td ) subsampling interval, directly followed by a voltage wave polarity change effected by opening the low side switch briey during an oversampling interval (T = 2td ), followed in turn by an energy discharge into the output capacitor during a second subsampling interval (e.g., T = 20td ). This type of operation may be used in, for example, acdc conversion, where the polarity changing feature recties the input ac voltage. Circuits Oa1, Ba2, Ba3, and Ba4 represent prime boost and prime buck boost pulsed amplier circuits. The output impedance of these circuits can be determined by the characteristic impedance of the TL by omitting the original converters output capacitor, and can therefore be matched to dened load impedances. A detailed description of circuit Oa1 can be found in Section VI. The low side switch may also be used to generate radio carriers (Ba5,

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TABLE II COMPONENTS FOR PULSED AMPLIFIER

Ba6), thus creating a simple yet highly efcient circuit forming a complete pulsed radio transmitter [9]. For this reason, the loads are represented by antennae symbols. The fourth mode is obtained by simultaneously mixing suband oversampling modes as previously described in Section IV [10]. A detailed description of circuit Om2 can be found in Section VII. The circuit types listed under alternating sub- and oversampling mode and mixed sub- and oversampling mode can be used to create efcient power converters and some of them may nd practical applications. Fig. 7 shows a selection of prime-power conversion circuits. The list can be expanded by introducing multiple TLs (i.e., creating prime single-ended primary-inductance converter or prime Cuk circuits) or isolated variants can be created by replacing each inductor in an LC network TL with a miniature core transformer, or using coreless microstrip transformers [6]. VI. PULSED AMPLIFIER EXAMPLE A. Simulation Verication The prime boost circuit Oa1, presented in Fig. 7, is simulated in this section by means of a lumped TL designed using 40 discrete LC elements. The main components are listed in Table II. Inductor models include dc resistance and parallel stray capacitance derived from the inductor self-resonance frequency. Capacitor models include equivalent series inductance (ESL) and equivalent series resistance (ESR). The circuit, detailed in Fig. 8, is operated in alternating suband oversampling mode. This circuit can be used in amplier applications where the load impedance R is dened and giving efciencies close to conventional power converters. The circuit generates a pulsed output voltage that is, for example, applicable in radar transmitters where RF signals are amplitude-modulated according to the systems pulse repetition frequency (PRF). A continuous modulated output voltage can be achieved by parallel coupling of multiple Ba2 circuits, shown in Fig. 7, as in a conventional multiphase power converter. A continuous modulated output voltage is, for example, applicable in envelope tracking radio transmitters where RF signals are amplitude-modulated to carry information.

Fig. 7.

Variant formation derived from buck, boost, and buckboost circuits.

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Fig. 8. Principal circuit diagram of a prime boost circuit with the device under test marked with a dashed line.

Fig. 10. Simulation of two modulation cycles for the prime boost circuit shown in Fig. 8. v G S A : gate voltage for switch SA ; v G S B : gate voltage for switch SB ; and v O U TA : output voltage. Time scale 2 s/div.

sum of the power stage PINPwSt and driver PINDRV input power PIN = PINPwSt + PINDRV (8)

and the power stage efciency is calculated by excluding the driver input power PwSt = POUT . PINPwSt (9)

The simulated power stage efciency is PwSt = 97%. B. Experimental Verication A prototype board was manufactured using the lumped TL components listed in Table II while switches SA and SB were implemented using Inneon IPB027N10N3G NFET 100 V. The switch turn ON and turn OFF times should preferably be fractions of the TLs propagation delay td in order to utilize its microwave properties. Using a lumped TL enables long propagation delay, thereby reducing requirements on the switch component, compared to if an actual TL was used. For maximum efciency, the external load resistance R was optimized to 12.8 . The divergence from the theoretical Z0 of 13.4 was mainly due to inductor L tolerances (20%). A photo of the board is shown in Fig. 11. A measurement is shown in Fig. 12. The circuit converts a +10 V dc input voltage into a pulsed output voltage with three discrete levels of approximately 10, 20, and 30 V, respectively, with a PRF of 272 kHz. The power parameters were measured to be PINPwSt = 5.59 W, PINDRV = 222 mW, and POUT = 5.20 W when recorded over more than ten modulation cycles. The efciency was 89.5% and the power stage efciency PwSt = 93.0%.

Fig. 9. Switch operation, TL input current iT L IN , TL output current iT L O U T , and output voltage v O U T plotted versus time.

A typical operation cycle is shown in Fig. 9. Switch SA is turned ON at t = 0 while the load mute switch SB remains in the ON state. Energy is accumulated during a subsampling interval (detailed in Section II) of 6td length. Switch SB is turned OFF at t = 5td and the energy in the TL is completely discharged into the matched load R during an oversampling interval. The amplitude of the output voltage pulse vOUT is determined by the accumulation subsampling interval length, while its duration is constant and equal to 2td . A modulation cycle with varying pulse amplitudes can be created by alternating the accumulation subsampling interval length. A simulation where three different amplitudes are generated is shown in Fig. 10. The circuits input power PIN is the

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Fig. 13. Principal circuit diagram of a prime boost converter with two individually controlled output voltages. Fig. 11. Photo of the prime boost prototype board. The lumped TL is visible on the right-hand side, while the drivers and switches, SA and SB , are located on each side of the lumped TL. The board measures 12 cm 18 cm.

Fig. 12. (a) Measured gate-source voltage for switch SA . (v G S A : 10 V/div). (b) Gate-source voltage for switch SB . (v G S B : 10 V/div.) (c) Output voltage v O U T 20 V/div with a time scale of 2 s/div. One modulation cycle, including three discrete voltage levels, is repeated twice. Note that the output voltage pulses increase in amplitude when preceded by longer energy accumulation subsampling intervals.

VII. DCDC CONVERTER EXAMPLE The prime boost circuit Om2 presented in Fig. 7 is simulated here with the components listed in Table II. However, the number of LC elements N is increased to 50, producing a propagation delay of 374 ns. The circuit is operated in mixed sub- and oversampling mode to perform dcdc conversion. Achieving two individually controlled stepped up output voltages normally requires two boost converters, including two switches and two rectiers, giving a total of four semiconductors. In the simulation, the same function is performed using only three semiconductors. The prime boost principal circuit diagram is shown in Fig. 13. Each voltage output (VOUTA , VOUTB ) has its own dedicated synchronous rectier (SA , SB ), but both output voltages share one common low side switch SC and TL. Note that this type of circuit will be unable to operate if switches SA and SB are designed using switches with parallel body diodes, such as FETs. The load resistors RA and RB are of equal value and set to 20 each. The start up operation cycle is shown in Fig. 14. Each output voltage has a dedicated time slot (marked with digits 1 and 2 in Fig. 14) where the common low side switch SC , and the common TL, can be used independently for energy accumulation.

Fig. 14. Simulated start up sequence of prime boost circuit shown in Fig. 13. v G S C : gate voltage for switch SC ; v G S A : gate voltage for switch SA ; v G S B : gate voltage for switch SB ; iS C : current in switch SC ; v O U TA : output voltage A; and v O U T B output voltage B. Time scale 1 s/div. M B = 4.

Note the linearly increasing peaks of the iSC current waveform reecting the TLs low-frequency inductive properties. This enables operation of circuit Om2 with a power stage efciency close to a boost converters power stage efciency (not possible with circuit Oo2 operated in oversampling mode). The simulation shown in Fig. 14 was run until a steady state was detected and the dc output voltages were then recorded.

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Fig. 15. Simulated dc output voltages V O U TA (square) and V O U T B (diamond) versus number of accumulation time slots used for channel B. The input dc voltage V IN (dot) is constant and set to 5 V.

This procedure was then repeated while stepping the number of energy accumulation time slots used for channel B MB from two to eight. The result is shown in Fig. 15. The output voltage VOUTB increases while output voltage VOUTA is substantially unaffected. The simulated maximum power stage efciency (appearing at MB = 8) is PwSt = 96%. REFERENCES
[1] S. Djuki c, D. Maksimovi c, and Z. Popovi c, A planar 4.5-GHz DC-DC power converter, IEEE Trans. Microw. Theory Tech., vol. 47, no. 8, pp. 14571460, Aug. 1999. [2] J. W. Phinney, Multi-resonant passive components for power conversion, Ph.D. dissertation, Dept. Elect. Eng. and Comput. Sci., Laboratory Electromagn. and Electron. Syst., Massachusetts Inst. Technol., Cambridge, 2005.

[3] J. W. Phinney, D. J. Perreault, and J. H. Lang, Radio-frequency inverters with transmission-line input networks, IEEE Trans. Power Electron., vol. 22, no. 4, pp. 11541161, Jul. 2007. [4] J. M. Rivas, R. S. Wahby, J. S. Shafran, and David J. Perreault, New architectures for radio-frequency DC-DC power conversion, IEEE Trans. Power Electron., vol. 21, no. 2, pp. 380393, Mar. 2006. [5] R. S. Wahby, Radio frequency rectiers for DCDC power conversion, M.S. thesis, Dept. Elect. Eng. and Comput. Sci., Massachusets Inst. Technol., Cambridge, 2002. [6] P. A. Dalal, H. Y. Yang, and C. Q. Lee, High frequency transmission line transformer for DC/DC converters, in Proc. 26th Annu. IEEE Power Electron. Spec. Conf. Rec., 1995, vol. 2, pp. 671677. [7] J. Shuai and F. Z. Peng, Transmission-line theory based distributed Zsource networks for power conversion, in Proc. 26th Annu. IEEE Appl. Power Electron. Conf. Expo., 2011, pp. 11381145. [8] J. W. Phinney, D. J. Perreault, and J. H. Lang, Synthesis of lumped transmission-line analogs, IEEE Trans. Power Electron., vol. 22, no. 4, pp. 15311542, Jul. 2007. [9] S. Sander, Sub sampling electrical power conversion, PCT Patent application PCT/SE2008/051551, Dec. 2008. [10] S. Sander, Mixed sub- and over sampling power conversion, PCT Patent Appl. PCT/EP2010/058258, Jun. 2010. [11] P. R. Karmel, G. D. Colef, and R. L. Camisa, Introduction to Electromagnetic and Microwave Engineering. New York: Wiley, 1998.

Sverker Sander (M11) received the B.S. degree in electrical engineering from the University of Chalmers, Gothenburg, Sweden, in 1997. He joined Ericsson Microwave Systems in 1997 where he later developed GHz multichip modules (MCM) for wide band electronic support measure (ESM) applications. Since 2004, he has been with Ericsson Power Solutions, Gothenburg, developing dc power systems for radio base stations (RBS). He holds more than 10 patent applications. His current research interests includes power conversion utilizing transmission lines.