RAJALAKSHMI ENGINEEERING COLLEGE THANDALAM DEPARTMENT OF ECE LESSON PLAN SUBJECT: DIGITAL ELECTRONICS CLASS: II YEAR ECE A AIM

To learn the basic methods used to design digital circuits and to provide the fundamental concepts used in the design of digital systems. OBJECTIVES To introduce basic postulates of Boolean algebra and shows the correlation between Boolean expressions To introduce the methods for simplifying Boolean expressions To outline the formal procedures for the analysis and design of combinational circuits and sequential circuits To introduce the concept of memories and programmable logic devices. To illustrate the concept of synchronous and asynchronous sequential circuits TEXT BOOKS T1-M. Morris Mano, Digital Design, 3 rd Edition, Prentice Hall of India Pvt. Ltd., 2003 / Pearson Education (Singapore) Pvt. Ltd., New Delhi, 2003. T2-S. Salivahanan and S. Arivazhagan, Digital Circuits and Design, 3 rd Edition., Vikas Publishing House Pvt. Ltd, New Delhi, 2006 REFERENCES 1. 2. 3. 4. John F.Wakerly, Digital Design, Fourth Edition, Pearson/PHI, 2006 John.M Yarbrough, Digital Logic Applications and Design, Thomson Learning, 2002. Charles H.Roth. Fundamentals of Logic Design, Thomson Learning, 2003. Donald P.Leach and Albert Paul Malvino, Digital Principles and Applications, 6 th Edition, TMH, 2003. 5. William H. Gothmann, Digital Electronics, 2nd Edition, PHI, 1982. 6. Thomas L. Floyd, Digital Fundamentals, 8th Edition, Pearson Education Inc, New Delhi, 2003 Donald D.Givone, Digital Principles and Design, TMH, 2003 SUBJECT CODE: 147302

FACULTY NAME/DESIGNATION: Mrs.J.Joselin Jeya Sheela

SI.no 1

Date

Period

Topics to be covered

No.of hours required 1

Text book page no. T1-33-40 T2-41-45

UNIT I -NUMBER SYSTEMS Boolean postulates and laws De-Morgans Theorem- Principle of Duality

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Boolean expression Minimization of Boolean expressions Minterm Maxterm Sum of Products (SOP) Product of Sums (POS) Karnaugh map Minimization Dont care conditions Quine-McCluskey method of minimization AND, OR, NOT, NAND, NOR, Exclusive OR and Exclusive NOR Implementations of Logic Functions using gates, NAND, NOR implementation Multi level gate implementations Multi output gate implementations TTL and CMOS Logic and their characteristics Tristate gates. UNIT II COMBINATIONAL CIRCUITS Design procedure Half adder Full Adder Half subtractor Full subtractor Parallel binary adder, parallel binary Subtractor Fast Adder Carry Look Ahead adder Serial Adder/Subtractor BCD adder Binary Multiplier Binary Divider Multiplexer/ Demultiplexer Encoder / decoder Parity checker, Parity generator Code converters

2 1 2 1 2 1

T1-40 T2-45-50 T1-50 T2-51-56 T1-64 T2-57-65 T1-76 T2-65-67 T2-67-72 T1-54 T2-77-89 T1-82-94 T2-84-95 T2-99-108 T2-108-110 T1-410427,151 T2-121-135, 145-147 T1-111-129 T2-161-168 T1-122-126 T2-168-175

9 10 11

1 1 2

12

13

14 15 16 17 18 19 20

1 1 1 2 2 1 2

T2-171-178 T1-129R1-178 T1-131 T2-181,184 T1-141-146 T2-187-204 T1-134-141 T2-220227,205-212 T2-227 T2-233-242

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Magnitude Comparator UNIT III - SEQUENTIAL CIRCUITS Latches,Flip flops SR, JK, T, D Characteristic table and equation Application table Master slave Flip flop Edge triggering Level Triggering Realization of one flip flopusing other flipflops Serial adder/ subtractor Asynchronous Ripple or serial counter Asynchronous Up/Down counter Synchronous counters Synchronous Up/Down counters Programmable counters Design of Synchronous counters: state diagramState table State minimization State assignment, Excitation table and maps-Circuit implementation Modulo n counter Register shift registers, Universal shift register Shift counters Ring counters. Sequence generators UNIT IV MEMORY DEVICES Classification of memories ROM ROM organization PROM EPROM EEPROM EAPROM RAM RAM organization Write operation Read operation Memory cycle - Timing wave forms Memory decoding memory expansion

1 1

T1-133 T2-242-246 T1-167-180 T2-255-268 T1-174,456 T2-276-277 T1-173 T2-270-275 T2-277-286 T2-177 T1-227-232 T2-293-306 T2-304 T1-232 T2-306 T2-324 notes T1-232 T2-312

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1 1 1 1 1 1 1 1 1 1

33 34 35 36 37

1 1 1 1 2

T1-239R1-311 T1-217-229 T2-345-358 T1-241 T2-368,362 T2-373 T1-256 T1-270 T2-392,401, 406,409 T1-256 T2-386,410 T1-260-261 T1-262 T2-423, 428

38

39 40

1 1

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42 43 44 45

46 47 48 49

50 51 52 53 54

Static RAM Cell2 T2-411-418 Bipolar RAM cell MOSFET RAM cell Dynamic RAM cell Programmable Logic 2 T1-275-280 Devices rogrammable T2-429,432 Logic Array (PLA) Programmable Array 2 T1-280 Logic (PAL) T2-440 Field Programmable 1 T1-287 Gate Arrays (FPGA) T2-443 Implementation of 2 T1-144 combinational logic T2-195, circuits using ROM, 398,440, 435 PLA, PAL UNIT V SYNCHRONOUS AND AYNCHRONOUS SEQUENTIAL CIRCUITS Synchronous Sequential 1 T2-453 Circuits: General Model Classification Design 2 T1-299 Use of Algorithmic T2-454,469State Machine 477 Analysisof Synchronous 2 T1-203 Sequential Circuits T2-486 Asynchronous 2 T1-344 Sequential Circuits: T2-496 Design of fundamental mode circuit pulse mode circuits 1 T2-507 Incompletely specified 1 T2-520 State Machines Problems in 2 T1-349Asynchronous Circuits 352,379-384 T2-521-523 Design of Hazard Free 1 T1-381 Switching circuits T2-525 Design of 3 T1-99,147Combinational and 160,190-198 Sequential circuits using VERILOG

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HOD/ECE