ECEN 3233 Digital Logic Design Spring 2011 Exam 2 50 minutes

WRITE YOUR NAME HERE ______DR J._______________

All questions must be answered on test paper!

1. (25 pts) A 4 bit counter (CD4CE), an AND gate (AND2) and a clocked D register or latch are provided. Clock (CLK) and D_input inputs are shown below. Draw the waveforms for the output Q_output when the clocked element is a level high (1) sensitive latch, or when the clocked element is positive (rising) edge sensitive register. Assume that the Q[3:0] are initially set to 1011, and Q_output is initially at 0.

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CLK 1100 1101 1110 1111 0000

1011 D_input

t Q_output level high (1) sensitive latch

t Q_output positive edge sensitive register

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3. (27 pts) Pete has managed to download a Verilog code from an alien mother ship. The aliens use a 0.5 Hz clock to run their Nexys2 FPGA board. Assume that new input patterns are applied to the rising edge of each clock cycle (t = 1, 3, 5, 7 s); find the outputs at each falling edge (t = 2, 4, 6, 8 s). Assume counter = 0 at t = 0 s.

module secretalienstuff (d, g, p, a, b, c, clk, S); output d, g, p; input a, b, c, clk; input [2:0] S; t (s) reg d, g, p, cint, bint, counter; always @(posedge clk) begin bint = S[0] ^ b; g = a & bint; p = a ^ bint; cint = S[1] & c; counter = counter + 1;

0.5 2 2.5 4 4.5 6

a 0 0 0

b 1 1 1

c 1 0 1

S[2:0] 110 111

d 1 1

g 0 0 0

p 1 0 1

010 1

if ( S[2] == 0 && counter > 1 ) begin d = p ^ cint; end else if ( S[2] == 1 ) begin if ( (S[1] == 0) & (S[0] == 0) ) begin d = a & b; end else if ( (S[1] == 0) & (S[0] == 1) ) begin d = ~ (a & b); end else if ( (S[1] == 1) & (S[0] == 0) ) begin d = a | b; end end end endmodule Page 3 of 5

3. (23 pts) Pete really wants to impress his boss. He needs to design a FSM to test his robot on the Oklahoma State University campus. Pete controls his robot wirelessly and his robot moves according to the information. Pete chooses six locations on campus and assigns each location with a state in 3-bit binary representation: Engineering North/EN (000), Engineering South/ES (001), Library (010), ATRC (011), Student Union/SU (100), and Cafeteria (101). Petes robot receives either logic 0 or logic 1 in order to travel to the next destination as specified below. Petes robot always starts off at Engineering North and your FSM should output its current location. Engineering North/EN (000): Engineering South/ES (001): Library (010): ATRC (011): Student Union/SU (100): Cafeteria (101): If 0, stay at EN. If 0, move to ATRC. If 0, move to SU. If 0, stay at ATRC. If 0, stay at SU. If 0, move to Library. If 1, move to ES. If 1, move to Library. If 1, move to Cafeteria. If 1, move to Library. If 1, move to EN. If 1, stay at Cafeteria

a. (18 pts) Draw the state transition diagram for this FSM.
0 EN 000 1 ES 001 0 1 1 0 AT RC 011 1 SU 100 0 0 LIB 010 1 0 CAF E 101 1

b. (2.5 pts) If Pete permanently transmits a sequence of ones (111111 ), where will his robot end up? Cafeteria c. (2.5 pts) If Pete permanently transmits a sequence of 10s (101010 ), which location(s) will it never visit? Cafeteria
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4. (25 pts) Design a Verilog module for Petes FSM (Problem #3). Use the schematic shown below as a reference for the inputs and outputs. When RESET is asserted, the robot needs to go back to Engineering North (000). GOTO RESET CLK

Robot

LOCATION (LOC)

module robot (GOTO, RESET, CLK, LOC) input GOTO, RESET, CLK; output [2:0] LOC; reg [2:0] LOC; always @(posedge CLK) begin if (RESET == 1) LOC = 3b000; else case (LOC) default : LOC = 3b000; 3b000: LOC = GOTO ? 3b001 : 3b000; 3b001: LOC = GOTO ? 3b010 : 3b011; 3b010: LOC = GOTO ? 3b101 : 3b100; 3b011: LOC = GOTO ? 3b010 : 3b011; 3b100: LOC = GOTO ? 3b000 : 3b100; 3b101: LOC = GOTO ? 3b101 : 3b010; endcase end endmodule

// Note // 3b000: LOC = GOTO ? 3b001 : 3b000; // Refer to page 175, Example 4.5 in your textbook

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