4 BIT MAGNITUDE COMPARATOR

Aim: To implement 4 Bit magnitude comparator using cpld XC9536

Implement Constraint File (.ucf)

NET "equal" LOC = "p37";

NET "greater" LOC = "p36";
NET "less" LOC = "p35";
NET "num1<0>" LOC = "p26";
NET "num1<1>" LOC = "p25";
NET "num1<2>" LOC = "p24";
NET "num1<3>" LOC = "p22";
NET "num2<0>" LOC = "p20";
NET "num2<1>" LOC = "p19";
NET "num2<2>" LOC = "p18";
NET "num2<3>" LOC = "p14";

Synthesis Report

Release 5.2i - xst F.28

Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to __projnav
CPU : 0.00 / 3.53 s | Elapsed : 0.00 / 2.00 s

--> Parameter xsthdpdir set to ./xst

CPU : 0.00 / 3.53 s | Elapsed : 0.00 / 2.00 s

--> Reading design: compare.prj

TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) HDL Analysis
4) HDL Synthesis
4.1) HDL Synthesis Report
5) Low Level Synthesis
6) Final Report

=========================================================================
*

Synthesis Options Summary

=========================================================================
---- Source Parameters
Input File Name
Input Format

: compare.prj
: VHDL

Ignore Synthesis Constraint File : NO

---- Target Parameters

Output File Name

: compare

Output Format

: NGC

Target Device

: xc9500

---- Source Options

Entity Name

: compare

Automatic FSM Extraction

: YES

FSM Encoding Algorithm

: Auto

Mux Extraction
Resource Sharing

: YES
: YES

Complex Clock Enable Extraction : YES

---- Target Options

Add IO Buffers

: YES

Equivalent register Removal

MACRO Preserve

: YES
: YES

XOR Preserve

: YES

---- General Options

Optimization Criterion
Optimization Effort
Keep Hierarchy

: Speed
:1
: YES

RTL Output

: Yes

Hierarchy Separator

:_

Bus Delimiter

: <>

Case Specifier

: lower

---- Other Options

cross_clock_analysis
wysiwyg

: NO
: NO

=========================================================================

=========================================================================
*

HDL Compilation

=========================================================================
Compiling vhdl file C:/Xilinx/bin/shifrt/4bitcomparator.vhd in Library work.
Entity <compare> (Architecture <behavioral>) compiled.

=========================================================================

HDL Analysis

=========================================================================

Analyzing Entity <compare> (Architecture <behavioral>).

Entity <compare> analyzed. Unit <compare> generated.

=========================================================================
*

HDL Synthesis

=========================================================================

Synthesizing Unit <compare>.

Related source file is C:/Xilinx/bin/shifrt/4bitcomparator.vhd.
Found 4-bit comparator greater for signal <$n0002> created at line 20.
Found 4-bit comparator less for signal <$n0003> created at line 23.
Summary:
inferred 2 Comparator(s).
Unit <compare> synthesized.

=========================================================================
HDL Synthesis Report

Macro Statistics
# Comparators

:2

4-bit comparator greater

:1

4-bit comparator less

:1

=========================================================================

=========================================================================
*

Low Level Synthesis

=========================================================================
Library "C:/Xilinx/xc9500/data/lib.xst" Consulted
Library "C:/Xilinx/data/librtl.xst" Consulted

Optimizing unit <compare> ...

=========================================================================
*

Final Report

=========================================================================
Final Results
RTL Top Level Output File Name
Top Level Output File Name
Output Format
Optimization Criterion
Keep Hierarchy

: compare.ngr
: compare

: NGC
: Speed
: YES

Macro Generator

: macro+

Target Technology

: xc9500

Macro Preserve

: YES

XOR Preserve
wysiwyg

: YES
: NO

Design Statistics
# IOs

: 11

Macro Statistics :
# Xors
#

1-bit xor2

:6
:6

Cell Usage :
# BELS

: 43

AND2

: 12

AND3

:2

INV

: 17

OR2

:6

XOR2

:6

# IO Buffers
#

IBUF

OBUF

: 11
:8
:3

=========================================================================
CPU : 5.39 / 8.97 s | Elapsed : 5.00 / 7.00 s

Total memory usage is 43432 kilobytes

VHDL Code

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

--entity declaration with port definitions

entity compare is
port( num1 : in std_logic_vector(3 downto 0); --input 1
num2 :
less :
equal :

in std_logic_vector(3 downto 0); --input 2

out std_logic; -- indicates first number is small
out std_logic; -- both are equal

greater : out std_logic -- indicates first number is bigger

);
end compare;

--architecture of entity
architecture Behavioral of compare is

begin
process(num1,num2)
begin -- process starts with a 'begin' statement
if (num1 > num2 ) then --checking whether num1 is greater than num2
less <= '0';

equal <= '0';

greater <= '1';

elsif (num1 < num2) then --checking whether num1 is less than num2
less <= '1';
equal <= '0';
greater <= '0';
else

--checking whether num1 is equal to num2

less <= '0';

equal <= '1';
greater <= '0';
end if;
end process; -- process ends with a 'end process' statement

end Behavioral;

Conclusion: The vhdl code for 4 bit magnitude comparator was successfully simulated, executed and
run on CPLD XC9536