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Developer's Reference

Chapter 6The POST Component

PhoenixBIOS 4.0 Rel 6.1

The following code fragment hooks the POST task dispatcher and gains control just before each POST task is executed. You can use this to run some test code on every POST task or only on POST tasks that you specify. Add this file to your OEM tip and enter your own test code.
INCLUDE initmacs.inc INCLUDE general.inc postSegment SEGMENT EXTERN postHookDispatcherReturn:NEAR ;+--------------------------------------------------------------------------; hookPostTaskDispatcher - Hook for testing. ; Entry: ; Standard POST Task. ; Exit: ; None. ; Modified: ; All except BX. hookPostTaskDispatcher PROC NEAR PUBLIC cmp cl, TEST_POINT_NUMBER ; Is this the task we want? jne doGeneralTests ; Exit if not ; ; Do tests that are specific to a certain POST task. doSpecificTests: ... jmp allDone ; ; Do test code for all other POST tasks. doGeneralTests: ... jmp allDone allDone: jmp postHookDispatcherReturn hookPostTaskDispatcher ENDP postSegment ENDS END

Listing 9. Hooking the POST Dispatcher

VIII.The POST Tasks


The following are the descriptions of typical POST routines. Some of the POST routines are optional, as noted, and are defined by strong/weak externals. Some routines are warm start only, as noted, and some depend on the POST routine specified in the MAKE.MAK module (STD, STDPCI, or DRAGON). Those interested in writing hook routines should consult the current POST tables in the installed POSTTBL.ASM for an up-to-date sequence of routines. The POST tables for Boot Block are in the BOOTBLOK\POST\STD.600 directory. NOTE: The following routines are sorted by their test point numbers as provided in TPOINTS.ASM in the \POST\COMMON1.xxx directory. Their actual order as executed in the POST tables varies considerably. In the following table the Warm Start only tasks are shaded, the Cold Start only tasks have heavy borders.
Tpoint 02h Hook Routine hookVerifyRealModeJ Post Routine postVerifyRealModeJ (Stackless-No Memory) Description Verify Real Mode. If the CPU is in protected mode, turn on A20 and pulse the reset line, forcing a shutdown 0. NOTE: Hook routine should not alter DX, which holds the powerup CPU ID. Disable Non-Maskable Interrupts.

03h

hookDisableNmiJ

postDisableNmiJ

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Tpoint 04h Hook Routine hookCpuGetTypeJ

Chapter 6The POST Component


Post Routine CpuGetTypeJ (Stackless)

PhoenixBIOS 4.0 Rel 6.1


Description

Get CPU type from CPU registers and other methods. Save CPU type in NVRAM. NOTE: Hook routine should not alter DX, which holds the powerup CPU ID. Initialize system hardware. Reset the DMA controllers, disable the videos, clear any pending interrupts from the real-time clock and set up port B register. Disable system ROM shadow and start to execute ROMEXEC code from the flash part. This task is pulled into the build only when the ROMEXEC relocation is installed. Initialize chip set registers to the Initial POST Values. Set in-POST flag in CMOS that indicates we are in POST. If this bit is not cleared by postClearBootFlagJ (AEh), the BIOS on next boot determines that the current configuration caused POST to fail and uses default values for configuration. Clear the CMOS diagnostic byte (register E). Check the real-time clock and verify the battery has not lost power. Checksum the CMOS and verify it has not been corrupted (Rel. 6.0). Initialize CPU registers Enable CPU cache. Set bits in cmos related to cache. Set the initial POST values of the cache registers if not integrated into the chipset. Set the initial POST values for registers in the integrated I/O chip. Enable the local bus IDE as primary or secondary depending on other drives detected. Initialize Power Management. General dispatcher for alternate register initialization. Set initial POST values for other hardware devices defined in the register tables. Restore the contents of the CPU control word whenever the CPU is reset. Early reset of PCI devices required to disable bus master. Assumes the presence of a stack and running from decompressed shadow memory. Verify that the 8742 keyboard controller is responding. Send a self-test command to the 8742 and wait for results. Also read the switch inputs from the 8742 and write the keyboard controller command byte. Verify that the ROM BIOS checksums to zero Initialize external cache before autosizing memory. Initialize all three of the 8254 timers. Set the clock timer (0) to binary count, mode 3 (square wave mode), and read/write LSB then MSB. Initialize the clock timer to zero. Set the RAM refresh timer (1) to binary count, mode 2 (Rate Generator), and read/write LSB only. Set the counter to 12H to generate the refresh at the proper rate. Set sound timer (2) to binary count, mode 3, and read/write LSB, then MSB. Initialize DMA command register with these settings: 1. Memory to memory disabled 2. Channel 0 hold address disabled 3. Controller enabled 4. Normal timing 5. Fixed priority 6. Late write selection 7. DREQ sense active

06h

hookHardwareInitJ

postHardwareInitializeJ (Stackless)

07h

hookCsBiosDeshadowJ

csBiosDeshadowJ (Stackless, Optional)

08h 09h

hookChipsetInitJ hookSetInPostFlagJ

csInitializeJ (Stackless) postSetInPostFlagJ

0Ah 0Bh 0Ch 0Eh 0Fh 10h 11h

hookCpuInitialize1J (Warm) hookCpuInitialize2J (Cold) hookCpuCacheOnJ hookCacheInitializeJ hookIoInitializeJ hookfDiskInitializeJ hookPmInitializeJ hookRegInitJ

cpuInitializeJ (Stackless) cpuCacheOnJ cacheInitializeJ (Stackless) ioInitializeJ (Stackless, optional) fdiskInitializeJ pmInitializeJ (Optional) postRegInitializeJ (Stackless, optonal) cpuRestoreCR0J (Stackless-No memory) pciBusMasterResetJ (Warm start, optional) postI8742InitJ (Stackless)

12h 13h

hookRestoreCR0J hookPciBusMasterResetJ

14h

hookI8742InitJ

16h 17h 18h

hookChecksumTestJ hookCachePreRamAutoSizeJ hookTimerInitJ

postChecksumTestJ (Stackless) cachePreRamAutoSizeJ (Stackless, Optional) postTimerInitJ (Stackless)

1Ah

hookDmaInitJ

postDmaInitJ

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Tpoint Hook Routine

Chapter 6The POST Component


Post Routine

PhoenixBIOS 4.0 Rel 6.1

1Ch 20h 22h 24h 28h

hookResetICsJ hookRefreshTestJ hookWarmKBStartJJ hookSetHugeESJ (Stackless) hookSetHugeES2J hookRamAutosizeJ

postResetICsJ (Stackless) postRefreshTestJ (Stackless) postWarmKBStartJ (Stackless) postSetHugeESJ csRamAutosizeJ (Stackless)

Description 8. DACK sense active low. Initialize all 8 DMA channels with these settings: 1. Single mode 2. Address increment 3. Auto initialization disabled (channel 4 Cascade) 4,. Verify transfer Initialize interrupt controllers for some shutdowns. Verify that DRAM refresh is operating by polling the refresh bit in PORTB. Reset the keyboard. Set segment-register addressibility to 4 GB Using the table of configurations supplied by the specific chipset module, test each DRAM configuration to see if that particular configuration is valid. Then program the chipset to its autosized configuration. Before autosizing, disable all caches and all shadow RAM. Initialize the POST Memory Manager Zero the first 512K of RAM Test 512K base address lines Test first 512K of RAM. Initialize external cache before shadowing. Compute CPU speed. Initialize the Phoenix Dispatch Manager Vector to proper shutdown routine. Shadow the system BIOS. Autosize external cache and program cache size for enabling later in POST. If CMOS is valid, load chipset registers with values from CMOS, otherwise load defaults and display Setup prompt. If Auto Configuration is enabled, always load the chipset registers with the Setup defaults (Rel 6.0). Load alternate registers with CMOS values. Registertable pointers are in the altregtable segment. Initialize extended memory for RomPilot. Initialize interrupt vectors 0 thru 77h to the BIOS general interrupt handler. Initialize all motherboard devices. Verify the ROM copyright notice Initialize support for I2O by initializing global variables used by the I2O code. Pause POST table processing if a CMOS bit is set (for debugging). Verify that the equipment specified in the CMOS matches the hardware currently installed. If the monitor type is set to 00 then a video ROM must exist. If the monitor type is 1 or 2 set the video switch to CGA. If monitor type 3, set the video switch to mono. Also specify in the equipment byte that disk drives are installed. Set appropriate status bits in CMOS or the BDA if configuration errors are found. Perform these tasks: 1. Size the PCI bus topology and set bridge bus numbers. 2. Set the system max bus number. 3. Write a 0 to the command register of every PCI device. 4. Write a 0 to all 6 base registers in every PCI device. 5. Write a -1 to the status register of every PCI device.

29h 2Ah 2Ch 2Eh 2Fh 32h 33h 36h 38h` 3Ah 3Ch

hookPostMemory MgrInitJ hookZeroBaseRamJ hookRealAddressTestJ hookBaseRamTestJ hookCachePreSysShadowJ hookComputeSpeedJ hookPdmInitJ hookCheckShutdownCodeJ hookSysShadowConfigJ hookCacheAutosizeJ hookAdvCsConfigJ

postMemoryMgrInitJ postZeroBaseRamJ (Stackless) postRealAddressTestJ (Stackless) postBaseRamTestJ (Stackless) cachePreSysShadowJ (Stackless) cpuComputeSpeedJ postPdmInitJ postCheckShutdownCodej (Stackless-No Memory) csSysShadowConfigJ CacheAutosizeJ csAdvConfigJ (Optional)

3Dh 41h 42h 45h 46h 47h

hookAdvRegConfigJ hookRomPilotInitJ hookVectorInitJ hookCoreDeviceInitJ hookCopyrightCheckJ hookI2oInitJ

postAdvRegConfigJ (Optional) featRomPilotInitJ postVectorInitJ (Stackless) coreDeviceInitJ postCopyrightCheckJ i2oInitJ (Optional)

48h

hookConfigCheckJ

postConfigCheckJ

49h

hookPciInitJ

pciInitJ

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Tpoint 4Ah 4Bh Hook Routine hookVideoInitJ hookQuietBootStartJ

Chapter 6The POST Component


Post Routine pciVideoInitJ quietBootStartJ (Optional)

PhoenixBIOS 4.0 Rel 6.1

4Ch 4Eh 4Fh 50h 51h 52h 52h 54h 55h 58h

hookVidShadowConfigJ hookCopyrightDisplayJ hookMultiBootInitJ hookCpuDisplayJ hookEisaInitJ hookWarmKBTestJ hookKBTestJ hookSetupKeyclickJ hookUsbConfigUsbFarJ hookHotInterruptTestJ

csVidShadowConfigJ postCopyrightDisplayJ multiBootInitFarJ (Optional) CpuDisplayJ eisaInitJ postWarmKBTestJ postKBTestJ featSetupKeyclickJ (Optional) usbConfigUsbFarJ (Optional) postHotInterruptTestJ

Description 6. Find all IOPs and initialize them. Initialize all video adapters in system Initialize QuietBoot if it is installed. Enable both keyboard and timer interrupts (IRQ0 and IRQ1). If your POST tasks require interrupts off, preserve them with a PUSHF and CLI at the beginning and a POPF at the end. If you change the PIC, preserve the existing bits. Shadow video BIOS ROM if specified by Setup, and CMOS is valid and the previous boot was OK. Display copyright notice. Initialize MultiBoot. Allocate memory for old and new MultiBoot history tables. Display CPU type and speed Checksum CMOS and initialize each EISA slot with data from the initialization data block. Verify keyboard reset. Verify keyboard reset. Initialize keystroke clicker if enabled in Setup. Enable USB devices. Test for unexpected interrupts. First do an STI for hot interrupts. Secondly, test the NMI for an unexpected interrupt. Thirdly, enable the parity checkers and read from memory, checking for an unexpected interrupt. Register POST Display Services, fonts, and languages with the POST Dispatch Manager. Display prompt "Press F2 to enter SETUP" Disable CPU cache. Test RAM between 512K and 640K. Determine and test the amount of extended memory available. Determine if memory exists by writing to a few strategic locations and see if the data can be read back. If so, perform an address-line test and a RAM test on the memory. Save the total extended memory size in the CMOS at cmosExtended. Perform an address line test on A0 to the amount of memory available. This test is dependent on the processor, since the test will vary depending on the width of memory (16 or 32 bits). This test will also use A20 as the skew address to prevent corruption of the system memory. Jump to UserPatch1. See "The POST Component.". Set cache registers to their CMOS values if CMOS is valid, unless auto configuration is enabled, in which case load cache registers from the Setup default table. Quick initialization of all Application Processors in a multi-processor system. Enable external cache and CPU cache if present. Configure non-cacheable regions if necessary. NOTE: Hook routine must preserve DX, which carries the cache size to the DisplayCacheSizeJ routine. Initialize the handler for SMM.
Display external cache size on the screen if it is non-zero. NOTE: Hook routine must preserve DX, which carries the cache size from the cacheConfigureJ routine.

59h 5Ah 5Bh 5Ch 60h

hookPdsInitializeJ hookDisplayF2MessageJ hookCpuCacheOffJ hookMemoryTestJ hookExtendedMemoryTestJ

pdsInitializeJ (Optional) postDisplayF2MessageJ cpuCacheOffJ (Stackless) postMemoryTestJ postExtendedMemoryTestJ

62h

hookExtendedAddressTestJ

postExtendedAddressTestJ

64h 66h

hookUserPatch1J hookAdvCacheConfigJ

postUserPatch1J cacheAdvConfigJ (Optional)

67h 68h

hookMpInitMinJ hookCacheConfigureJ

mpInitMinJ (Optional) cacheConfigureJ

69h
6Ah

hookPmSMMInitJJ
hookDisplayCacheSizeJ

pmSMMInitJ (Optional)
postDisplayCacheSizeJ

6Bh
6Ch 6Eh

hookLoadCustomDefaultsJ
hookDisplayShadowsJ hookDisplayNonDispJ

featLoadCustomDefaultsJ (Optional)
postDisplayShadowsJ postDisplayNonDisposableJ

If CMOS is bad, load Custom Defaults from flash into CMOS. If successful, reboot.
Display shadow message Display the starting offset of the non-disposable segment of the BIOS

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Tpoint
70h

Chapter 6The POST Component


Post Routine
postDisplayErrorMessagesJ

PhoenixBIOS 4.0 Rel 6.1


Description

Hook Routine
hookDisplayErrorMsgsJ

72h 76h 7Ch

hookTestConfigJ hookKeyboardTestJ hookSetupHWVectorsJ

postTestConfigJ postKeyboardTestJ postSetupHardwareVectorsJ

Check flags in CMOS and in the BIOS data area for errors detected during POST. Display error messages on the screen. Check status bits to see if configuration problems were detected. If so, display error messages on the screen. Check status bits for keyboard-related failures. Display error messages on the screen. Initialize the hardware interrupt vectors from 08 to 0F and from 70h to 77H. Also set the interrupt vectors from 60h to 66H to zero.

7Dh
7Eh

hookISMInitJ
hookCoprocessorTestJ

postISMInitJ (Optional)
cpuCoprocessorTestJ

Initialize Intelligent System Monitoring.


The Coprocessor initialization test. Use the floating point instructions to determine if a coprocessor exists instead of the ET bit in CR0. Disable onboard COM and LPT ports before testing for presence of external I/O devices.. Run late device initialization routines. Test and identify RS232 ports. Configure Fisk Disk Controller.

80h 81h 82h 83h

hookIoBeforeInitJ hookCoreLateDeviceInitJ hookRS232TestCodeJ hookFdiskCfgIdeCtrlrJ

ioBeforeInitJ (Optional) corelateDeviceInitJ (Optional) ioRS232TestCodeJ fdiskCfgIdeCtrlrJ

84h
85h 86h 87h

hookParallelTestCodeJ
hook PciInitPccJ hookIoAfterInitJ hookMcdConfigureDevicesJ

ioParallelTestCodeJ
pciInitPccJ (Optional) ioAfterInitJ (Optional) mcdPostConfigure DevicesJ

Test and identify parallel ports.


Display any ESCD read errors and configure all PnP ISA devices. Initialize onboard I/O and BDA according to CMOS and presence of external devices. Initialize motherboard configurable devices.

88h
89h 8Ah 8Bh 8Ch

hookBiosInitJ
hookEnableNmiJ hookInitExtBDAJ hookMouseTestJ hookFloppyTestJ

postBiosInitJ
postEnableNmiJ postInitExtBDAJ featMouseTestJ (Optional) postFloppyTestJ

Initialize interrupt controller.


Enable non-maskable interrupts. Initialize Extended BIOS Data Area and initialize the mouse. Setup interrupt vector and present bit in Equipment byte. Initialize both of the floppy disks and display an error message if failure was detected. Check both drives to establish the appropriate diskette types in the BIOS data area. Count the number of ATA drives in the system and update the number in bdaFdiskcount. Initialize hard-disk controller. If the CMOS ram is valid and intact, and fixed disks are defined, call the fixed disk init routine to intialize the fixed disk system and take over the appropriate interrupt vectors. Configure the local bus IDE timing register based on the drives attached to it. Jump to UserPatch2. See "The POST Component". Build the MPTABLE for multi-processor boards 1. Check CMOS for CD-ROM drive present 2. Activate the drive by checking for media present 3. Check sector 11h (17) for Boot Record Volume Descriptor 4. Check the boot catalog for validity 5. Pick a boot entry 6. Create a Specification Packet Reset segment-register addressibility from 4GB to normal 64K by generating a Shutdown 8. Create pointer to MP table in Extended BDA.

8Fh 90h

hookFdiskPreFastInitJ, hookFDiskTestJ

fdiskPreFastInitJ (Optional) fdiskPostTestJ

91h 92h 93h 95h

hookFdiskFastInitJ hookUserPatch2J hookMpInitJ hookCDTestJ

fdiskFastInitJ (Optional) userPatch2J mpInitJ (Optional) hddCDTestJ (Optional)

96h 97h

hookClearHugeESJ hookMpFixUpTableJ

postDoShutdown8 postMpFixUpTableJ (Optional)

98h

hookRomAreaCheckJ

postRomAreaCheckJ

99h 9Ah

hookCheckSmartJ hookMiscShadowConfigJ

postCheckSmartJ (Optional) csMiscShadowConfigJ

Search for option ROMs. Rom scan the area from C800h for a length of BCP_ROM_Scan_Size (or to E000h by default) on every 2K boundry, looking for add on cards that need initialization. Check support status for Self-Monitoring Analysis Reporting Technology (disk-failure warning). Shadow miscellaneous ROMs if specified by Setup

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Tpoint 9Ch
9Dh

Chapter 6The POST Component


Post Routine pmSetupJ
securityEngineInitJ (Optional)

PhoenixBIOS 4.0 Rel 6.1

Hook Routine hookPmSetupJ (Optional)


hookSecurityEngineInitJ

Description and CMOS is valid and the previous boot was OK. Set up Power Management. Initiate power management state machine.
Initialize Security Engine.

9Eh 9Fh A0h A2h A4h A8h AAh

hookEnableIRQsJ hookFdiskRestFastInitJ hookSetTimeOfDayJ hookKeyLockTestJ hookInitKeyRateJ hookEraseF2MsgJ hookScanForF2J

postEnableIRQsJ fdiskRestFastInitJ (Optional) postSetTimeOfDayJ postKeyLockTestJ featInitKeyboardRateJ (Optional) postEraseF2MsgJ postScanForF2J

Enable hardware interrupts Check the total number of Fast Disks (ATA and SCSI) and update the bdaFdiskCount. Verify that the system clock is interrupting. Setup Numlock indicator. Display a message if key switch is locked. Initialize typematic rate Overwrite the "Press F2 for Setup" prompt with spaces, erasing it from the screen. Scan the key buffer to see if the F2 key was struck after keyboard interrupts were enabled. If an F2 keystroke is found, set a flag. Enter SETUP. If (F2 was pressed) go to SETUP Else if (errors were found) display "Press F1 or F2" prompt if (F2 is pressed) go to setup else if (F1 is pressed) boot Else boot Clear ConfigFailedBit and InPostBit in CMOS. Check for errors. If (errors were found) beep twice display "F1 or F2" message if (F2 keystroke) go to SETUP if (F1 keystroke) go to BOOT Inform RomPilot about the end of POST. Change status bits in CMOS and/or the BIOS data area to reflect the fact that POST is complete. One quick beep Turn off <Esc> and <F2> key checking. IF (VGA adapter is present) IF (OEM screen is still up) Note OEM screen is gone. Fade out OEM screen. Reset video: clear screen, reset cursor, reload DAC. ENDIF ENDIF If password on boot is enabled, a call is made to Setup to check password. If the user does not enter a valid password, Setup does not return. Initialize ACPI BIOS. Clear all screen graphics before booting. Initialize the SMBIOS header and sub-structures. Clear parity-error latch Display Boot First menu if MultiBoot is installed. If BCP option is enabled, clear the screen before booting. Check virus and backup reminders. Display System Summary. Try to boot with INT 19 Initialize the Post Error Manager. Write PEM errors.

ACh

hookSetupCheckJ

postSetupCheckJ

AEh B0h

hookClearBootFlagJ hookErrorCheckJ

postClearBootFlagJ postErrorCheckJ

B1h B2h B4h B5h

hookRomPilotUnloadJ hookPostDoneJ hookOneBeepJ hookQuietBootEndJ

featRomPilotUnloadJ postDoneJ postOneBeepJ quietBootEndJ (Optional)

B6h

hookCheckPasswordJ

featCheckPasswordJ (Optional)

B7h B9h BAh BCh BDh BEh BFh C0h C1h C2h

hookACPIConfigJJ hookPrepareToBoot hookDMIConfigJ hookClearParityJ hookBootMenuJ hookClearScreenJ hookCheckRemindersJ hookInt19 hookPemInit hookPemLog

postACPIConfigJ (Optional) postPrepareToBootj postDMIConfigJ (Optional) postClearParityJ featBootMenuJ (Optional) postClearScreenJ postCheckRemindersJ postInt19 pemInitFarJ pemLogErrorsFarJ

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