DESCRIPTION
The PD784927 and 784928 are members of the NEC 78K/IV Series of microcontrollers equipped with a highspeed, high-performance 16-bit CPU for VCR software servo control. The PD784927Y and 784928Y are based on the PD784928 with the addition of an I2C bus interface compatible with multi-master. They contain many peripheral hardware units ideal for VCR control, such as a multi-function timer unit (super timer unit) for software servo control and VCR analog circuits. Flash memory models, the PD78F4928 and PD78F4928Y, are under development. The functions of the PD784927 is described in detail in the following Users Manual. Be sure to read this manual before designing your system.
: U12648E : U10905E
FEATURES
High instruction execution speed realized by 16-bit CPU core Minimum instruction execution time: 250 ns (with 8 MHz internal clock) High internal memory capacity
Item Part Number
PD784927, 784927Y
96K bytes 2048 bytes
PD784928, 784928Y
128K bytes 3584 bytes
VCR analog circuits conforming to VHS Standard CTL amplifier RECCTL driver (rewritable) CFG amplifier DFG amplifier DPG amplifier Reel FG comparator (2 channels) CSYNC comparator
Timer unit (super timer unit) for servo control Serial interface : 3 channels 3-wire serial I/O : 2 channels I2C bus interface: 1 channel A/D converter: 12 channels (conversion time: 10 s) Low-frequency oscillation mode: main system clock frequency = internal clock frequency Low-power consumption mode: CPU can operate with a subsystem clock. Supply voltage range: VDD = +2.7 to 5.5 V Hardware watch function: watch operation at low voltage (VDD = 2.7 V (MIN.)) and low current consumption
Unless otherwise specified, the PD784927 is treated as the representative model throughout this document.
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. U12255EJ2V0DSJ1 (2nd edition) Date Published September 2000 N CP(K) Printed in Japan
The mark
1997,1999
ORDERING INFORMATION
(1) PD784928 subseries Part Number Package 100-pin plastic LQFP (fine pitch) (14 14 mm) 100-pin plastic QFP (14 20 mm) 100-pin plastic LQFP (fine pitch) (14 14 mm) 100-pin plastic QFP (14 20 mm)
Package 100-pin plastic LQFP (fine pitch) (14 14 mm) 100-pin plastic QFP (14 20 mm) 100-pin plastic LQFP (fine pitch) (14 14 mm) 100-pin plastic QFP (14 20 mm)
78K/IV series
PD784928
PD784928Y
100-pin QFP. With flash memory. Expanded internal memory capacity. More powerful analog amplifier. Improved VCR functions. Increased I/O. High-current port added. I2C function added (Y model only). 100-pin QFP. Expanded internal memory capacity. Internal analog amplifier. Reinforced super timer. Low-power consumption mode added. 100-pin QFP Expanded internal RAM capacity. Operational amplifier, watch function, multiplier added.
PD784915
78K/I series
PD78148
PD78138
80-pin QFP
PD784927, 784927Y
PD784928, 784928Y
16 MHz (internal clock: 8 MHz) Low frequency oscillation mode : 8 MHz (internal clock: 8 MHz) Low power consumption mode : 32.768 kHz (subsystem clock) 250 ns (with 8 MHz internal clock)
74
11 (including one each for pseudo VSYNC, head amplifier switch, and chrominance rotation) Timer/counter TM0 (16 bits) TM1 (16 bits) FRC (22 bits) TM3 (16 bits) UDC (5 bits) EC (8 bits) EDV (8 bits) Input signal CFG DFG HSW VSYNC CTL TREEL SREEL Compare register 3 3 2 1 4 1 Number of bits 22 22 16 22 16 22 22 Capture register 1 6 1 Measurable cycle 125 ns to 524 ms 125 ns to 524 ms 1 s to 65.5 ms 125 ns to 524 ms 1 s to 65.5 ms 125 ns to 524 ms 125 ns to 524 ms Remark
For HSW signal generation For CFG signal division Operating edge
Capture register
VSYNC separation circuit, HSYNC separation circuit VISS detection, wide aspect detection circuits Field identification circuit Head amplifier switch/chrominance rotation output circuit Timer TM2 (16 bits) TM4 (16 bits) TM5 (16 bits) Compare register 1 1 (capture/compare) 1 Capture register 1
General-purpose timer
PWM output
16-bit resolution : 3 channels (carrier frequency: 62.5 kHz) 8-bit resolution : 3 channels (carrier frequency: 62.5 kHz)
Serial interface
3-wire serial I/O: 2 channels (BUSY/STRB control: 1 channel) I2C bus interface: 1 channel (PD784928Y subseries only) 8-bit resolution 12 channels, conversion time: 10 s
A/D converter
PD784927, 784927Y
PD784928, 784928Y
4 levels (programmable), vectored interrupt, macro service, context switching 9 (including NMI) 22 (including software interrupt) 23 (including software interrupt)
HALT mode/STOP mode/low power consumption mode/low power consumption HALT mode STOP mode can be released by input of valid edge of NMI pin, watch interrupt (INTW), or INTP1/ INTP2/KEY0-KEY4 pins
0.5-second measurement, low-voltage operation (VDD = 2.7 V) 1.95 kHz, 3.91 kHz, 7.81 kHz, 15.6 kHz (Internal clock: 8 MHz) 2.048 kHz, 4.096 kHz, 32.768 kHz (Subsystem clock: 32.768 kHz)
VDD = +2.7 to 5.5 V 100-pin plastic LQFP (fine pitch)(14 14 mm)Note 100-pin plastic QFP (14 20 mm)
Note
Under development
P84/PWM2/SDANote 2 P83/ROTC P82/HASW P80 P57 P56 P55 P54 P53 P52 P51 P50 VSS VDD P47 P46 P45 P44 P43 P42 P41 P40 P07 P06 P05
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 1 75 2 74 3 73 4 72 5 71 6 70 7 69 8 68 9 67 10 66 11 65 12 64 13 63 14 62 15 61 16 60 17 59 18 58 19 57 20 56 21 55 22 54 23 53 24 52 25 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
P65/HWIN/DPGMON P64/BUZ/DFGMON P103/CSYNCIN P102/REEL0IN/INTP3 P101/REEL1IN DFGIN P100/DPGIN CFGCPIN CFGAMP0 CFGIN AVDD1 AVSS1 VREFC CTLOUT2 CTLOUT1 CTLIN RECCTL RECCTL+ CTLDLY AVSS2 P113/ANI11 P112/ANI10 P111/ANI9 P110/ANI8 P77/ANI7
Notes 1. Under development 2. Pins SCL and SDA are provided for the PD784928Y subseries only. Caution Directly connect the IC (Internally Connected) pins to VSS in the normal operation mode.
P04 P03 P02 P01 P00 P23/INTP2 P22/INTP1 P21/INTP0 P20/NMI P90/ENV P91/KEY0 P92/KEY1 P93/KEY2 P94/KEY3 P95/KEY4 P96 AVDD2 AVREF P70/ANI0 P71/ANI1 P72/ANI2 P73/ANI3 P74/ANI4 P75/ANI5 P76/ANI6
DFGMON/P64/BUZ DPGMON/P65/HWIN CFGMON/P66/PWM4 CTLMON/P67/PWM5 P60/STRB/CLO P61/SCK1/BUZ P62/SO1 P63/SI1 P37/PWM0 P36/PWM1 P35/SCK2 P34/SO2 P33/SI2/BUSY VDD XT1 XT2 VSS X2 X1 RESET IC P32/PTO02 P31/PTO01 P30/PTO00 P87/PTO11 P86/PTO10 Note SCL /P85/PWM3 Note SDA /P84/PWM2 P83/ROTC P82/HASW
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
P80 P57 P56 P55 P54 P53 P52 P51 P50 VSS VDD P47 P46 P45 P44 P43 P42 P41 P40 P07
CSYNCIN/P103 REEL0IN/INTP3/P102 REEL1IN/P101 DFGIN DPGIN/P100 CFGCPIN CFGAMPO CFGIN AVDD1 AVSS1 VREFC CTLOUT2 CTLOUT1 CTLIN RECCTLRECCTL+ CTLDLY AVSS2 ANI11/P113 ANI10/P112
ANI9/P111 ANI8/P110 P77/ANI7 P76/ANI6 P75/ANI5 P74/ANI4 P73/ANI3 P72/ANI2 P71/ANI1 P70/ANI0 AVREF AVDD2 P96 P95/KEY4 P94/KEY3 P93/KEY2 P92/KEY1 P91/KEY0 P90/ENV NMI/P20 INTP0/P21 INTP1/P22 INTP2/23 P00 P01 P02 P03 P04 P05 P06
Note
Pins SCL and SDA are provided for the PD784928Y subseries only.
Pins SCL and SDA are provided for the PD784928Y subseries only.
NMI INTP0-INTP3
PWM0-PWM5 PTO00-PTO02 PTO10, PTO11 SUPER TIMER UNIT CLOCK OUTPUT BUZZER OUTPUT VREFC REEL0IN REEL1IN CSYNCIN DFGIN DPGIN CFGIN CFGAMPO CFGCPIN CTLOUT1 CTLOUT2 CTLIN RECCTL+ RECCTLCTLDLY DFGMON DPGMON CFGMON CTLMON AVDD1, AVDD2 AVSS1, AVSS2 AVREF AN10-AN11
KEY INPUT
KEY0-KEY4
P00-P07 78K/IV 16-BIT CPU CORE (RAM: 512 bytes) REAL-TIME OUTPUT PORT P80, P82, P83 PORT0 PORT2 ANALOG UNIT & A/D CONVERTER RAM ROM PORT3 PORT4 PORT5 P00-P07 P20-P23 P30-P37 P40-P47 P50-P57 P60-P67 P70-P77 P80, P82-P87 P90-P96 P100-P103 P110-P113
SERIAL INTERFACE 1
PORT6 PORT7
SERIAL INTERFACE 2
PORT8 PORT9
SDA SCL
PORT10 PORT11
Note
Remark Internal ROM and RAM capacities differ depending on the product.
PD784927
DFG DPG Drum motor M Driver DFGIN DPGIN PORT PWM0 PORT SCK1 SI1 SO1 INTP0 INTP0 SCK Cameracontrolling SO microcontroller SI PD784038 PORT PORT Key matrix
CFG
CFGIN
Capstan motor
Driver
PWM1 Camera block RECCTL+ PORT SCK2 SO2 BUSY CS CLK DATA BUSY
LCD C/D
PD7225
Loading motor
Driver
Composite sync signal CSYNCIN Video head switch PTO00 Audio head switch PTO01 Pseudo vertical sync signal P80 Remote controller reception signal
PORT
STRB
OSD
PD6461
INTP2
Mechanical block
PC2800A
Note
EEPROMTM SDA SDA SCL Other ICs SDA X1 X2 XT1 XT2 SCL
SCL
Note
16 MHz
32.768 kHz
Note
Pins SCL and SDA are provided for the PD784928Y subseries only.
PWM0
CFG
Capstan motor
Driver
CTL head RECCTLPORT Composite sync signal Audio/video signal CSYNCIN Video head switch processing circuit PTO00 Audio head switch PTO01 Pseudo vertical sync signal P80 PWM5 PORT M Reel motor M Driver Reel FG1 PWM4 INTP2 REEL1IN +VDD +VDD EEPROM SDA
Note
Loading motor
Driver
PWM2
Reel FG0
REEL0IN Tuner
Driver
PWM3 PORT Remote controller reception signal Mechanical block Remote controller signal
PC2800A
SCL
Note
8 MHz
32.768 kHz
Note
Pins SCL and SDA are provided for the PD784928Y subseries only.
10
1. DIFFERENCE BETWEEN PD784928 SUBSERIES AND 784928Y SUBSERIES .................... 12 2. PIN FUNCTION ............................................................................................................................... 13
2.1 2.2 2.3 Port Pins ................................................................................................................................................ Pins Other Than Port Pins .................................................................................................................. I/O Circuits of Pins and Processing of Unused Pins ...................................................................... 13 14 16
Memory Space ...................................................................................................................................... Special Function Registers (SFRs) ................................................................................................... Ports ....................................................................................................................................................... Real-Time Output Port ......................................................................................................................... Super Timer Unit .................................................................................................................................. Serial Interface ..................................................................................................................................... A/D Converter ....................................................................................................................................... VCR Analog Circuits ............................................................................................................................
3.10 Watch Function .................................................................................................................................... 3.11 Clock Output Function ........................................................................................................................ 3.12 Buzzer Output Function ......................................................................................................................
Standby Function ................................................................................................................................. Clock Generation Circuit ..................................................................................................................... Reset Function .....................................................................................................................................
5. INSTRUCTION SET ........................................................................................................................ 66 6. ELECTRICAL SPECIFICATIONS .................................................................................................. 70 7. PACKAGE DRAWING .................................................................................................................... 85 8. RECOMMENDED SOLDERING CONDITIONS ............................................................................. 87 APPENDIX A. DEVELOPMENT TOOLS ............................................................................................ 88 APPENDIX B. RELATED DOCUMENTS ............................................................................................ 91
11
PD784927, PD784927Y
Mask ROM 96K bytes
PD784928, PD784928Y
PD78F4928, PD78F4928Y
Flash memory
Internal RAM Internal memory capacity select register (IMS) IC pin VPP pin Electrical characteristics
12
Input
P50-P57
I/O
P60 P61 P62 P63 P64 P65 P66 P67 P70-P77 P80 P82 P83 P84 P85 P86 P87 P90 P91-P95 P96 P100 P101 P102 P103 P110-P113
I/O
Input I/O
8-bit input port (port 7) Pseudo VSYNC output HASW output ROTC output 7-bit I/O port (port 8). Can be set in input or output mode in 1-bit units. Can be connected with software pull-up resistors.
PWM2/SDANote PWM3/SCLNote PTO10 PTO11 I/O ENV KEY0-KEY4 Input DPGIN REEL1IN REEL0IN/INTP3 CSYNCIN Input ANI8-ANI11 4-bit input port (port 11). 7-bit I/O port (port 9).
Can be set in input or output mode in 1-bit units. Can be connected with software pull-up resistors. 4-bit input port (port 10).
Note
Pins SCL and SDA are provided for the PD784928Y subseries only.
Data Sheet U12255EJ2V0DS00
13
Note
Pins SCL and SDA are provided for the PD784928Y subseries only.
Data Sheet U12255EJ2V0DS00
14
15
Note
Pins SCL and SDA are provided for the PD784928Y subseries only.
16
: bit 1 of amplifier control register (AMPC) : bit 7 of amplifier mode register 0 (AMPM0) : bit 2 of amplifier control register (AMPC) : bit 3 of amplifier control register (AMPC) : bit 5 of amplifier control register (AMPC) : bit 6 of amplifier control register (AMPC) : bit 4 of amplifier control register (AMPC)
17
Type 2
Type 8-A
VDD
IN
P-ch
Type 2-A
VDD Pull-up enable Output disable N-ch
IN/ OUT
P-ch IN
Type 9
IN
P-ch N-ch
+ -
Comparator
Type 5-A
VDD Pull-up enable VDD Data P-ch IN/ OUT Output disable Input enable N-ch Pull-up Enable VDD Data P-ch IN/OUT Open drain Output disable N-ch VREF (Threshold voltage) Input enable P-ch
Type 10-A
VDD
P-ch
18
A (R1) B (R3) R5 RP2 R7 RP3 V VVP (RG4) U UUP (RG5) R11 R9 VP (RP4)
BC (RP1)
R10 UP (RP5)
D (R13) E (R12) DE (RP6) TDE (RG6) W H (R15) L (R14) HL (RP7) WHL (RG7) ( ): absolute name
8 banks
Caution Although R4, R5, R6, R7, RP2, and RP3 can be used as X, A, C, B, AX, and BC registers, respectively, by setting the RSS bit of PSW to 1, do not use this function. The function of the RSS bit is planned to be deleted from the future models in the 78K/IV Series.
19
19 PC
(2) Program status word This is a register that holds the various statuses of the CPU. Its contents are automatically updated as the program is executed.
10
4 AC
3 IE
2 P/V
1 0
0 CY
Note
The RSS flag is provided to maintain compatibility with the microcomputers in the 78K/III Series. Always clear this flag to 0 except when the software of the 78K/III Series is used.
(3) Stack pointer This is a 24-bit pointer that holds the first address of the stack. Be sure to write 0 to the high-order 4 bits.
SP
23 0 0
20 0
20
0F100H-0FFFFH
Remark The area of the internal ROM overlapping the internal data area cannot be used when the LOCATION 0 instruction is executed.
Part Number Unusable Area 0F700H-0FFFFH (2304 bytes) 0F100H-0FFFFH (3840 bytes)
21
22
Cannot be used
18000H 17FFFH
0FEFFH
FFEFFH
Internal ROM
0FE3BH
(32768 bytes) 10000H 0FFFFH Special function registers (SFRs) 0FFDFH 0FFD0H Note 1 (256 bytes) 0FF00H 0FEFFH
Data Sheet U12255EJ2V0DS00
Macro service control 0FE06H word area (54 bytes) Data area (512 bytes)
FFE3BH FFE06H
0FD00H 0FCFFH
FFD00H FFCFFH
FF700H 17FFFH
Cannot be used
0F6FFH
Note 4
Program/data areaNote 3
01000H 00FFFH
18000H 17FFFH
CALLT table area (64 bytes) Vector table area (64 bytes)
Note 4
00000H
00000H
00000H
Notes 1. Accessed in external memory expansion mode 2. The 2304 bytes in this area can be used as an internal ROM only when the LOCATION 0FH instruction is executed. 3. When LOCATION 0H instruction is executed: 96000 bytes, when LOCATION 0FH instruction is executed: 98304 bytes 4. Base area or entry area for reset or interrupt. Excluding the internal RAM for reset.
0FEFFH
FFEFFH
Cannot be used
20000H 1FFFFH
Internal ROM
0FE3BH
(65536 bytes) 10000H 0FFFFH Special function registers (SFRs) 0FFDFH 0FFD0H Note 1 (256 bytes) 0FF00H 0FEFFH
Data Sheet U12255EJ2V0DS00
Macro service control 0FE06H word area (54 bytes) Data area (512 bytes)
FFE3BH FFE06H
0FD00H 0FCFFH
FFD00H FFCFFH
FF100H 1FFFFH
Cannot be used
0F0FFH
Note 4
Program/data areaNote 3
01000H 00FFFH
20000H 1FFFFH
CALLT table area (64 bytes) Vector table area (64 bytes)
Note 4
00000H
00000H
00000H
Notes 1. Accessed in external memory expansion mode 2. The 3840 bytes in this area can be used as an internal ROM only when the LOCATION 0FH instruction is executed. 3. When LOCATION 0H instruction is executed: 127232 bytes, when LOCATION 0FH instruction is executed: 131072 bytes
23
4. Base area or entry area for reset or interrupt. Excluding the internal RAM for reset.
Bit length ................................. Indicates the bit length (word length) of the SFR. Bit units for manipulation ....... Indicates bit units in which the SFR in question can be manipulated. An SFR that can be manipulated in 16-bit units can be used as the operand sfrp of an instruction. Specify an even address to manipulate this SFR. An SFR that can be manipulated in 1-bit units can be used for a bit manipulation instruction. After clearing reset ................. Indicates the status of each register immediately after clearing reset. Caution The addresses shown in Table 3-1 are used when the LOCATION 0H instruction is executed. Add F0000H to the address values shown in the table when the LOCATION 0FH instruction is executed.
24
Remark Cleared to 0: Counter is initialized to 0 within 16 clocks after the reset signal has been cleared (the contents before initialization are undefined).
25
Notes 1. When the TOM1 is read, the write sequence of the REC driver is read (bits 0 and 1). 2. ADML is the low-order 8 bits of ADM and can be manipulated in 1- or 8-bit units. Remark Cleared to 0: Counter is initialized to 0 within 16 clocks after the reset signal has been cleared (the contents before initialization are undefined).
26
Serial mode register 1 Serial shift register 1 Slave address register Serial mode register 2 Serial shift register 2 Serial control register 2 I2C bus status registerNote I2C bus shift registerNote Amplifier mode register 2 Head amplifier switch output control register Amplifier control register Amplifier mode register 0 Amplifier mode register 1 Gain control register VISS detection circuit shift register 0
Note
Remark Cleared to 0: Counter is initialized to 0 within 16 clocks after the reset signal has been cleared (the contents before initialization are undefined).
Data Sheet U12255EJ2V0DS00
27
Remark Cleared to 0: Counter is initialized to 0 within 16 clocks after the reset signal has been cleared (the contents before initialization are undefined).
28
Interrupt control register (INTTB) Interrupt control register (INTAD) Interrupt control register Interrupt control register (INTP2)Note 2 (INTCR40)Note 2
FFF0H FFF1H FFF2H FFF3H FFF4H FFF5H FFF6H FFF7H FFF8H FFFAH
Interrupt control register (INTUDC) Interrupt control register (INTCR30) Interrupt control register (INTCR50) Interrupt control register (INTCR13) Interrupt control register (INTCSI1) Interrupt control register (INTW) Interrupt control register (INTVISS) Interrupt control register (INTP1) Interrupt control register (INTP3) Interrupt control register (INTCSI2)
Notes 1. PD784928Y subseries only. 2. PIC2 and CRIC40 are at the same address (register). Remark Cleared to 0: Counter is initialized to 0 within 16 clocks after the reset signal has been cleared (the contents before initialization are undefined).
29
P60 Port 6 P67 P70-P77 P80 P82 Port 8 P87 P90 8 Port 7
P40 Port 4 P47 P50 Port 5 P110 P57 P113 P96 P100
Port 9
Port 10 P103
Port 11
Port 3
P30-P37
Can be set in input or output mode in 1-bit units. Can be set in input or output mode in 1-bit units. Can directly drive LED. Can be set in input or output mode in 1-bit units. Input port Can be set in input or output mode in 1-bit units. Input port
Port 4
P40-P47
Pull-up resistor is not provided. Pull-up resistors are connected to all pins in input mode. Pull-up resistor is not provided.
30
Port
Notes 1. Select one of the four trigger sources. 2. When the real-time output port mode is set by the port mode control register 8 (PMC8), the HASW and ROT-C signals that are set by the head amplifier switch output control register (HAPC) are directly output. The HASW and ROT-C signals are synchronized with HSW output (TM0-CR00 coincidence signal). However, the set signal is output immediately when the HAPC register is rewritten.
31
Internal bus
8 4 4
P07
P00
Remark INTCR01: TM0-CR01 coincidence signal INTCR02: TM0-CR02 coincidence signal Figure 3-7. Block Diagram of RTP8
Internal bus 8 Head amplifier output control register (HAPC) SEL SEL SEL PB PB PB 0 0 ROTC HASW ENV MOD2 MOD1 MOD0 TRGP80 HASW, ROT-C TM0-CR00 control circuit coincidence signal PMC80 0 PMC82 PMC83 PMC8 Output latch (P8) 8 Port 8 buffer register L (P8L) SEL 0 0 0 P8L4 P8L2 0 P8L0 MD80 Pseudo VSYNC output control circuit 8
32
TM0
Selector
CR00 CR01 CR02 Selector TM1 Trigger of P80 Interrupt and timer output
Interrupt CR13
TM5
CR50
Interrupt
33
34
Unit Name
Timer/Counter
Resolution
Register
Remark
35
36
Figure 3-10. Block Diagram of Super Timer Unit (TM0, FRC, TM1)
Selector Selector Selector
Clear TM0 CR00 CR01 CR02
DPGIN Divider
Selector
Selector
Mask
Output control circuit Output control circuit Output control circuit (Superimposition) RTP RTP, A/D INTCR00
Selector
DFGIN
Analog circuit
REEL1IN
Selector
Selector
Selector
Selector
Selector
Selector
To P80
Selector
Selector
CSYNCIN
INTCLR1
Selector
Selector
FRC Capture Capture Capture Capture Capture Capture CPT0 CPT1 CPT2 CPT3 CPT4 CPT5
REEL0IN
Mask
INTP3 Output control circuit PTO10 INTCR10 Output control circuit INTCR11 INTCR12 INTCR13 INTCR30 To PBCTL signal input block PTO11
CFGIN
Capture
CTL F/F
FFLVL
37
Clear TM2
CR20
INTCR20
(5) Timer 4 unit Timer 4 unit is a general-purpose 16-bit timer unit. This unit consists of a timer (TM4), a capture/compare register (CR40), and a capture register (CR41). The value of the timer is captured to CR40/CR41 when the INTP2 signal is input. This timer can be used to decode a remote controller signal. Figure 3-12. Block Diagram of Timer 4 Unit
INTP2
CR40 CR41
INTCR40
(6) Timer 5 unit Timer 5 unit is a general-purpose 16-bit timer unit. This unit consists of a timer (TM5) and a compare register (CR50). The timer is cleared by the TM5-CR50 coincidence signal, and at the same time, an interrupt request is generated. Figure 3-13. Block Diagram of Timer 5 Unit
Clear TM5
CR50
38
Selector
Selector
UP/DOWN UDC
PBCTL
UDCC
INTUDC
(8) PWM output unit The PWM output unit has three 16-bit accuracy output lines (PWM0, PWM1, and PWM5) and 8-bit accuracy output lines (PWM2 through PWM4). The carrier frequency of all the output lines is 62.5 kHz (fCLK = 8 MHz). PWM0 and PWM1 can be used to control the drum motor and capstan motor. Figure 3-15. Block Diagram of 16-Bit PWM Output Unit
PWMC0 To selector
16 MHz
PWMn
1/256
RESET
39
Internal bus
PWM2
PWM3
PWM4
PWMC1
8-bit comparator
8-bit comparator
PWM4
16 MHz
PWM counter
PWM3
PWM2
(9) VISS detection circuit Figure 3-17. Block Diagram of VISS Detection Circuit
PBCTL
Selector
INTVISS
40
CSYNC signal
fCLK/4
Selector
fCLK/8
Selector
S Q R
VSYNC
"00"
3.7 Serial Interface The PD784927 is provided with the serial interfaces shown in Table 3-6. Data can be automatically transmitted or received through these serial interfaces, when the macro service is used. Table 3-6. Types of Serial Interfaces
Name Serial interface channel 1 Clocked serial interface (3-wire) Bit length: 8 bits Clock rate: External clock/31.25 kHz/62.5 kHz/125 kHz/250 kHz/500 kHz/1 MHz (fCLK = 8 MHz) MSB first/LSB first selectable Serial interface channel 2 Clocked serial interface (3-wire) Bit length: 8 bits Clock rate: External clock/31.25 kHz/62.5 kHz/125 kHz/250 kHz/500 kHz/1 MHz (fCLK = 8 MHz) MSB first/LSB first selectable BUSY/STRB control function Serial interface channel 3 I2C bus interface For multimaster Function
41
Internal bus
SIn /BUSY
Selector
SIOn register
CSIMn register
SOn
INTCSIn
STRB
CSIC2 register
Internal bus
Remark The circuits enclosed in the broken line are provided to serial interface channel 2 only.
42
Selector
SDA SCL
SDA SCL
SDA SCL
SDA SCL
Slave IC Address 3
SDA SCL
Slave IC Address N
43
44
AVREF
. . .
Conversion trigger Control circuit Trigger enable 8 Delay detection circuit INTAD A/D conversion end interrupt
R/2 AVSS2
Trigger source select register 1 (TRGS1) A/D converter mode register (ADM) 16
3.9 VCR Analog Circuits The PD784927 is provided with the following VCR analog circuits: CTL amplifier RECCTL driver (rewritable) DPG amplifier DFG amplifier DPFG separation circuit (ternary separation circuit) CFG amplifier Reel FG comparator (2 channels) CSYNC comparator
45
RECCTL driver
RECCTL-
CTL head
VREF AMPC. 1 + -
AMPC. 1 CTLIN CTLOUT1 CTLM. 0-CTLM. 4 CTLOUT2 Waveform shaping circuit PBCTL signal (to timer unit) CTLMON (to P67) + Gain control signal generation circuit CTL detection flag L (AMPM0. 1) CTL detection flag S (AMPM0. 3) CTL detection flag clear (1 write to AMPM0. 6)
46
Selector
RECCTL+
AMPC.7 VREF AMPC.2 AMPM0.0 Drum PG signal DPGIN VREF + DPG amplifier 0 : ON AMPM0.2 AMPC.2 Selector 1 0 DPG comparator
VREF
DFGIN AMPM0.2 AMPM0.2 0 1 AMPC.2 DPFG separation circuit (ternary separation circuit) AMPM0.2 1 0 AMPC.2
Selector
47
CFGAMPO
AMPM0.0
AMPC.3
CFGCPIN +
Selector
(4) Reel FG comparators The reel FG comparator converts a reel FG signal that indicates the speed information of the reel motor into a logic signal. Two comparators, one for take-up and the other for supply, are provided. Figure 3-25. Block Diagram of Reel FG Comparators
VREF AMPC.6 AMPM0.0 1 REEL0IN Reel FG comparator 0 VREF AMPC.6 AMPM0.0 AMPC.6
Selector
Selector
48
AMPC.5
(6) Reference amplifier The reference amplifier generates a reference voltage (VREF) to be supplied to the internal amplifiers and comparators of the PD784927. Figure 3-27. Block Diagram of Reference Amplifier
AVDD1 +
ENCAP (AMPC.3)
VREFC
AVSS1
+ VREF DFG amplifier, DPG comparator, reel FG comparator, and CSYNC comparator)
Remark Multiple reference amplifiers are provided to assure the accuracy of the amplifiers and comparators.
49
PM65 PMC65 CMS5 Edge detection Pin level read WM.2 (enables/disables operation)
Selector
P65
P65
13
Selector
1 0
HW0
HW1 WM.2
Selector
WM.1
Selector
WM.6 INTW
50
CLOM7
CLOM6 CLOM5
ENCLO
Selector
Selector
fCLK/8
1 P60/STRB/CLO
RESET
Remark fCLK: internal system clock Caution Do not use the clock output function in the STOP mode. Clear ENCLO (CLOM.4) to 0 in the STOP mode. Figure 3-30. Application Example of Clock Output Function
PD784927
PD7503A
LCD 24 CLO SCK1 SI1 SO1 System clock CL1 SCK SO SI
51
CMS4 WM7
Selector
CLOM7
0 P61/BUZ
1 0
Selector
BUZ output
Selector
P64/BUZ
52
53
Macro
INTCPT3 EDVC output signal (CPT3 capture) INTCPT2 DFGIN pin input edge (CPT2 capture) INTCR12 PBCTL input edge/EDVC output signal (CR12 capture)
4 5 6 7 8 9 10
INTCR00 TM0-CR00 coincidence signal INTCLR1 CSYNCIN pin input edge INTCR10 TM1-CR10 coincidence signal INTCR01 TM0-CR01 coincidence signal INTCR02 TM0-CR02 coincidence signal INTCR11 TM1-CR11 coincidence signal INTCPT1 Pin input edge/EC output signal (CPT1 capture)
11 12 13 14 15
INTCR20 TM2-CR20 coincidence signal INTIIC INTTB INTAD INTP2 End of I2 C bus transfer
CRIC20 IICICNote TBIC ADIC PIC2 CRIC40 UDCIC CRIC30 CRIC50 CRIC13 CSIIC1 WIC VISIC PIC1 PIC3 CSIIC2 No No
Time base from FRC A/D converter conversion end INTP2 pin input edge
INTCR40 TM4-CR40 coincidence signal 16 17 18 19 20 21 22 23 24 25 Operand error Software INTUDC UDC-UDCC coincidence/UDC underflow
FE26H FE28H FE2AH FE2CH FE2EH FE30H FE32H FE34H FE36H FE3AH
0026H 0028H 002AH 002CH 002EH 0030H 0032H 0034H 0036H 003AH 003CH
INTCR30 TM3-CR30 coincidence signal INTCR50 TM5-CR50 coincidence signal INTCR13 TM1-CR13 coincidence signal INTCSI1 INTW INTVISS INTP1 INTP3 INTCSI2 End of serial transfer (channel 1) Overflow of watch timer VISS detection signal INTP1 pin input edge INTP3 pin input edge End of serial transfer (channel 2) Illegal operand of MOV STBC, #byte or LOCATION instruction Execution of BRK instruction Execution of BRKCS instruction
Yes
003EH
Note
Remark EVDC : Event divider compare register EC FRC : Event counter : Free running counter
Data Sheet U12255EJ2V0DS00
54
Macro service
Main routine
Main routine
Main routine
Note 2
Interrupt processing
Note 3
Main routine
Main routine
Note 4
SEL RBn
Interrupt processing
Main routine
Vectored interrupt
Main routine
Note 4
Interrupt processing
Main routine
Notes 1. When the register bank switching function is used and when initial values are set in advance to the registers 2. Selecting a register bank and saving PC and PSW by context switching 3. Restoring register bank, PC, and PSW by context switching 4. Saves PC and PSW to stack and loads vector address to PC
55
Register bank (0-7) A B R5 R7 X C R4 R6 VP UP D H E L <3> Switching register bank (RBS0-RBS2 n) <4> RSS 0 IE 0
<6> Exchange <2> Save Bits 8-11 of temporary register <5> Save V U T <1> Save PSW W
Temporary register
56
CPU
Memory
Read Write
Write Read
SFR
Internal bus
(1) Counter mode In this mode, the value of the macro service counter (MSC) is decremented when an interrupt request occurs. This mode can be used to execute the division operation of an interrupt request or count the number of times an interrupt request has occurred. When the value of the macro service counter has been decremented to 0, a vectored interrupt occurs.
MSC
-1
(2) Compound data transfer mode When an interrupt request occurs, data are simultaneously transferred from an 8-bit SFR to memory, a 16bit SFR to memory (word), memory (byte) to an 8-bit SFR, and memory (word) to a 16-bit SFR (3 points MAX. for each transfer). This mode can also be used to exchange data, instead of transferring data. This mode can be used for automatic transfer/reception by the serial interface or automatic updating of data/ timing by the serial output port. When the value of the macro service counter reaches to 0, a vectored interrupt request occurs.
Memory
SFR<4>-1
SFR<4>-2 SFR<4>-3
SFR<3>-1
SFR<3>-2
SFR<3>-3
. . .
Internal bus
SFR<2>-1 SFR<2>-2 SFR<2>-3 SFR<1>-1 SFR<1>-2 SFR<1>-3
Internal bus
57
Data 2 Data 1
Data 2 Data 1
Internal bus
Internal bus
SFR
SFR
(4) Data pattern identification mode (VISS detection mode) This mode of macro service is for detection of the VISS signal and is used in combination with a pulse width detection circuit. When an interrupt request occurs, the content of bit 7 of an SFR (usually, TMC3) specified by SFR pointer 1 is shifted into the buffer area. At the same time, the data in the buffer area is compared with the data in the compare area. If the two data coincide, a vectored interrupt request is generated. When the value of the macro service counter is decremented to 0, a vectored interrupt request occurs. It can be specified by option that the value of an SFR (usually, CPT30) specified by SFR pointer 2 be multiplied by a coefficient and the result of this multiplication be stored to an SFR (usually, CR30) specified by SFR pointer 3 (this operation is to automatically update an identification threshold value when the tape speed fluctuates).
Coefficient (memory)
CPT30 TM3
Coincidence
Multiplier
CR30
CTL F/F (bit 7 of TMC3) Vectored interrupt
58
FE50H
High-order address
Macro service counter (MSC = 2) Memory pointer H (= FD) Macro service channel Memory pointer L (= 50) ddccbbaa (= 01000100B) SFR pointer <2> (SFRP2 = 85H) SFR pointer <4> (SFRP4 = 85H)
Channel pointer (= 50H) Macro service control word Mode register (= 10110011B) FE2EH Low-order address
Transmit data 3 FD52H SIO1 (FF85H) <3> Transmit data 2 FD51H <2> (Exchange 1) (Transmit data 1) FD50H <1> Transfer is started by writing transmit data 1 to SIO1 by software.
SO1
59
Channel pointer (= 7FH) FE2EH Mode register (= 00010001B) Starts macro service when INTCSI1 occurs
SI1
SIO1 (FF85H)
60
CPT30 High-order address FE50H Macro service counter (MSC = FFH) SFR pointer 2 (SFRP2 = 56H) Coefficient (6EH: 43%) SFR pointer 3 (SFRP3 = 5CH) SFR pointer 1 (SFRP1 = 3BH) Buffer size specification register (64 bits: 8H) 1 8 bytes 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 Bit 7 0 TMC3 Multiplier CR30 TM3
1050H 8 bytes
Compare area pointer (high): 10H Compare area pointer (low): 50H Coincidence (vectored interrupt) Channel pointer (= 50H) FE0CH Mode register (= 00010100B) (CTL signal input edge detection interrupt) Low-order address
61
STOP mode
These modes are programmable. The macro service can be started in the HALT mode. Figure 4-4. Status Transition of Standby Function
Ma
Normal operation
En En
cro fo
do
se
rvi
do
fm
ne ro
ce
ac
pro se
req ssi
ce
ue
st
HAL
put
f os nd o
req
Tm
cil at
io
rvi
ng
Sets HAL
ce
rupt
RE
P2
pu
Set
req
I in
INT
r co
owe
ce
NM
W,
rvi
wp
INT
cro
s lo
Ma
Set
Notes 1. NMI input means starting NMI by NMI pin input, watch interrupt, or key interrupt input. 2. Unmasked interrupt request
62
En
do
fo
ne
pro
se
ce
ss
ing
TO
t Note
inte
SE
mpt
Macro service
ue st
pt
ET in
T in
rru
ion
requ
put
nsu
sS
est
Note 2
pu
te 1
INTP1 INTP2 KEY0 KEY1 KEY2 KEY3 KEY4 Cleared when "0" is written to KEYC.7 Mask KEYC.6 Mask KEYC.5 Mask KEYC.4 S Q R WM.6 Cleared when "0" is written to KEYC.0
Selector
S Q R
KEYC.7
KEYC.0
Mask WM.3
63
Selector
X2 16 MHz or 8 MHz
1/2
Selector
Selector
64
PD784927
X1
Main system clock oscillation circuit
The clock generation circuit generates and controls the internal system clock (CLK) to be supplied to the CPU and
CC.7 STBC.4, 5 Low-frequency oscillation mode fXX Normal mode Oscillation stabilization timer 1/2 1/2 1/2 fXX/16 (fXX/8)Note 1 fXX/8 (fXX/4)Note 1 STBC.6
fCLK
XT1
Subsystem clock oscillation circuit
fXT
Watch timer
Notes 1. fXX: oscillation frequency, ( ): in low-frequency oscillation mode. 2. The peripheral hardware units that can operate with the subsystem clock have some restrictions. For details, refer to PD784928, 784928Y Subseries Users Manual-Hardware (U12648E).
Main system clock oscillation circuit During reset, oscillation is unconditionally stopped. fCLT
RESET input
The RESET pin is provided with an analog delay noise rejection circuit to prevent malfunctioning due to noise. Figure 4-8. Accepting Reset Signal
Analog delay
Analog delay
RESET input
Internal clock
65
(ADD)Note 1 (ADD)Note 1 (ADD)Notes 1,6 (ADD)Note 1 ADDNote 1 r MOV ADDNote 1 (MOV) (XCH) MOV XCH MOV XCH MOV XCH MOV XCH
(ADD)Note 1 (ADD)Note 1
Notes 1. ADDC, SUB, SUBC, AND, OR, XOR, and CMP are the same as ADD. 2. Either the second operand is not used, or the second operation is not an operand address. 3. ROL, RORC, ROLC, SHR, and SHL are the same as ROR. 4. XCHM, CMPME, CMPMNE, CMPMNC, and CMPMC are the same as MOVM. 5. XCHBK, CMPBKE, CMPBKNE, CMPBKNC, and CMPBKC are the same as MOVBK. 6. If saddr2 instead of saddr is used in this combination, the code length of some instructions is short.
66
saddrp saddrp
sfrp
!addr16 !!addr24
[WHL+]
byte
None
Note 2
(MOVW) (XCHW)
(MOVW) (XCHW)
(MOVW) XCHW
MOVW XCHW
(MOVW) (XCHW)
MOVW XCHW
MOVW XCHW
MOVW XCHW
MOVW
SHRW SHLW
(MOVW)Note 3 MOVW
MOVW ADDWNote 1
sfrp
MOVW
MOVW
MOVW
ADDWNote 1 (ADDW)Note 1 ADDWNote 1 !addr16 !!addr24 mem [saddrp] [%saddrg] PSW MOVW MOVW (MOVW) MOVW
PUSH POP
SP
ADDWG SUBWG
post
[TDE+] byte
(MOVW)
Notes 1. SUBW and CMPW are the same as ADDW. 2. Either the second operand is not used, or the second operation is not an operand address. 3. If saddr2 instead of saddr is used in this combination, the code length of some instructions is short. 4. MULUW and DIVUX are the same as MULW.
67
Note
Either the second operand is not used, or the second operation is not an operand address.
(4) Bit manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR, BFSET
2nd Operand CY saddr.bit sfr.bit A.bit X.bit PSWL.bit PSWH.bit mem2.bit iaddr16.bit !addr24.bit MOV1 AND1 OR1 XOR1 MOV1 /saddr.bit /sfr.bit /A.bit /X.bit /PSWL.bit /PSWH.bit /mem2.bit /!addr16.bit /!!addr24.bit AND1 OR1 NoneNote
1st Operand CY
Note
Either the second operand is not used, or the second operation is not an operand address.
68
Note
BNZ, BNE, BZ, BE, BNC, BNL, BL, BNV, BPO, BV, BPE, BP, BN, BLT, BGE, BLE, BGT, BNH, and BH are the same as BC.
(6) Other instructions ADJBA, ADJBS, CVTBW, LOCATION, SEL, NOT, EI, DI, SWRS
69
Caution
If the rated value of even one of the above parameters is exceeded even momentarily, the quality of the product may be degraded. Absolute maximum ratings therefore specify the values exceeding which the product may be physically damaged. Never exceed these values when using the product.
Operating Conditions
Clock Frequency 4 MHz fXX 16 MHz 32 kHz fXT 35 kHz Operating Ambient Temperature (TA) 10 to +70C Operating Conditions All functions CPU function only Subclock operation (CPU, watch, and port functions only) Supply Voltage (VDD) +4.5 to +5.5 V +4.0 to +5.5 V +2.7 to +5.5 V
70
Recommended Circuit
MIN. 4
MAX. 16
Unit MHz
C1
C2
Oscillator Characteristics (subclock) (TA = 10 to +70C, VDD = AVDD = 2.7 to 5.5 V, VSS = AVSS = 0 V)
Resonator Crystal resonator
XT1 XT2 VSS
Recommended Circuit
MIN. 32
MAX. 35
Unit kHz
C1
C2
Caution
When using the main system clock and subsystem clock oscillator, wire the portion enclosed by the broken line in the above figures as follows to avoid the adverse influence of wiring capacitance: Keep the wiring length as short as possible. Do not cross the wiring with the other signal lines. Do not route the wiring in the neighborhood of a signal line through which a high alternating current flows. Always keep the ground point of the capacitor of the oscillator to the same potential as VSS. Do not ground the capacitor to a ground pattern to which a high current flows. Do not extract signals from the oscillation circuit. Exercise particular care in using the subsystem clock oscillator because the amplification factor of this circuit is kept low to reduce the current consumption.
Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation.
71
TYP.
MAX. 0.3 VDD 0.2 VDD 0.4 VDD V DD V DD 1.0 0.6 0.45 0.25
Unit V V V V V V V V V V V V
V DD 1.0 V DD 0.4 10 10 30 50
A A
mA
50
80
10
25
mA
25
50
V DDDR I DDDR
STOP mode STOP mode Subclock oscillates VDDDR = 5.0 V STOP mode Subclock oscillates VDDDR = 2.7 V STOP mode Subclock stops VDDDR = 2.5 V
2.5 18 50
A A A
k
2.5
10
0.2
7.0
Pull-up resistor
RL
VI = 0 V
25
55
110
Notes 1. RESET, IC, NMI, INTP0-INTP2, P61/SCK1/BUZ, P63/SI1, SCK2, SI2/BUSY, P65/HWIN, P91/KEY0 to P95/KEY4 2. P40 to P47 3. In the STOP mode in which the subclock oscillation is stopped, disconnect the feedback resistor, and connect the XT1 pin to VDD. 4. P46, P47
72
Serial interface (1) SIOn: n = 1 or 2 (TA = 10 to +70C, VDD = AVDD = 4.5 to 5.5 V, VSS = AVSS = 0 V)
Parameter Serial clock cycle time Symbol tCYSK Input Output Conditions External clock fCLK1/8 fCLK1/16 fCLK1/32 fCLK1/64 fCLK1/128 fCLK1/256 Serial clock high- and low-level widths SIn setup time (vs. SCKn ) SIn hold time (vs. SCKn ) SOn output delay time (vs. SCKn ) tWSKH tWSKL tSSSK tHSSK tDSSK Input Output External clock Internal clock MIN. 1.0 1.0 2.0 4.0 8.0 16 32 420 tCYSK/2 50 100 400 0 300 MAX. Unit
s s s s s s s
ns ns ns ns ns
Remarks 1. fCLK1: operating clock of peripheral circuit (8 MHz) 2. n = 1 or 2 (2) SIO2 only (TA = 10 to +70C, VDD = AVDD = 4.5 to 5.5 V, VSS = AVSS = 0 V)
Parameter SCK2(8) STRB Strobe high-level width BUSY setup time (vs. BUSY detection timing) BUSY hold time (vs. BUSY detection timing) BUSY inactive SCK2(1) tLBUSY tCYSK + tWSKH t HBUSY 100 ns Symbol tDSTRB tWSTRB t SBUSY Conditions MIN. tWSKH tCYSK 30 100 MAX. tCYSK tCYSK + 30 ns ns Unit
Remarks 1. The value in ( ) following SCK2 indicates the number of SCK2. 2. BUSY is detected after the time of (n + 2) x tCYSK (n = 0, 1, and so on) in respect to SCK2 (8) . 3. BUSY inactive SCK2 (1) is the value when data has been completely written to SIO2.
73
s s s s s s s
ns ns ns
Data setup time SDA and SCL signal rise time SDA and SCL signal fall time Stop condition setup time Pulse width of spike restrained by input filter Each bus line capacitative load
s
ns
Cb
400
400
pF
Notes 1. The first clock pulse is generated at the start condition after this period. 2. The device needs to internally supply a hold time of at least 300 ns for the SDA signal to fill the undefined area at the falling edge of the SCL (VIHmin. of the SCL signal). 3. Unless the device extends the low hold time (tLOW) of the SCL signal, it is necessary to fill only the maximum data hold time (tHD : the following conditions: When the device does not extend the low hold time of the SCL signal tSU :
DAT DAT).
4. The high-speed mode I2C bus can be used in the standard mode I2C bus system. In this case, satisfy
250 ns
When the device extends the low hold time of the SCL signal Send the next data bit to the SDA line before releasing the SCL line (tRmax. + tSU:DAT = 1000 + 250 = 1250 ns : in the standard mode I2C bus specification) 5. Cb: Total capacitance of one bus line (unit: pF)
74
s
ns ns
s s
ns ns ns
s
ns
s
ns
s s
ms
In STOP mode, for releasing STOP mode INTP2 high-level width tWIPH2 In normal mode, with main clock Normal mode, with subclock Sampling = fCLK Sampling = fCLK/128 Sampling = fCLK Sampling = fCLK/128
s
ns
s s
ms
In STOP mode, for releasing STOP mode RESET low-level width tWRSL
s s
Note
If a high or low level is successively input two times during the sampling period, a high or low level is detected.
Remark tCKL1: operating clock cycle time of peripheral circuit (125 ns)
75
Remarks 1. n: system clock division 2. T = 1/fCLK Data hold characteristics (TA = 10 to +70C, VDD = AVDD = 2.5 to 5.5 V, VSS = AVSS = 0 V)
Parameter Low-level input voltage High-level input voltage Symbol VIL VIH Condition Special pins (pins in Note) MIN. 0 0.9 VDDDR TYP. MAX. 0.1 VDDDR VDDDR Unit V V
Note
RESET, IC, NMI, INTP0-INTP2, P61/SCK1/BUZ, P63/SI1, SCK2, SI2/BUSY, P65/HWIN, P91/KEY0-P95/ KEY4
Watch function (TA = 10 to +70C, VDD = AVDD = 2.7 to 5.5 V, VSS = AVSS = 0 V)
Parameter Subclock oscillation hold voltage Hardware watch function operating voltage Symbol VDDXT VDDW Condition MIN. 2.7 2.7 MAX. Unit V V
Subclock oscillation stop detection flag (TA = 10 to +70C, VDD = AVDD = 4.5 to 5.5 V, VSS = AVSS = 0 V)
Parameter Oscillation stop detection width Symbol tOSCF Condition MIN. 45 MAX. Unit
A/D converter characteristics (TA = 10 to +70C, VDD = AVDD = AVREF = 4.5 to 5.5 V, VSS = AVSS = 0 V)
Parameter Resolution Total error Quantization error Conversion time tCONV Bit 4 of ADM = 0 Bit 4 of ADM = 1 Sampling time t SAMP Bit 4 of ADM = 0 Bit 4 of ADM = 1 Analog input voltage Analog input impedance AV REF current V IAN Z AN AI REF 160t CLK1 80t CLK1 32t CLK1 16t CLK1 0 1000 0.4 1.2 AV REF AVREF = VDD Symbol Condition MIN. 8 2.0 1/2 TYP. MAX. Unit bit % LSB
s s s s
V M mA
76
Note
High comparator set voltage of waveform shaping VPBCTLHS High comparator reset voltage of waveform shaping VPBCTLHR Low comparator set voltage of waveform shaping VPBCTLLS
Low comparator reset voltage of waveform shaping VPBCTLLR Comparator Schmitt width of waveform shaping High comparator voltage of CTL flag S Low comparator voltage of CLT flag S High comparator voltage of CTL flag L Low comparator voltage of CTL flag L VPBSH VFSH VFSL VFLH VFLL
VREF + 1.00 VREF + 1.05 VREF + 1.10 VREF 1.10 VREF 1.05 VREF 1.00 VREF + 1.40 VREF + 1.45 VREF + 1.50 VREF 1.50 VREF 1.45 VREF 1.40
77
Note
The conditions include the following circuit and input signal. Input signal : Sine wave input (5 mVp-p) fi = 1 kHz Voltage gain: 50 dB
1 k + 22 F 330 k CFGIN
PD784927
CFGAMPO 0.01 F
CFGCPIN
DFG amplifier (AC coupling) (TA = 25C, VDD = AVDD = 5 V, VSS = AVSS = 0 V)
Parameter Voltage gain Feedback resistance Input protection resistance High comparator voltage Low comparator voltage Symbol GDFG R FDFG R IDFG V DFGH VDFGL Condition f i = 900 Hz, open loop MIN. 50 160 400 150 VREF + 0.07 VREF + 0.10 VREF + 0.14 VREF 0.14 VREF 0.10 VREF 0.07 640 TYP. MAX. Unit dB k V V
Caution
Set the input resistance connected to the DFGIN pin to 16 k or below. Connecting a resistor exceeding that value may cause the DFG amp to oscillate.
78
SELDPGHL0 = 0, SELDPGHL1 = 0 VREF + 0.02 VREF + 0.05 VREF + 0.08 SELDPGHL0 = 1, SELDPGHL1 = 0 VREF + 0.56 VREF + 0.60 VREF + 0.64 SELDPGHL0 = 0, SELDPGHL1 = 1 VREF 0.44 VREF 0.40 VREF 0.36 SELDPGHL0 = 0, SELDPGHL1 = 0 VREF 0.08 VREF 0.05 VREF 0.02 SELDPGHL0 = 1, SELDPGHL1 = 0 VREF + 0.36 VREF + 0.40 VREF + 0.44 SELDPGHL0 = 0, SELDPGHL1 = 1 VREF 0.64 VREF 0.60 VREF 0.56
Caution
When both the SELDPGHL0 and SELDPGHL1 are set to 0, the DPG amplifier is not used. Therefore, be sure to set AMPC.7 (ENDPG) to 0.
CSYNC comparator (AC coupling) (TA = 25C, VDD = AVDD = 5 V, VSS = AVSS = 0 V)
Parameter Input impedance High comparator voltage Low comparator voltage Symbol ZICSYN VCSYNH VCSYNL Condition MIN. 20 TYP. 50 MAX. 100 Unit k V V
VREF + 0.07 VREF + 0.10 VREF + 0.13 VREF 0.13 VREF 0.10 VREF 0.07
Reel FG comparator (AC coupling) (TA = 25C, VDD = AVDD = 5 V, VSS = AVSS = 0 V)
Parameter Input impedance High comparator voltage Low comparator voltage Symbol ZIRLFG VRLFGH VRLFGL Condition MIN. 20 TYP. 50 MAX. 100 Unit k V V
VREF + 0.02 VREF + 0.05 VREF + 0.08 VREF 0.08 VREF 0.05 VREF 0.02
79
tWSKH
tSSSK
tHSSK
SIn
Input data
80
STRB
tWSKL SCK2 7
BUSY
Active high
Caution
When an external clock is selected as the serial clock, do not use the busy control or strobe control.
81
SDA tBUF Stop condition Start condition Restart condition Stop condition
82
tWCTH When DFGIN, CFGIN, DPGIN, REEL0IN, or REEL1IN logic level is input 0.8 VDD 0.8 V
tWCTL
tWCR1L
tWNIL
tWIPL0
tWIPL1
INTP1, KEY0-KEY4
tWIPL2
83
tWRSL
RESET 0.8 V
84
75 76
51 50
C D
S Q R
100 1
26 25
F G P H I
M
J K M
N
NOTE Each lead centerline is located within 0.08 mm (0.003 inch) of its true position (T.P.) at maximum material condition.
L
ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 16.000.20 14.000.20 14.000.20 16.000.20 1.00 1.00 0.22 +0.05 0.04 0.08 0.50 (T.P.) 1.000.20 0.500.20 0.17 +0.03 0.07 0.08 1.400.05 0.100.05 3 +7 3 1.60 MAX. INCHES 0.6300.008 0.551 +0.009 0.008 0.551 +0.009 0.008 0.6300.008 0.039 0.039 0.0090.002 0.003 0.020 (T.P.) 0.039 +0.009 0.008 0.020 +0.008 0.009 0.007 +0.001 0.003 0.003 0.0550.002 0.0040.002 3 +7 3 0.063 MAX. S100GC-50-8EU
Remark The package dimensions and materials of ES versions are the same as those of mass-production versions.
85
80 81
51 50
S Q R
100 1
31 30
F G H I
M
K M N L
ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 23.60.4 20.00.2 14.00.2 17.60.4 0.8 0.6 0.300.10 0.15 0.65 (T.P.) 1.80.2 0.80.2 0.15 +0.10 0.05 0.10 2.70.1 0.10.1 5 5 3.0 MAX. INCHES 0.9290.016 0.795 +0.009 0.008 0.551 +0.009 0.008 0.6930.016 0.031 0.024 0.012 +0.004 0.005 0.006 0.026 (T.P.) 0.071 +0.008 0.009 0.031 +0.009 0.008 0.006 +0.004 0.003 0.004 0.106 +0.005 0.004 0.0040.004 5 5 0.119 MAX. P100GF-65-3BA1-3
NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition.
Remark The package dimensions and materials of ES versions are the same as those of mass-production versions.
86
PD784927GF--3BA : 100-pin plastic QFP (14 20 mm) PD784928GF--3BA : 100-pin plastic QFP (14 20 mm) PD784927YGF--3BA: 100-pin plastic QFP (14 20 mm) PD784928YGF--3BA: 100-pin plastic QFP (14 20 mm)
Soldering Method Soldering Conditions Package peak temperature: 235 C, Time: 30 secs. max. (210 C min.), Number of times: three times max. Package peak temperature: 215 C, Time: 40 secs. max. (200 C min.), Number of times: three times max. Wave soldering Solder bath temperature: 260 C max., Time: 10 secs. max., Number of times: once, Preheating temperature: 120 C max.(Package surface temperature) Pin temperature: 300 C max., Time: three secs. max. (per device side) WS60-00-1 Recommended Conditions Symbol IR35-00-3
Infrared reflow
VPS
VP15-00-3
Partial heating
Caution Do not use two or more soldering methods in combination (except partial heating).
87
Adapter for writing 100-pin plastic LQFP (GC-8EU type) flash memory. Be sure to connect depending on the target product. Adapter for writing 100-pin plastic QFP (GF-3BA type) flash memory. Be sure to connect depending on the target product.
88
(4) Real-time OS
RX78K/IV MX78K4 Real-time OS for 78K/IV series OS for 78K/IV series
89
EWS HP9000 series 700 TM [HP-UX TM ] SPARCstation TM [SunOS TM , Solaris TM ] NEWSTM (RISC) [NEWS-OS TM]
[Windows TM ]
Note Note
Note
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PD784928, 784928Y Subseries Users Manual - Hardware PD784927, 784928, 784927Y, 784928Y Data Sheet PD784928 Subseries Special Function Register Table PD78F4928 Preliminary Product Information PD784928Y Subseries Special Function Register Table PD78F4928Y Preliminary Product Information
PD784915, 784928, 784928Y Subseries Application Note - VCR Servo
78K/IV Series Users Manual - Instruction 78K/IV Series Instruction Table 78K/IV Series Instruction Set 78K/IV Series Application Note - Software Basics
U12648J U12255J U12798J U12188J U12719J U12271J U11361J U10905J U10594J U10595J U10095J
External Part User Open U10092J Interface Specifications Reference Reference Reference U12796J U10440J U11960J
Caution
The contents of the above related documents are subject to change without notice. Be sure to use the latest edition of the document when designing your system.
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Other documents
Document Japanese SEMICONDUCTORS SELECTION GUIDE Products & Packages (CD-ROM) Semiconductor Device Mounting Technology Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control System Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) Guide to Microcomputer-Related Products by Third Party X13769X C10535J C11531J C10983J C11892J U11416J C10535E C11531E C10983E C11892E Document No. English
Caution
The contents of the above related documents are subject to change without notice. Be sure to use the latest edition of the document when designing your system.
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Purchase of NEC I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I 2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
EEPROM and FIP are trademarks of NEC Corporation. Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or other countries. PC/AT and PC DOS are trademarks of IBM Corporation. HP9000 Series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. Solaris and SunOS are trademarks of Sun Microsystems, Inc. NEWS and NEW-OS are trademarks of Sony Corporation.
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Regional Information
Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify:
Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.
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The documents referred to in this publication may include preliminary versions. However, preliminary versions are not marked as such.
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
The information in this document is current as of December, 1999. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above).
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