Semiconductor
Technologies
Quality Control
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Figure 10.1: Data collected for the hermetic lid length at incoming store room.................... 5
Figure 10.2: Statistical control chart of the data shown in Fig. 10.1 using X and R as
estimate .............................................................................................................. 5
Figure 10.3: Statistical control chart of the data shown in Fig. 10.1 using X and s as
estimate .............................................................................................................. 6
Figure 10.4: A pre-control chart ............................................................................................. 9
Figure 10.5: Data for D-NOM chart ..................................................................................... 10
Figure 10.6: Data for standardized X and R charts ............................................................. 12
Figure 10.7: Control chart of standardized mean X ............................................................ 13
Figure 10.8: Control chart of standardized range R ............................................................. 13
Figure 10.9: Processes with same Cpk but different Cpm indices .......................................... 19
Figure 10.10: Failure rate versus time for a typical integrated circuit ................................... 25
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Chapter 10
Quality Control
_____________________________________________
10.0 Introduction
In integrated circuit manufacturing involves design, fabrication, assembly, and
test processes. To ensure that each process step conforms to specifications, it is
necessary to implement quality control scheme. Quality control
monitoring/checking has become an important process and is normally imposed
at the end of certain critical process steps. Besides the quality control at in
process step, quality control procedure is also required to be implemented at the
incoming material inspection stage.
With the quality control in place at critical process steps and at incoming
material acceptance stage, it is also necessary to monitor the process
stability/reliability and process capability of the machine/equipment used to
process the device.
In this section, student will learn how in process quality control and
incoming control are performed. The concepts of how to establish statistical
process control charts and at the same time learn how use the collect data to
determine the process capability ratio CP and process capability index CPK of the
machine/equipment used for the manufacturing processes. At the last of
learning, the concepts and methods used to determine the reliability of
integrated circuit are studied.
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10 Quality Control
been taken, quality control personnel will take new samples to check for
conformance to specifications. When conformance is achieved, the particular
process is then released to manufacturing for further processing of device. The
failed sample lot is either re-processed or declared as total reject.
Let’s take a critical process step, which is wire bonding. After wire
bonding process, the quality control personnel will pull the samples according
to specific quality sampling plan to check the wire loop height and wire bond
strength according to specifications. Besides, he/she also checks if there is
missing wire, bond crack, wrong bonding etc. If there is any non-conformance
detected, stop process notice is issued. The process will only be allowed after
collective action has been taken and the subsequent samples pass the quality
control check/test.
In test operating, the quality control personnel would pick the sample
according to the quality sampling plan to test to see if all selected samples pass
the electrical test specifications. If selected samples fail the sampling plan, the
tested lot is normally re-tested and re-submitted for sampling test.
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10 Quality Control
When setting up a hypothesis testing for the mean µ, one considers the null
hypothesis µ = µ0 versus the alternative hypothesis µ ≠ µ0, selecting an unbiased
statistic with minimum variance as possible, which means x = µ , specify
probability of Type I error, which is α = P[Rejecting H0, when it is true], and
using α and distribution of x to set-up acceptance region for x that is accept the
null hypothesis H0 if µ 0 − Z α / 2 σ 0 / n < x < µ 0 + Zα / 2 σ 0 / n and reject the null
hypothesis H0 if x < µ 0 − Z α / 2 σ 0 / n or x > µ 0 + Zα / 2 σ 0 / n .
The statistical control chart has three lines, which are upper control limit
line UCL, center line CL, and lower control limit line LCL. These lines are
established based on the data collected over a period of time from a normal
conformance process and in the control acceptance region mentioned in the
above paragraphs. Thus, the upper control limit UCL line is defined as
UCL = µ 0 + Zα / 2 σ 0 / n (10.1)
LCL = µ 0 − Z α / 2 σ 0 / n (10.2)
CL = µ0 (10.3)
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10 Quality Control
UCL = µ 0 + 3σ 0 / n (10.4)
LCL = µ 0 − 3σ 0 / n (10.5)
The type II error will not be discussed here, where it defines β equals to the
probability of the accepting the null hypothesis when actually it is not true.
Once the control chart is established and in used. If the trend of chart has
any of the following stated abnormality, collective action must be taken for the
specific process. The rules
Presented in this section are two ways to established the statistical control chart
SPC for process mean X using X , R /d2, and s /c4.
Let’s use the data shown in Fig. 10.1 to illustrate how µ0 and σ0 can be
estimated by the mean X of the sample at defined interval and the range R of the
sample to estimate the value of σ0.
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10 Quality Control
Figure 10.1: Data collected for the hermetic lid length at incoming store room
Let X be the grand average of the mean X for five batches of hermetic lid
length and R be the grand average of the range R for five batches of hermetic
lid length. The mean µ0 can then be estimated by X and the standard deviation
(σ0) is estimated by R /d2, whereby the value of d2 can be obtained from the
constant table (refer to Appendix B) used for estimation and construction of
control chart. For the sample size of n = 3, d2 value is 1.6929. Thus, the
established lines of the control chart are: UCL = X + 3R /(d 2 n ) =
4.48 + 3x 0.18 /(1.6929 3 ) = 4.66, LCL = X − 3R /(d 2 n ) = 4.48 − 3x 0.18 /(1.6929 3 ) =
4.29, and CL = 4.48.
The plot of the established statistical control chart is shown in Fig. 10.2.
Figure 10.2: Statistical control chart of the data shown in Fig. 10.1 using X and R as
estimate
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10 Quality Control
Let σ or s be the grand average of the standard deviation σ then the standard
deviation σ0 is estimated by σ /c4, whereby the value of c4 can be obtained from
the constant table used for estimation and construction of control chart. For the
sample size of n = 3, c4 value is 0.9213. Thus, the established lines of the
control chart are: UCL = X + 3σ /(c 4 n ) = 4.48 + 3x 0.095 /(0.9213 3 ) = 4.65, LCL =
X − 3σ /(c 4 n ) = 4.48 − 3x 0.095 /(0.9213 3 ) = 4.30, and CL = 4.48.
The plot of the established statistical control chart is shown in Fig. 10.3.
Figure 10.3: Statistical control chart of the data shown in Fig. 10.1 using X and s as
estimate
Presented in this section are two ways to established the statistical control chart
SPC for process standard deviation s using R /d2, and s /c4 statistics. The lengthy
discussion of how to establish the statistical control chart using these two
statistics will not be described.
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10 Quality Control
The formulae for the lines of the control chart for process standard deviation
established using R /d2 statistics are
LCL = (1 − 3d 3 / d 2 )R = D 3 R (10.6)
UCL = (1 + 3d 3 / d 2 )R = D 4 R (10.7)
CL = R (10.8)
The values of d2, d3, D3, and D4 can be obtained from the constant table (refer to
appendices) used for estimation and construction of control chart. For the
sample size of n = 3, d2 = 1.6929, d3 = 0.8884, D3 = 0, and D4 = 2.5743. One
may ask; why D3 is equal 0 instead of -0.5743. The reason being the standard
deviation cannot be a smaller than 0. Using data shown in Fig. 2.19, the lines of
the control chart are: LCL = (1 − 3d 3 / d 2 )R = 0, UCL = (1 + 3d 3 / d 2 )R = 0.4639, and
CL = R = 0.18.
The formulae for the lines of the control chart for process standard device
established using s /c4 statistics are
3 1 − c4
LCL = 1 − s = B3 s
(10.10)
c4
3 1− c4
UCL = 1 + s = B 4 s
(10.11)
c4
CL = s (10.12)
The values of c4, B3, and B4 can be obtained from the constant table used for
estimation and construction of control chart. For the sample size of n = 3, c4 =
0.8862, B3 = 0, and B4 = 2.5684. One may ask why B3 is equal 0 instead of -
0.14198. The reason being the standard deviation cannot be a smaller than 0.
Using data shown in Fig. 10.1, the lines of the control chart are: LCL =
3 1 − c4 3 1− c4
1 − s = B3 s = 0, UCL = 1 + s = B 4 s = 0.244, and CL = s = 0.095.
c4 c4
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X chart is meant for individual measurement and R chart is meant for moving
range. The sample taken at designated interval is one not like the earlier case
that has more than one. The acceptable control limits of the process mean X is
µ 0 ± 3σ 0 / n = µ 0 ± 3R / (d 2 n ) taking α is equal to 0.0026. Since for individual
measurement n = 1, then the for formulae for the lines of control chart are
LCL = X − 3R / d 2 (10.13)
CL = X (10.14)
UCL = X + 3R / d 2 (10.15)
Since moving range is calculated from two successive data, thus, d2 is equal to
1.128 taken from the constant table used for estimation and construction of
control chart. The formulae for the lines of control charts are:
LCL = X − 3R / d 2 = X − 2.66R , CL = X , and UCL = X + 3R / d 2 = X + 2.66R .
The formulae for the statistical control chart for moving range R chart with
assumption that α is equal to 0.0026 are
LCL = D 3 R (10.16)
CL = R (10.17)
UCL = D 4 R (10.18)
From the constant table used for estimation and construction of control chart, D3
= 0 and D4 = 3.2672. Thus, the formulae for the moving range R control charts
are; LCL = 0 , CL = R , and UCL = 3.267R .
There are situations where it may be difficult to take a sample of size greater
than one or when only one measurement is meaningful each time. Some
examples of these situation are the production rate is very slow or the batch size
is very small or a continuous process such as chemical process, measurement on
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10 Quality Control
In this example, these lines are at 0.5 – 1/4x(0.502 – 0.498) = 0.499 and 0.5
+ 1/4x(0.502 – 0.498) = 0.501. The regions above the USL and below the LSL
are called the red zone, the interval between nominal size – 1/4 x total tolerance
and nominal size + 1/4 x total tolerance is called the green zone, and the regions
between the red and green zones are called the yellow zone. The control chart is
shown in Fig. 10.4.
1. Collect the measurements and plot them on the chart until five
consecutive values fall in the green zone.
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10 Quality Control
2. If a measurement data falls in the yellow zone, restart the count to obtain
five consecutive pieces in the green zone. Do not adjust the process.
3. If two consecutive data fall in the yellow zone or one value falls in the
red zone then adjust the process.
4. When five consecutive measurement data fall in the green zone, approves
the setup as in-control process and starts regular manufacturing.
During regular manufacturing, sample two consecutive components every h
interval such as 10 minutes and follow these rules:
1. If the first data falls in the green zone, do not plot the second value and
continue the process.
2. If the first data falls in the red zone, stop the process and investigate.
3. If the first data falls in the yellow zone, then plot the second value. If it
falls in the green zone then continue the process, otherwise, stop the
process and investigate.
R = 2.375
Figure 10.5: Data for D-NOM chart
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10 Quality Control
D-NOM charts are established based on the assumptions that the process
standard deviation is the same for all parts and sample size is constant. The
control limits of the established are X and R charts are as follows:
X chart
UCL = X + A 2 R (10.19)
LCL = X − A 2 R (10.20)
CL = X (10.21)
R chart
UCL = D 4 R (10.22)
LCL = D 3 R = 0 (10.23)
CL = R (10.24)
These charts are used if the assumption that the standard deviation is not the For
the part type j test statistic, let X0j be the target value for part type j and R j be
the average range of part type j then
(
X chart test statistics = x j − X 0j / R j = ) (10.25)
ij
i =1
test statistics is also equal to (x ij )/ R j if X0j is equal to zero. The control limits of
standardized X shall be
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10 Quality Control
UCL = A2 (10.27)
CL = 0.0 (10.28)
The R chart test statistic is equal to R = R ij / R j and the control limits are
LCL = D3 (10.29)
UCL = D4 (10.30)
CL = 1.0 (10.31)
Let’s now use the data shown in Fig. 10.5 to establish standardized X and R
charts.
Dev. of Dev. of Dev. of Test Test
Batch Part Obs 1 Obs 2 Obs 3 xj Rj Statistics Statistics
xi xi xi x R
1 A 0 1 2 1.00 2 1/2.67 = 0.375 2/2.67 = 0.75
2 A -1 0 1 0.00 2 0.00 2/2.67 = 0.75
-0.33/2.67
3 A -2 -1 2 -0.33 4 4/2.67 = 1.50
= -0.124
R = 2.67
4 B 0 2 1 0.67 2 0.67/2.2 = 0.305 2/2.2 = 0.909
5 B 0 2 -1 0.33 2 0.33/2.2 = 0.15 2/2.2 = 0.909
6 B 2 1 -2 0.33 4 0.33/2.2 = 0.15 4/2.2 = 1.818
7 B 0 -1 -2 -1.00 2 1.00/2.2 = -0.455 2/2.2 = 0.909
8 B -1 0 0 -0.33 1 -0.33/2.2 = -0.15 1/2,2 = 0.455
R = 2.2
The control charts are respectively shown in Fig. 10.7 and 10.8.
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1.5
0.5
Mean
LCL
0
CL
1 2 3 4 5 6 7 8
UCL
-0.5
-1
-1.5
Observation
Standardized R Chart
2.5
R
LCL
1.5
CL
UCL
1
0.5
0
1 2 3 4 5 6 7 8
Observation
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10 Quality Control
Process capability is simply the range that contains all possible values of a
specified quality characteristics generated by a process under a given set of
conditions. For a normal distribution with α = 0.0026, the range shall contain
99.74% of the values, which is equal to six standard deviation (σ). Thus, the
process capability is
The recent trend for the process capability is looking at eight standard
deviations, which is 99.9937% or 12 standard deviations, which is
99.9999998% of the values covering in the range.
Cp =
(USL − LSL ) (10.33)
6σ
where LSL is the lower specification limit and USL is the upper specification
limit. For the VLSI device process, it normally demands the process capability
ratio of more than 2, which means Cp ≥ 2.
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10 Quality Control
The portion of out of specification device produced is P[X < LSL] + P[X >
USL], which either equal to 2xP[X < LSL] or 2xP[X > USL]. If the mean µ of
the device produced is µ = (USL+LSL)/2, then the probability of defective
device is 2P z <
(LSL − µ ) =
2P z <
LSL − ( USL + LSL) / 2
or 2P z >
(USL − µ ) =
σ σ
σ
USL − ( USL + LSL) / 2
2P z > , where z = (X-µ)/σ that has standard normal
σ
distribution with mean equals to 0 and standard deviation equals to 1. After
substituting σ from equation (10.20), the portion of defective device is equal to
[ ] [
2P z < −3C p or 2P z > 3C p ] (10.34)
For the case whereby there only one specification limit, which is either LSL or
USL, the process capability ratio are respectively equal to
(µ − LSL)
Cp = for the larger the better characteristic (10.35)
3σ
( USL − µ)
Cp = for the smaller the better characteristic (10.36)
3σ
The portion of out of specification device produced is P[X < LSL] or P[X >
USL], which are also equal to P z <
(LSL − µ ) or
P z >
(USL − µ ) . After
σ
σ
substituting µ equation (10.35) and (10.36), the out of specification device
portions are respectively equal to
[ ]
P z < −3C p for the larger the better characteristic (10.37)
[ ]
P z > 3C p for the smaller the better characteristic (10.38)
For the process case whereby the process mean is not equal to µ = (USL-
LSL)/2, which shall mean that µ can either closed to LSL or USL, the portion of
the defective device produced is equal to
P z <
(LSL − µ ) + P z > (USL − µ ) (10.39)
σ σ
devices. The specification of the leakage test is ±30.0nA. The means obtained
from three testers are 20nA, 10nA, -15nA, while the standard deviations
obtained from three testers are 5.0nA, 6.0nA and 4.0nA respectively. Find the
portion of defective devices produced by the three testers. With known z-score,
use the standard normal cumulate probability table to obtain the cumulative
probability of reject.
The LSL is -30nA, while the USL is 30nA. The portion of defective device
produced by tester 1 is
P z <
(LSL − µ ) + P z > (USL − µ ) = P z < (− 30 − 20) + P z > (30 − 20) = P[z < -10]
σ σ 5 5
+ P[z > 2] = 1- 0.9772 = 0.0228.
Based on the example shown above, one can see that tester 3 is the most capable
tester. One can also see that the deviation of the mean from the nominal value
(in this case is 0nA) has greatly affect the portion of the defective device
produced by the testers. This effect is not capture by the process capability ratio
(Cp) because this ratio always assumes that the mean of the process is always
equal to (USL+LSL)/2. We shall discuss a different way that is to calculate the
process capability index Cpk to identify the effect.
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10 Quality Control
Based on the above example, this shall mean that the process capability
ratio Cp shall be taken from the value closer to either the LSL or USL divided
by a divisor, which should be 3σ instead of 6σ because it does not cover the
entire range of the specifications. Thus, the process capability index Cpk is
defined in equation (10.40) the device characteristics that have both LSL and
USL limits.
(µ − LSL ) (USL − µ )
C pk = Min , (10.40)
3σ 3σ
The process capability index Cpk for VLSI device process demands the index
value of at least 1.5. i.e. Cpk ≥ 1.5.
For the device characteristic that has either LSL or USL, the process
capability index Cpk is defined as
(µ − LSL)
Cpk = for the larger the better characteristic (10.41)
3σ
( USL − µ)
Cpk = for the smaller the better characteristic (10.42)
3σ
Let’s use the earlier example to calculate the process capability indices of the
(µ − LSL ) (USL − µ )
three tester s. The Cpk of tester 1 is C pk = Min , =
3σ 3σ
(USL − µ ) = (30 − 20 ) = 0.6666. The Cpk of tester 2 is
3σ 3x 5
(µ − LSL ) (USL − µ ) (USL − µ ) (30 − 10 )
C pk = Min , = = = 1.1111. The Cpk of tester 3
3σ 3σ 3σ 3x 6
is C pk = Min
(µ − LSL ) , (USL − µ ) = (µ − LSL ) = (30 − 10) = 1.6666. Based on the
3σ 3σ 3σ 3x 4
results, one can clearly see that tester 3 has a better process capability index
then two other two testers and tester 1 has the least process capability index.
These results concur with portion of defective device produced by the testers
using Cp method.
The portion of out of specification device produced is P[X < LSL] + P[X >
USL] = P z <
(LSL − µ ) + P z > (USL − µ ) . If the mean µ is closed to LSL then
σ σ
P z <
(LSL − µ ) > P z > (USL − µ ) and C = (µ − LSL) , this shall mean that
σ σ pk
3σ
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10 Quality Control
2P z <
(LSL − µ ) = 2P z < −3C
[ ] (10.43)
σ pk
2P z >
(USL − µ ) = 2P z > 3C
[ ] (10.44)
σ pk
The main limitation of the Cpk index is due to the normality assumption of the
characteristics. Also, for the nominal-the-better type of characteristics, the Cpk
index yields only an upper bound for the total proportion of defectives.
Taguchi process capability index Cpm takes into the consideration of loss due to
variation from the targeted value by replacing the standard deviation σ of the
process capability index Cp with the Taguchi’s loss function σ2 + (µ − X 0 )2 ,
where X0 is the targeted value. It is useful to identify processes that have same
Cpk. The Cpm index is calculated using equation (10.45).
Cpm =
(USL − LSL ) (10.45)
6 σ2 + (µ − X 0 )
2
Let’s use the example shown in Fig. 10.9 as the illustration. The targeted value
of the process is 1.00. The two processes have same Cpk values but different Cpm
indices theoretically saying that process B has a better process capability. In
practice, it may not be true since the variance of process B is higher means
expected more dissatisfaction from end user. The Cp values of process A and B
are respectively equal to 1.389 and 0.833, while the Cpk values are both equal to
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10 Quality Control
0.833. Although process A has lower standard deviation, its mean is further
away from target value. This resulted same Cpk value like the process B
whereby it has wider spread with mean closes to target value.
Figure 10.9: Processes with same Cpk but different Cpm indices
The calculated Cpm for the processes are 0.712 for process A and 0.833 for
process B.
Wrong estimation of mean and standard deviation was shown as one source of
error in measuring the process capability. Let’s take an example. 50
observations collected over a period of 60 minutes. These observations were
collected in 10 sample batches of size 5 each. The time interval between
successive batches was 10 minutes. The following estimates of the process
standard deviation were obtained.
It was pointed out that the estimate given by 0.000738 contains the variation
within each sample batch of size 10 (short-term variability) only, whereas the
estimate of 0.001329 contains the variation within the batches as well as the
long-term variation in the process over a period of 60 minutes. Assuming that
the process was not stopped and adjusted during the interval of 60 i.e. the
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10 Quality Control
process control technique used to monitor the process allowed the observed
deviation in the mean. The true estimate of the total variability in the
characteristic is 0.001329. Usually the estimate of the variation within each
batch size of 10 is used in calculating of Cp and Cpk indices. As this estimate is
smaller than the estimate of the total variation including the long-term
variability, these indices over estimate the process capability and hence under
estimate the proportion of defectives. In order to address this problem, the Ppk
index was introduced.
The Ppk index is calculated using the same formulae for calculating the Cpk
index. For nominal-the-better type of formula is
(µ − LSL ) (USL − µ )
Ppk = Min , (10.46)
3σ 3σ
For the device characteristic that has either LSL or USL, the process capability
index Cpk is defined as
(µ − LSL)
Ppk = for the larger the better characteristic (10.47)
3σ
( USL − µ)
Ppk = for the smaller the better characteristic (10.48)
3σ
2P z <
(LSL − µ ) = 2P z > (USL − µ )
σ σ
[ ] [
= 2P z < −3Ppk = 2P z > 3Ppk ] (10.49)
[ ] [
2P z < −3Ppk or 2P z > 3Ppk ] (10.50)
For smaller the better and larger the better types characteristics. As in the case
of the Cpk index, the distribution of the characteristic must be normal in order
for equation (10.49) and (10.50) to be valid.
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10 Quality Control
Let’s take an example to calculate the Ppk index for the data that has USL
0.995, USL 1.005, batch average standard deviation 0.000738, long-term
standard deviation 0.001329, batch average mean 1.001, long-term batch mean
1.0005 and estimate the proportion of defectives using the Ppk index.
The portion of reject using Ppk is 2P[z > 3Ppk ] = 2P[z > 3x1.128] = 2x[1-0.9996]
= 0.0008 = 800ppm.
The portion of reject using Cpk is 2P[z > 3C pk ] = 2P[z > 3x1.86] = 2x1.21x10-8 =
2.42x10-8 = 0.0008 = 0.0242ppm.
From the results, one can see that Ppk gives a more realistic result than Cpk.
The limitations of the Ppk index are the same as those of the Cpk index
discussed earlier. In short, these are the normality assumption required for the
expressions to be valid, the upper bound on the proportion of defectives, and the
masking of the deviation of the mean from the target value by the standard
deviation.
10.4 Reliability
Reliability is a study of probability that a component such as integrated circuit,
equipment, or system will satisfactorily perform the intended function under
given circumstances, such as environmental conditions, limitations as to
operating time, and frequency, and thoroughness of maintenance, for a specified
period of time. Thus, an integrated circuit designed for the operation in the
space for a period of 15 years and if this integrated circuit can live up with the
intended period then one can say that this integrated circuit is reliable.
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In this topic, student will learn the definition of failure rate, the statistical
distribution models used to calculate the reliability function, the failure rate, and
the cumulative fail function of the device/system. The student will also learn the
failure rate for the lifetime of the device and the accelerated test methods used
to wipe-out unreliable device earlier instead of waiting for a long time before
failure is shown up under normal operation conditions.
1 Failure
λ< (10.51)
No of transistor x period of operation
If a system contains 100,000 transistors then the failure rate (λ) from one month
1 Failure 1 Failure
operation is equal to λ < = ,
No of transistor x period of operation 1.0x105 x 720 hrs
which is equal to 14x10-9 Failure/Device-hour. If the unit of failure is defined to
be 1 Failure Unit = 1 FIT = 1 Failure/109 Device-hour then the example shown
has failure rate λ<14 FIT.
If one now considers a system that has 225 integrated circuits and the
failure rate of integrated circuit is 100 FIT. One can calculate the mean time to a
1 Failure
failure using equation (10.51). Thus, Period of operation <
No of transistor x λ
1 Failure
= -9
= 4.44x104hrs, which is equal to 5.13 years. The percentage of
225 x 100x10
failure per month shall be 100x10-9x225x720x100% = 1.62%.
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10 Quality Control
Based on the above discussed example, one would see that it is time consuming
before a failure is shown out. We cannot be waiting for 5.13 years to see a
failure is shown out to calculate the failure rate of a system. One ought to have a
developed method by sample testing to predict the failure rate of the system. In
this section, it discusses the methods to quantitatively measure and predict
device failure rate, and to identify and eliminate the failure mechanism.
F(t) = 0 t <0
0≤ F(t) ≤ F(t’) 0 ≤ t ≤ t’ (10.52)
F(t) →1 t →∞
The reliability function R(t) is a probability that the device will survive to time t
without failure. Thus, the reliability function R(t) is related to fail function by
equation (10.52).
The derivative of fail function F(t) with respect to time is known as the
probability density function (pdf) and is represented by f(t). Thus, the pdf is
related to the cdf by
d
f (t) = F( t ) (10.53)
dt
and
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10 Quality Control
d
f (t) = − R (t) (10.56)
dt
In most applications, the most concern is the hazard rate, which is referring to
instantaneous failure rate. Thus, the term failure rate is always referred as
instantaneous failure rate not average failure rate.
The fraction of devices that are good at time t and that fails by time t+∆t
is given by
1 R ( t ) − R ( t + ∆t )
Average failure rate = (10.58)
∆ R (t)
In the limit as ∆ approaches zero, this becomes the instantaneous failure rate
λ(t), which is given by
1 dR ( t )
λ( t ) = − (1059)
R ( t ) dt
t
R ( t ) = exp − ∫ λ( x )dt (10.61)
0
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10 Quality Control
MTTF is the device’s average age at failure for a population whose reliability
function is R(t) with probability density function f(t).
It is desired to have a distribution that represents the failure rate of device over
its entire life. The failure of rate of an integrated circuit generally varies as a
function of time following the manner shown in Fig10.10.
Figure 10.10: Failure rate versus time for a typical integrated circuit
During the early life of the device, the failure rate is high but it decreases as
time passed. The failure during this period is called infant mortality failure. The
causes of the early failure are generally fabrication and assembly related defects
such as wire problem, micro-crack, over etch, photoresist residue,
contamination, electrostatic defect etc. The defects can be wiped out by
accelerated life test and followed by a final test to segregate them.
The steady useful life period, the failure rate is normally low and the rate of
failure is also fairly constant. Device failure in this period is a result of a large
number of fabrication and assembly unrelated causes such as mishandling,
applying wrong stimulant etc. The wear out period is the old age period,
whereby the device has reached the end of its life.
The simplest distribution for the failure rate is the exponential function,
which is characterized by a constant failure rate over the entire life time of the
device. This is the function of the steady useful life period, whereby all early
infant mortality failure and wear out mechanism have been eliminated. Thus,
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10 Quality Control
the steady useful life failure rate function is λ(t) = λ0 = constant. From equation
(10.61), the reliability function R(t) is equal to R ( t ) = e − λ t . The cumulative
0
∞
1
MTTF = ∫ tλ 0 e −λ0 t dt = .
0
λ0
Let’s look at another failure rate function, which is the Weibull distribution
function. The Weilbull states the failure rate varies as power of the age of the
device. The failure rate is represented by
β β−1
λ( t ) = t (10.63)
α
1 1 ln t − µ 2
f (t) = exp − (10.64)
σt 2π 2 σ
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10 Quality Control
1 1 t 2
= exp − ln (10.65)
σt 2π 2 t 50
where the median time to failure t50, which is the time when 50% of the devices
have failed is given by
t50 = eµ (10.66)
1
t
dx 1 ln t − µ 2
σt 2π ∫0 x
F( t ) = exp − (2.26)
2 σ
f (t)
λ( t ) = (10.67)
1 − F( t )
There are six common stress tests used to accelerate device failure. They
are temperature, voltage, current, humidity, temperature cycling, and burn-in.
Temperature cycle is used to accelerate mechanical failure of die and assembled
package. This process is normally required for high reliable device such as the
military graded device. The progress is done before gross and fine leak test in
assembly process steps.
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10 Quality Control
The temperature cycle determines the ability of parts to resist extremely low and
extremely high temperature, as well as its ability to withstand cyclical exposure
to these temperature extreme. The devices are subjected to two extreme
temperatures normally between -650C and 1750C for minimum of 10 cycles.
Each cycle takes approximately 21 minutes. The dwell time in each temperature
is 10 minutes and the transfer time of the device between two temperature
chambers is 1 minute. Another failure can be sorted out by fine/gross leakage
test and test operation.
Many of the mechanism are due to chemical or physical processes that can be
accelerated by temperature. The reaction rate (R) at which these processes
proceed is governed, in most of the time, by Arrhenius equation.
R = R0exp(-Ea/kT) (10.68)
t1 R 2 E 1 1
= = exp a − (10.69)
t 2 R1 k T1 T2
where temperature T1>T2 and time t1< t2. The ratio time to failure t1/t2 is also
termed as acceleration factor.
10.4.4.3 Voltage and Current Acceleration
Voltage and current are effective accelerating stresses for many of the common
failure mechanisms observed in integrated circuit. Voltage causes acceleration
of failure caused by dielectric breakdown, interface charge accumulation,
charge injection, and corrosion.
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10 Quality Control
Most studies indicate that the reaction rate of the failure mechanism is
proportional to the power of the applied voltage. The power is usually a
function temperature, which is
R (T , V ) = R 0 ( T ) V γ ( T ) (10.70)
R (T , V ) = R 0 (T ) J γ ( T ) (10.71)
For high reliable product, the leads of package especially the solder dipped
and tin plated leads are subject to high humidity salt atmosphere condition for
some time to check the corrosion level of the leads.
10.4.4.5 Burn-In
Burn-in is a process used basically to wipe out infant mortality failure of the
device so that the remaining devices can live from its steady useful life state to
wear out end of life state. As already mentioned earlier, the causes of the early
failure are generally fabrication and assembly related defects, through burn-in,
time to failure due to these defects would usually show up in less than 168
hours.
Exercises
10.1. What is the purpose of in-process quality control monitoring?
10.3. The data in the table are obtained from an operation in fabrication. Derive
the values of SPC control lines for xi and R charts.
10.4. Plot a SPC X chart and R chart of the control lines established in question
10.3.
10.5. The data in the table shown below are the current drain of eight integrated
circuits measured by a piece of equipment in test operation. The
specification limit of current drain is 10mA. Calculate the process
capability index of this equipment and defective part per million
produced by this equipment.
Observation Observation xi
1 9.0
2 9.2
3 9.9
4 9.0
5 9.5
6 9.8
7 8.9
8 9.8
Mean x = 9.39
Standard Deviation s = 0.41
10.6. A particular system contains 200,000 transistors has failure rate 75 FIT,
calculate the repair cost per month if each field engineer visit causes the
company RM2,000.
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10 Quality Control
10.7. Calculate the mean time between failures of the system that has data
stated in question 10.6.
10.8. State how acceleration test method can be used to accelerate physical and
chemical processes failure in shorten time.
10.9. State two acceleration stress tests that used to accelerate failure due to
processes.
10.10. The VDD voltage for the voltage acceleration stress test for a device is set
at 7.0V instead of its normal operating voltage of 4.5V. If the time to fail
at normal operation voltage is 15 years, calculate the time to fail for the
device if voltage acceleration stress test is applied. You may use γ = 4 for
your calculation.
Bibliography
1. M Jeya Chandra, “Statistical Quality Control”, CRC Press LLC, 2001.
2. S.M. Sze, “VLSI Technology”, New York, McGraw Hill, 2002.
3. Jan M. Rabaey, Anantha Chandrakasan and Borivoje Nikolic “Digital
Integrated Circuit – A Design Perspective”, 2nd edition, Prentice Hall,
2003.
4. C.Y. Chang and S.M. Sze, “ULSI Technology”, New York, McGraw Hill,
1996.
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Appendix A
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Appendix B
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P
A
Ppk index .................................................. 19
Alternative hypothesis ..............................3
Arrhenius equation ..................................28 Pre-control chart ....................................... 9
Probability density function.................... 23
B Process capability ................................... 14
Burn-in ....................................................30 Process capability index ............. 14, 16, 18
Process capability ratio ........................... 14
C
Q
Center line .................................................3
Cumulative distribution function ............23 Quality control .......................................... 1
D R
Distribution function of failure rate ........25 R chart ....................................................... 8
D-NOM Charts........................................10 Reaction rate ........................................... 29
Reliability ............................................... 21
E Reliability function ................................. 24
Electrostatic defect ..................................25 S
F Statistical process control chart ................ 2
Failure rate ..............................................22 T
Failure Unit .............................................22
Taguchi process capability index............ 18
H Temperature cycle .................................. 28
Hermetic package......................................2 U
Humidity-temperature acceleration ........29
Upper control limit ................................... 3
L Upper specification limit ........................ 14
Lower control limit line ............................3 V
Lower specification limit ........................14
Voltage and current acceleration ............ 28
M
W
Mean time to failure ................................24
Weibull distribution ................................ 26
N
X
Null hypothesis .........................................3
X chart ...................................................... 8
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