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Quantum Cellular Automata Based Efficient BCD Adder Structure

N. A. Shah1, F. A. Khanday1* and Z. A. Bangi1
1

Department of Electronics and Instrumentation Technology University of Kashmir, Srinagar-190006, India * farooqsnn20@yahoo.co.in

Abstract-In this paper, design of quantum-dot cellular automata (QCA) based Binary Coded Decimal (BCD) adder is presented. The design is based on pipelined structure with noise problems circumvented by careful clocking organization. The design occupies smaller area and enjoys superior performance in respect of noise, circuit stability and power consumption compared to the previously reported design. The QCA circuit is simulated and its operation is analyzed using QCA Designer bistable vector simulation. Keywords-Nanotechnology; Nanoelectronics; Quantum-dot Cellular Automata; Circuit Design; Circuit Simulation; Arithmetic Computing

conversion of binary to decimal (for numbers having many digits). Therefore, often when a number is being held in a digital circuit, before it is to be displayed in decimal form, binary coded decimal (BCD) rather than straight binary code is used. BCD encodes each decimal digit with its binary equivalent using four bit strings. So, decimal digits are simply represented in four bits by their direct binary values. A disadvantage of BCD is its inefficiency of using only first 10 of the possible 16 codes that four bits can produce. Nevertheless, the advantages usually outweigh this disadvantage and so it is regularly used. The next immediate problem that is being experienced in BCD addition is the use of only first 10 codes, contrary to straight binary addition where all the 16 states are used. The problem in the conventional digital design is overcome by adding logic circuitry and thus giving it a special name of BCD adder. The QCA based BCD adder design presented in this paper occupies less space in comparison with reported in [26]. The operational stability of the design has been given particular importance by restricting the minimum wire to wire distance to 2 cells in almost entire area of the design and the maximum wire length in a clocking zone to 13 cells. Both these measures reduce the probability for a kink to occur. II. QCA BCD ADDER Our main objective is to develop an efficient design of QCA based BCD adder. A high-level block diagram of the BCD adder design is shown in Fig. 1, where Ai and Bi (i = 0-3) are the BCD inputs, and Si (i = 0-3) and Cout are respectively BCD sum and final carry. The design includes two AND blocks, six full binary adder blocks, and one each of an OR Block and an XOR block.

I. INTRODUCTION Quantum Cellular Automata (QCA) originally proposed by Lent et al. [1, 2] are a nanoelectronic digital logic architectures in which information is stored as configurations of electron pairs in quantum-dot arrays. QCA use arrays of coupled quantum dots [3] to build Boolean logic functions and to perform useful computations. QCA take advantage of quantum-mechanical effects to significantly reduce the size of digital circuits and operate at high speeds at very low power levels. Conventional digital technologies use ranges of voltage or current to represent binary values. In contrast, QCA use the position of electrons in quantum dots to represent binary values 0 and 1. QCAs primary advantages are the exceptionally high logic integration derived from the small size of dots, the simplicity and the notably low power-delay product [4]. The basic QCA cell consists of four quantum dots in a square array coupled by tunnel barriers. The physical mechanism for interaction between dots is the Coulomb interaction and the quantum-mechanical tunneling. Electrons are able to tunnel between the dots, but they cannot leave the cell. If two mobile electrons are placed in the cell, in the ground state and in the absence of external electrostatic influence, Coulomb repulsion will force the electrons to dots on the opposite corners [5-7]. It is possible to implement all combinational and sequential logic functions by properly arranging cells so that the polarization of one cell sets the polarization of a nearby cell [8]. According to previous studies, several logic gates and computing devices [9] are implemented with QCA. Basic implementations that have been proposed are the binary wire [2], the majority gate, AND gate [10], OR gate [10], NOT gate [10], XOR gate [10], bit-serial adder [11, 12], full adder [13, 10, 11, 14, 15], multiplier [16], multiplexer [13, 17], flipflop [1820], serial memory [21, 22], parallel memory [23], Arithmetic Logic Unit [13, 24], microprocessor [24], Programmable Logic Array (PLA) [25], etc. A problem encountered in binary arithmetic is that quite complex digital circuit is required to accomplish direct

Fig. 1 High-level Block Diagram of the BCD Adder Design

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Fig. 2 shows the QCA implementation of the AND, OR, XOR and full binary adder blocks. The XOR and full binary adder blocks require Inverter gate given in Fig. 2(e). Both AND and OR blocks are usually based on a three-input majority voter (MV) gate, settling into minimum energy between the input and output cells. The gate performs the two-input AND-operation when its third input is set at logical zero or the two-input OR-operation when its third input is fixed at logical one. The XOR gate basically consists of two AND gate and a single OR gate with one input of the each AND gate is inverted ( XOR A B AB ). The full binary adder block given in Fig. 2(d) is based on Fig. 3 expressed in terms of MVs and inverters. The final QCA implementation layout of the proposed BCD adder is depicted in Figure 4. It can be easily seen that the clocking phases are traversed in the proper order (0, 1, 2, 3, 0, 1 . . .) so that the required clock phases are always adjacent to one another to allow correct signal propagation. The signal propagates diagonally with a line profile from the top left block to the bottom right block. Also using pipelining structure, the proper signals arrive simultaneously at the inputs of the blocks. The circuit was designed and simulated using QCADesigner tool. In the environment of the previously mentioned tool, the overall QCA cell dimensions are defined to be 1818nm; the dot diameter is defined to be 5 nm and the inter-cell distance to be 2 nm. According to the QCADesigner tool, the design consists of 1903 cells covering an area of 29381870nm2, that is, approximately 5.5m2 and the ratio of the area covered by QCA cells to the overall area of the layout is (0.61m2/5.5m2) 1/9. The simulation results of the design, acquired by the QCADesigner bistable vector simulation engine, are given in Fig. 5. There are some design concerns taken into account to increase the robustness of the QCA circuit [27]. The length of the wire within a given clocking zone is kept minimum to increase the probability that a QCA cell will switch successfully which decreases in proportion to the distance of this particular cell from a clamped (frozen) input at the beginning of the wire. Additionally, short wire lengths result in circuit operation with higher clock rates. Thus, the maximum wire length in the proposed design equals 13 cells. Further, minimum wire length decreases the probability for a kink to occur (a QCA cell to align differently from its expected polarization) at higher temperatures. The area of the clocking zones is kept minimum to increase uniformity and consequently manufacturability. Furthermore, by keeping the area to a minimum, wire lengths are also kept to a minimum and consequently the circuit can operate at higher temperatures with no kink occurrence. Another problem associated with complex QCA designs is that usually large amount of white space wasted area is left between cells [4, 30]. In the presented design the use of clocking zones with many cells is avoided and consequently the QCA cells are uniformly distributed into the clocking zones. The clocking zones are also designed in such a way that the uncovered areas can be as small as possible. Finally, to overcome this problem, the total area covered by QCA cells was minimized by keeping the distance between binary wires as close as possible according to QCA design rules proposed by Kim et al. [28, 29]. As a result, the proposed architecture does not leave a large amount of unused area.

(a)

(b)

(c)

(d)

(e) Fig. 2 Elementary Block Implementation for the BCD Adder Design (a) AND Block (b) OR Block (c) XOR Block (d) Binary Full Adder and (e) Inverter.

Fig. 3 Binary Full Adder Circuit Diagram by MV and Inverter Gates

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A comparison of proposed design with previously reported [26] is given in Table I. A study of this table shows that the new design uses significantly lesser area. Besides, it has a delay of 9 clock phases compared with 11 clock phases delay of the previous design. Further, the design has significantly smaller maximum wire length which leads to a higher maximum temperature for kink-free operation.
TABLE I COMPARISON OF THE PROPOSED DESIGN IN THIS PAPER WITH [26]

Characteristics No. of cells Estimated area by QCADesigner tool (m2) Computational time Maximum wire length in a zone (cells)

Reported design [26] ~ 3193 9.00 11 More than 30

Proposed design 1903 Fig. 5 Simulation Results of the BCD Adder 5.50 9 13 [1] REFERENCES C. S. Lent, P. D. Tougaw, W. Porod and G. H. Bernstein, Quantum cellular automata, Nanotechnology, vol. 4, pp. 4957, 1993. [2] C. S. Lent and P. D. Tougaw, Lines of interacting quantum-dot-cells: a binary wire, Journal of Applied Physics, vol. 74, pp. 62276233, 1993. [3] Amlani, A. O. Orlov, R. K. Kummamuru, G. H. Bernstein, C. S. Lent and G. L. Snider, Experimental demonstration of a leadless quantumdot cellular automata cell, Applied Physics Letters, vol. 77, pp. 738 740, 2000. [4] Amlani, A. O. Orlov, G. H. Bernstein, C. S. Lent and G. L. Snider, Realization of a functional cell for quantum-dot cellular automata, Science, vol. 227, pp. 928930, 1997. [5] C. S. Lent, P. D. Tougaw and W. Porod, Quantum cellular automata: the physics of computing and arrays of quantum dot molecules, Proceedings of the Workshop on Physics and Computing, IEEE Computer Society Press: Dallas, TX, pp. 513, 1994. [6] B. Meurer, D. Heitmann and K. Ploog, Excitation of three dimensional quantum dots, Physical Review B, 48, pp. 1148811491, 1993. [7] Amlani, A. O. Orlov, G. Toth, G. H. Bernstein, C. S. Lent and G. L. Snider, Digital logic gate using quantum-dot cellular automata, Science, vol. 284, pp. 289291, 1999. [1] C. S. Lent and P. D. Tougaw, Device architecture for computing with quantum dots, Proceedings of the IEEE, vol. 85, pp. pp. 541557, 1997. [2] T. Lantz and E. Peskin, A QCA implementation of a configurable logic block for an FPGA, IEEE International Conference on Reconfigurable Computing and FPGAs, San Luis Potosi, Mexico, pp. 110, 2006. [3] P. D. Tougaw and C. S. Lent, Logical devices implemented using quantum cellular automata, Journal of Applied Physics, vol. 75, pp. 18181825, 1994. [4] I. Hnninen and J. Takala, Binary Adders on Quantum-Dot Cellular Automata, Journal Signal Processing Systems, vol. 58, pp. 87103, 2010. [5] A. Fijany, N. Toomarian, K. Modarress and M. Spotnitz, Bit-serial adder based on quantum dots, NASA Technical Report, 2003. [6] A. Gin, S. Williams, H. Meng and P. D. Tougaw, Hierarchical design of quantum-dot cellular automata devices, Applied Physics, vol. 5, pp. 37133720, 1999. [7] K. Kim, K. Wu and R. Karri, The robust QCA adder designs using composable QCA building blocks, IEEE Transactions on Computeraided Design of Integrated Circuits and Systems1, vol. 26, pp. 176 183, 2007. [8] My. Choi and Mi. Choi, Scalability of globally asynchronous QCA (quantum-dot cellular automata) adder design, Journal of Electronic Testing, vol. 24, pp. 313320, 2008. [9] I. Hanninen and J.,Taka, Arithmetic design on quantum-dot cellular automata nanotechnology, Workshop on Embedded Computer Systems Architectures, Modeling, and Simulation SAMOS, Samos, Greece, pp. 4352, 2008. [10] V. Vankamamidi, M. Ottavi and F. Lombardi, Two-dimensional schemes for clocking/timing of QCA circuits, IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, vol. 27, pp. 3444, 2008.

III. CONCLUSION We presented the design and simulation of a QCA BCD adder circuit and analyzed its operation. The design consists of less number of cells than the earlier design. The design utilizes lesser number of clock phases and has significantly smaller maximum wire length which leads to kink-free operation at higher operating temperature. Further, to increase the robustness of the QCA design, various design concerns have been addressed.

Fig. 4 QCA Implementation of the BCD Adder

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[11] J. Huang, M. Momenzadeh and F. Lombardi, Analysis of missing and additional cell defects in sequential quantum-dot cellular automata, Integration, the VLSI Journal, vol. 40, pp. 503515, 2007. M. Momenzadeh, J. Huang and F. Lombardi, Defect characterization and tolerance of QCA sequential devices and circuits, IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Monterey, California, U.S.A., pp. 199207, 2005. J. Huang, M. Momenzadeh and F. Lombardi, Design of sequential circuits by quantum-dot cellular automata, Microelectronics Journal, vol. 38, pp. 525537, 2007. V. Vankamamidi, M. Ottavi and F. Lombardi, Tile-based design of a serial memory in QCA, Proceedings of the 15th ACM Great Lakes Symposium on VLSI, Chicago, Illinois, U.S.A., pp. 201206, 2005. V. Vankamamidi, M. Ottavi, F. Lombardi, A serial memory by quantum-dot cellular automata (QCA), IEEE Transactions on Computers, vol. 57, pp. 606618, 2008. V. Vankamamidi, M. Ottavi and F. Lombardi, A line-based parallel memory for QCA implementation, IEEE Transactions on Nanotechnology, vol. 4, pp. 690698, 2005. M. T. Niemier, M. J. Kontz and P. M. Kogge, A design of and design tools for a novel quantum dot based microprocessor, Proceedings of the 37th Design Automation Conference, Los Angeles, California, U.S.A., pp. 227232, 2000. [18]

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