DESIGN OF SINGLE PHASE H-BRIDGE MULTILEVEL INVERTER USING MICROCONTROLLER ATMEL 89C51

A Project report submitted in partial fulfillment of the requirements for the Award of Degree of BACHELOR OF TECHNOLOGY IN ELECTRICAL AND ELECTRONICS ENGINEERING By CH. ASHLESHA (08241A0203) A.MOUNIKA B.APARNA N.SHARADA (08241A0224) (09245A0201) (09245A0205)

Under the Esteemed Guidance of Mr. P.PRAVEEN KUMAR Assistant Professor

Department of Electrical and Electronics Engineering GOKARAJU RANGARAJU INSTITUTE OF ENGINEERING & TECHNOLOGY, BACHUPALLY, HYDERABAD-72 2008 2012

GOKARAJU RANGARAJU INSTITUTE OF ENGINEERING & TECHNOLOGY BACHUPALLY, HYDERABAD-72 2008 2012

CERTIFICATE
This is to certify that the project report entitled DESIGN OF SINGLE PHASE H-BRIDGE MULTILEVEL INVERTER USING MICRO CONTROLLER ATMEL 89C51 that is being submitted by CH.ASHLESHA, ROLL.NO.08241A0203 A.MOUNIKA, B.APARNA, ROLL.NO.08241A0224, ROLL.NO.09245A0201,

N.SHARADA, ROLL.NO.09245A0205, in partial fulfillment for the award of the Degree of Bachelor of technology in Electrical and Electronics Engineering to the Jawaharlal Nehru Technological University is a record of bonafide work carried out by them under my guidance and supervision. The results embodied in this project report have not been submitted to any another University or Institute for the award of any Degree or Diploma. External Guide HOD, EEE GRIET, Hyderabad. Internal Guide MR.P.PRAVEEN KUMAR Assist. Professor GRIET, HYDERABAD

ACKNOWLEDGEMENT
This is to place on record our appreciation and deep gratitude to the persons without whose support this project would never seen the light of the day. We express our propound sense of gratitude to Mr. P.S. RAJU, Director, GRIET. For his guidance, encouragement, and for all facilities to complete this project. We also express my sincere thanks to Mr. P.M. SARMA, Head of the Department, Electrical and Electronics Engineering G.R.I.E.T for extending his help. We have immense pleasure in expressing thanks and deep sense of gratitude to my guide Mr. P.PRAVEEN KUMAR, Assist. Professor of Electrical and Electronic Engineering, G.R.I.E.T for his valuable suggestion and guidance throughout this project. Finally at the outset we would like to thank all those who have directly or indirectly helped us accomplish our project successfully. CH.ASHLESHA A.MOUNIKA B.APARNA N.SHARADA

ABSTRACT

The power electronics device which converts DC power to AC power at required output voltage and frequency level is known as inverter. The voltage source inverters produce an output voltage or a current with levels either 0 or +ve or-ve V dc. They are known as two-level inverters. Multilevel inverter is to synthesize a near sinusoidal voltage from several levels of dc voltages. Multilevel inverter has advantage like minimum harmonic distortion. Multi-level inverters are emerging as the new breed of power converter options for high power applications. They typically synthesize the stair case voltage waveform (from several dc sources) which has reduced harmonic content. In this project work hardware model of Three-level single phase cascade HBridge inverter has been developed using MOSFETS. Gating signals for these MOSFETS have been generated by designing comparators. In order to maintain the different voltage levels at appropriate intervals, the conduction time intervals of MOSFETS have been maintained by controlling the pulse width of gating pulses ( by varying the reference signals magnitude of the comparator ). The results of hardware are compared with simulation results. Simulation models (designed in SIMULINK) have been developed up to five levels and THD in all the cases have been identified.

CONTENTS

Chapter 1

INTRODUCTION 1.1 Outline of the thesis

Chapter 2

MULTI-LEVEL INVERTERS TOPOLOGIES 2.1 Introduction 2.2 Types of Multi-level Inverters 2.3 Applications 2.4 Conclusions

Chapter 3

SIMULATION OF MULTI -LEVEL INVERTERS 3.1 Introduction 3.2 Single phase H-bridge Inverters 3.3 Comparison with conventional systems

Chapter 4

HARDWARE COMPONENTS 4.1 Introduction 4.2 Description of components 4.2.1 Power MOSFETS 4.2.2 NOT gate 4.2.3 Comparator

Chapter 5

HARDWARE IMPLEMENTATION 5.1 Single H-Bridge 5.2 Cascade H-Bridge 5.2.1 Positive cycle 5.2.2 Negative cycle 5.2.3 Complete waveform

Chapter 6

CONCLUSIONS Future Scope of the Project REFERENCES APPENDIX

CHAPTER 1 INTRODUCTION

In high power systems, the multilevel inverters can appropriately replace the existing system that uses traditional multi-pulse converters without the need of the transformers . All the three multi-level inverter topologies can be used in reactive power compensation without having the voltage unbalance problem. With the help of a transformer having one primary winding and several secondary windings, the cascade Hbridge configuration can be used in back-to-back intertie application. Also the structure of separate dc sources is well suited for various renewable energy sources such as fuel cell , photovoltaic , biomass etc. This structure is therefore well suited for an ac power supply in vehicle system utilities. The key features of a multi-level structure are as follows Harmonic content decreases as the number of levels increases thus Reducing the filtering requirements. Here switching losses can be avoided. (because of the absence of PWM techniques) Without an increase in the rating of an individual device, the output Voltage and power can be increased. The switching disservices do not encounter any voltage sharing problems. For this reason, multi-level inverters can easily be applied for high power applications such as large motor drivers and utility supplies. They have higher efficiency because the devices can be switched at Low frequency. Because of the key feature, they have become indispensable in high power and high voltage applications.

1.1

Outline of the thesis:

Here a complete survey of the multi-level inverters is described. In chapter 2, the various topologies available are presented. Simulation of the cascade type inverter is done up to 5 level and the results of are shown in chapter 3 . A detailed description of the components used in hardware implementation is done in chapter 4 . In chapter 5 , hardware implementation of single phase H-Bridge , cascade Hbridge inverter is described.

CHAPTER 2 MULTI-LEVEL INVERTERS TOPOLOGIES 2.1 Introduction

The voltage source inverters produce a voltage or a current with levels either 0 or V dc they are known as two level inverters. To obtain a quality output voltage or a current waveform with a minimum amount of ripple content, they require high switching frequency along with various pulse width modulation (PWM) strategies. In high power and high voltage applications, these two level inverters, however, have some limitations in operating at high frequency mainly due to switching devices should be used in such a manner as to avoid problems associated with their series- parallel combinations that are necessary to obtain capability of handling high voltages and currents. It may be easier to produce a high power, high voltage inverter with the multilevel structure because of the way in which device voltage stresses are controlled in the structure. Increasing the number of voltage levels in the inverters without requiring higher ratings on the individual devices can increase the power rating. The unique structure of Multi-level voltages sources inverters allow them to reach high voltages with low harmonics without the use of transformer or series connected synchronized switching devices. As the number of voltage levels increases , the harmonic content of output voltage waveform decreases significantly.

2.2 Types of Multi-level Inverters

The general structure of multi-level converter is to synthesize a near sinusoidal voltage from several levels of dc voltages, typically from capacitor voltage sources. As number of levels increases, the synthesized output waveform has more steps, which provides a staircase wave that approaches a desired waveform . Also, as steps are added to waveform, the harmonic distortion of the output wave decreases, approaching zero as the number of voltage levels increases. The Multi-level inverters can be classified into three types. Diode clamped Multi-level inverter Flying capacitor Multi-level inverter Cascade Multi-level inverter

2.2.1 Diode- clamped Multi level inverter

A diode clamped (m-level) inverter (DCMLI) typically consists of (m-1) capacitor on the dc bus and produces m levels on the phase voltages. Figure shows full bridge fivelevel diode clamped converter. The numbering order of the switches is Sa1, Sa2, Sa3, Sa4,

Sa1, Sa2, Sa3, Sa4. The dc bus voltage consists of four capacitors C1, C2, C3, and C4. For a dc voltage Vdc, the voltage across each capacitor is V dc/4, and each devices voltage stress is limited to one capacitor voltage level V dc/4 through clamping diodes. An m-level inverter leg requires (m-1) capacitors, 2(m-1) switching devices and (m-1) X(m-1) clamping diodes.

2.2.1(a) Principle of operation

To produce a stair case output, let us consider only one leg of five level inverter, as shown in Figure 2.1. A single phase bridge with one leg is shown in figure 2.1 The steps to synthesize the five level voltages are as follows a) b) c) d) e) Voltage level Van= V dc; turn on all upper switches S1, S2 , S3 and S4. Voltage level Van= V dc/2, turn on the switches S2, S3, S4 and S1. Voltage level Van= 0, turn on the switches S3, S4, S1 and S2. Voltage level Van= - V dc/2 turn on the switches S4, S1, S2, S3. Voltage level Van= - V dc; turn on all lower switches S1, S2 ,S3 and S4.

Fig 2.1 Single phase Diode clamped inverter

2.2.1(b)Advantages:
a) b) When the number of levels is high enough , the harmonic content is Low enough to avoid the filters. Inverter efficiency is high because all devices are switching at the Fundamental frequency.

c) The control method is simple.

2.2.1(c)Disadvantages:
a) b) Excessive clamping diodes are required when the number of levels is high. It is difficult to control the real power flow of the individual Converter in multi-level converter system.

2.2.2 Flying capacitor multilevel inverter: 2.2.2(a) Single phase flying capacitor inverter:
The figure 2.2 shows a single phase full bridge 5-level inverter based on flying capacitors. Each phase like has an identical structure. Assuming that each capacitor has the same voltage rating, the series connection of the capacitors indicates the voltage level between calming points. All phase legs share the DC link capacitors C1 to C4.

2.2.2(b) Principle of operation:

To produce a staircase output voltage, the switching instants of MOSFETS will be shown below. 1) 2) Voltage level Van = Vdc/2, turn on all upper switches S1 - S4 . Voltage level Van = Vdc/4, there are three combinations. a) Turn on switches S1, S2, S3 and S1. (Van = Vdc/2 of upper C4s - Vdc/4 of C1s). b) Turn on switches S2, S3, S4 and S4. (Van = 3Vdc/4 of upper C3s - Vdc/2 of C4s). c) Turn on switches S1, S3, S4 and S3. (Van= Vdc/2 of upper C4s 3Vdc/4 or C3s + Vdc/2 of upper C2). Voltage level Van= 0, turn on upper switches S3, S4, and lower switch S1, S2. Voltage level Van= -Vdc/4, turn on upper switch S1 and lower switches S1, S2 and S3.

3)

4)

5) Voltage level Van= -Vdc/2, turn on all lower switches S1, S2, S3 and S4.

Fig 2.2

single phase flying capacitor inverter

2.2.2(c) Advantages:
a) Large amount of storage capacitors can provide capabilities during Power outages. b) These inverters provide switch combination redundancy for Balancing different voltage levels. c) With the number of voltages levels increased, the harmonic content is low enough to avoid the filters. d) Both real and reactive power flow can be controlled.

2.2.2(d) Disadvantages:
a) An excessive number of storage capacitors are required when the Number of levels is high. High-level inverters are more difficult to Package with the bulky power capacitors and expensive too. b) The inverter control can be very complicated and switching Frequency and switching losses are high for real power Transmission.

2.2.3 Cascaded Multi-level inverter:

A relatively new converter structure called Cascaded Multi-level inverter, can avoid extra clamping diodes or voltage balancing capacitors. The converter topology used here is based on the series connection of single phase inverters with separate DC sources.

2.2.3(a) The different topologies by with H-bridge are designed are:

Cascade H-bridge Hybrid H-bridge

2.2.3.1 Cascade H-bridge:

Figure 2.3 shows the basic block of cascade H-bridge Multi-level inverter and its associated switching instants. As shown its consists of four power devices and a DC source. The switching states for four power devices are constant i.e., When S1 is on, S2 cannot be on and vice versa. Similarly with S3 and S4.

Fig 2.3 Block of a h-bridge Multi-level inverter

Figure 2.4 shows the power circuit for one phase of multi level inverter. The resulting voltage ranges from +3Vdc to -3Vdc and the staircase are nearly sinusoidal, even without filtering.

2.2.3.2 Hybrid H-bridge:

A hybrid H-bridge inverter consists of a series of H-bridge inverter units. The general function of this Multi-level inverter is to synthesize a desired voltage form several DC sources (SDCSs). Each SDCS is connected to an H-bridge inverter. The AC terminal voltages of different level inverters are connected in series. Unlike diode clamp or flying capacitors inverters the hybrid H-bridge inverter does not require any voltageclamping diodes or voltage-balancing capacitors.

Fig 2.4 Circuit diagram of 4-level cascade multi-level inverter

2.2.3.2 Single phase Hybrid H-bride inverter: 2.2.3.2(a) Principle of operation:

Figure 2.6 shows the synthesized phase voltage waveform of five-level hybrid H-bridge inverter with four SDCSs. The phase output voltage is synthesized by the sum of the four inverter outputs, Van = Va1+Va2+Va3+Va4. Each inverter circuit can generate three different outputs, +Vdc , 0 , -Vdc , by connecting the dc source to the ac output side by different combinations of four GTOs , S1,S2, S3, S4. Turning on S1 and S4 yields Va4 = +Vdc. Turning on S2 and S3 yields Va4 = -Vdc. Bypassing the source yields Va4 = 0. Similarly ac output voltage at each level can be obtained in the same manner. The circuit connections of hybrid H-bridge and cascade H-bridge are same but the basic difference between them is that we can have only voltage source of same magnitude in cascade H-bridge whereas in hybrid h-bridge we can have voltage source of different magnitude in the hybrid H-bridge. Figure 2.5 shows a single phase leg of

the hybrid Multi-Level inverter. Figure 2.6 4Vdc, 3Vdc, 2Vdc, 1Vdc and 0.

shows output waveform has the levels :

Fig 2.5 Hybrid H-Bridge inverter

Five level H-bridge Inverter output waveform

2.2.3.2(b) Advantages
1. 2. Requires the least number of components among all multi-level Converter to achieve the same number voltage levels. Modularized circuit layout and packaging is possible because each Level has the structure, and there are no extra clamping diodes or Voltage balancing capacitors. Soft switching can be used in this structure to avoid bulky and lossy resistor, capacitor, diode, snubbers.

3.

2.2.3.2(c) Disadvantages
The limitation of h-bridge is the provision of the isolated power supply for each individual H-bridge cell. For applications, where, isolated power supply cannot be provided, the requirement of capacitors and complexity of its control increases as the number of voltage levels increases, which restricts its applications.

2.3 Applications: 1. Reactive power compensator

When a Multi-level inverter draws pure reactive power, the phase voltage and current are 90 degrees apart, and the capacitor charge and discharge can be balanced. Such a converter, when serving for reactive power compensation is called Static Var Generator. The high voltage transformer . compensation multi-level structure allows all the converter to be directly connected to a distribution or transmission system without the need of a step down All the three Multi level inverters can be used in reactive power without having voltage unbalanced problem.

2. Back to Back intertie

Inter connection of two Multi-level inverter with a DC link in between is called as a Back to back intertie. In this type of circuit the left hand side converter servers as rectifier , while the right hand side serves as the inverter. The purpose of the back to back intertie is to connect to synchronous systems of different frequencies. It can be treated as a) frequency connector b) phase shifter c) a power flow controller.

3. Utility compatible adjustable speed drives

An ideal utility compatible adjustable speed drives requires unity power factor, negligible harmonics and high efficiency. By extended the back to back intertie, the multilevel inverter can be used for a utility compatible adjustable speed drive with the input as constant frequency AC source and the output has the variable frequency AC source. The major differences when using as a utility compatible adjustable speed drives and for back to back intertie, are the control design and size of capacitor.

2.4 CONCLUSION
In this chapter design of multi-level inverter discussed in detail, relevant waveforms are presented and analyzed. From this analysis it can be concluded that multilevel inverters offer a low total harmonic distortion and high efficiency. Multi-level inverters are suitable for high voltages and high current application and also have higher efficiency because the devices can be switched at a lower frequency.

CHAPTER 3 SIMULATION OF MULTI-LEVEL INVERTERS Introduction:

The multi-level inverter system is a very promising device in AC power drives when both reduced content and high power are required. Up to now several multilevel topologies have been introduced. The main topologies are diode clamped inverter, flying capacitor inverter, hybrid H-bridge inverter in order to generate a high voltage waveform using low voltage devices. In this chapter, we are considering the simulation of Hbridge inverters. Compared with diode clamped inverter and flying capacitor inverter , Hbridge inverters requires the least number of components to achieve the same number of voltage levels and H-bridge inverters does not require any extra clamping diodes or voltage balancing capacitors. Optimized circuit layout and packaging are possible in Hbridge multi-level inverter because each level has the same structure. The general structure of the H-bridge multi-level inverter is to synthesize a near sinusoidal voltage form several levels of DC voltages. As the number of levels are increased, the synthesize output waveform has more steps which produce a staircase wave that approaches the desired waveform. Also as the steps are added to the waveform the harmonic distortion of the output wave decreases. This can be observed from the figure following which are generated by simulating a single phase H-Bridge Multi level inverter and three phase H-Bridge Multilevel inverter using MATLAB SIMULINK.

3.2 Single Phase H-Bridge inverters

Fig 3.1 Single Phase Full-Bridge inverter

Fig 3.2 Single Phase Full-Bridge Inverter output waveform

Fig 3.3 Single Phase Full-Bridge Inverter Harmonic waveform

Fig 3.4 Single Phase three Level H-Bridge Inverter

Fig 3.5 Single Phase Three Level H-Bridge Inverter output wave form

Fig3.6 Single Phase Three Level H-Bridge Inverter Harmonic

Fig 3.7 Single Phase four-level H-Bridge Inverter

Fig 3.8 Single Phase four level H-Bridge inverter Harmonic waveform

Fig 3.9 Single Phase four level H-Bridge Inverter Harmonic waveform

Fig 3.10 Single Phase five level H-Bridge Inverter

Fig 3.11 Single phase five level H-bridge Inverter Harmonic waveform

Fig 3.12 Single phase five level H-Bridge Inverter Harmonic Waveform

3.3 Comparison with conventional systems

The 3rd, 5th , 7th and 9th harmonic ( normalized components ) of a H-Bridge Multilevel inverter for different number of levels are tabulated in table 3.1 3rdharmonic Content 5thharmonic content 7thharmonic content 9thharmonic content Total Harmonic Distortion

Single phase Full Bridge

24.4

1.065

10.62

12.59

0.5605

Single phase Three level

-99.69

-99.69

-99.69

-99.69

0.3831

Single phase Four level

4.318e-009

4.318e-009

4.318e-009

4.318e-009

0.3443

Single phase Five level

17

10.66

5.436

9.385

0.2979

From the above table we can observe that the harmonic content as well as the Total Harmonic Distortion (THD) factors gets reduced as the number of levels increased in a Single phase H-Bridge Multi-level inverter . This leads to a better and sinusoidal voltage waveform. We can also observe the great reduction of harmonic content in three-level HBridge inverter

CHAPTER 4 HARDWARE COMPONENTS

4.1 Introduction:
Hardware implementation aims at cascading two single level inverters to obtain a three level inverter. The key components in the hardware implementation are: 1. Power MOSFETs 2. NOT Gate 3. IR 2110 Power MOSFETs are used as switching devices, NOT Gate is in a single level inverter to give signal to negative half inverse to that of the positive half and the IR 2110 is to give gating pulses of modulated pulse width and also for phase shifting. A brief description of the above components is given in the following section.

4.2 Description of the Components 4.2.1 Power MOSFET

Metal oxide semiconductor field effect transistor (MOSFET) is a power of transistor. The switching speed of the modern transistors is much higher than that of thyristors and are extensively employed in dc-dc and dc-ac converters. However, their voltage ratings and current ratings are lower than those of thyristors and are used in low to medium-power applications. A power MOSFET is a voltage-controlled device and requires only a small input current. The switching speed is very high and the switching times are of the order of nanoseconds. As the MOSFETs conduct in the duration for which the gate pulse is present and it doesnt conduct when the gate pulse is removed, there is no need for an external commutation circuitry. Power MOSFETs find increasing applications in low-power high frequency converters. The input impendence is very high, 10^9 to 10^11 ohms. They require very low low gate energy and low switching and low conduction losses. However MOSFETs have the problem of electrostatic discharge and also its difficult to protect them under short circuited fault conditions. The two types of MOSFETs are 1. Depletion MOSFETs, and 2. Enhancement MOSFETs.

A depletion type MOSFET remains on at zero gate voltage where as an enhancement type of MOSFET remains off at zero gate voltage, the enhancement type MOSFETs are generally used as switching devices in power electronics. In this project we have used n-channel enhancement MOSFETs.

Choice of MOSFETs over other power transistors:

The other types of power transistors are BJTs (Bipolar Junction Transistors), SITs (static induction transistors), IGBTs (insulated gate bipolar transistors) and COULUMBS. MOSFETs do not have the problem of second breakdown phenomena as do BJT. A BJT is a current-controlled device and its current gain is highly dependent on the junction temperature. The high on-state drops in SITs limit its applications for general power conversions. The switching speed of IGBTs is inferior to that of MOSFETs. IGBTs are costlier than the MOSFETs. COULUMBS is a new technology for high voltage power MOSFETs, expect for switching losses (same as the conventional MOSFETs) COULUMBS is advanced and improved version of power MOSFET. Our hardware implementation is limited to three level inverters which doesnt need COULUMBS technology which is much costlier than MOSFETs.

PIN DIAGRAM OF A MOSFET

A practical MOSFET consists of three pins namely G-gate, D-drain, and S-source. Gate signal is a given between G and S. Supply is a given between D and S. its called the common source connection.

MOSFET symbol

4.2.2 NOT Gate

The NOT Gate performs a basic logic function called inversion or complementation. The purpose of the gate is to change one logic level to opposite logic level. it has one input and one output, when high level is applied as an input low level will appear at output and vice versa.

NOT GATE SYMBOL

NOT GATE TRUTH TABLE

S. No 1 2 A 1 0 X= -A 0 1

The NOT gate has been used in the project to provide inversed gate signal to the negative half of single level inverter in its hardware implementation.

NOT GATE PIN DIAGRAM

NOT GATE OUTPUT WAVEFORM

4.2.3 IR2110
The IR2110 ICs is floating channel designed for bootstrap operation. It is a high voltage, high speed power. MOSFET and IGBT drive with independent high and low side referenced output channels.

CHAPTER 5 HARDWARE IMPLEMENTATION

In this unit I discuss in detail about the hardware implementation of single h-bridge and cascaded h-bridge. The cascaded h-bridge model is used for obtaining the three level because of the advantages over the other two designs as discussed before. we also present the pictures of the waveforms obtained. The basic idea of getting the stepped waveform is to connect the desired number of sources(in series) across the load at a particular instant through fast switching devices i.e, to get a voltage level of 5Vs, we connect five voltage sources in series across the load. The next instant we need a lesser voltage level (say 4Vs), one of the sources is eliminated from the circuitry using the switching devices. So we have only four sources connected in series across the load. Hence we make use of these fast switching devices to connect or disconnect a particular source across the load. The basic idea of controlling the output voltage magnitude of inverter by using microcontroller technique is, changing the width of pulses by varying a magnitude of reference wave. Here we first present the h-bridge (single level), cascaded h-bridge(3 levels) and go on to the microcontroller. In the process we made use of IR2110 and NOT gate whose operations are discussed in previous chapters.

MULTILEVEL INVERTER IMPLEMENTATION 5.1 Single H-bridge

For obtaining single level, MOSFETs are connected as shoe in the figure. Here MOSFETs are shown as switches and are numbered for easy understanding. The applied source is a low voltage DC supply (say 15V) and the load may be a resistive one (10000 ohms).

Single H- Bridge The expected voltage across the load and the gating signals for the MOSFETs are as shown. MOSFETs conduct for the duration its gate pulse is present and is commutated as soon as the pulse is removed. So we do not need any extra commutating circuitry. The duration for which the gating signal b has to be given for a particular MOSFET is shown in shaded portion

During the first half cycle i.e., during which the MOSFETs 1&2 are fired voltage, across the output is positive and the equivalent circuit is as shown.(the MOSFET s which are not conducting during interval are not shown).

During the other half cycle i.e., during which MOSFETs 3&4 conducts, voltage across the load is negative (opposite to that assumed) and the equivalent circuit is as shown

Now to practically obtain such a gating signals we make use of NOT gate IC whose operation is discussed before. MOSFET s 1&2 are fired from function generator and MOSFETs 3&4 are fired from the NOT gate whose input is taken from the same function generator which ICs used to fire the MOSFETs 1&2. When a 10V voltage source and a resistive load of 10000 ohms is applied to the h-bridge the following waveform is observed in CRO, which is connected across the load. The entire block diagram is as shown. In the block diagram the waveform obtained is shown at the load terminal.

5.2 Cascaded H-bridge

By cascading two single h-bridges, we can get a three level inverter with levels 2Vs, Vs and 0. The circuit diagram of the cascaded configuration is as shown. The MOSFETs in the upper bridge are numbered 1,2,3 & 4 where as that of the lower bridge 1, 2, 3 & 4.

In obtaining 3-levels, we individually obtain the positive and negative cycles and by cascading the two cycles we can get the 3-level stepped waveform.

5.2.1 Positive cycle

For obtaining positive half cycle, we need to get +Vs, +2Vs and 0s. The expected wave form is as shown.

To obtain a voltage level of Vs at the load, only one the sources has to be connected to the load. For that we trigger MOSFETs 1,2 in one bridge and MOSFETs 2 and 4 in the other. this ensures only the source in the upper bridge to be connected across the load and equivalent circuit as shown.

For 2Vs,both the sources are to be connected in series across the load. this condition can be obtained by firing MOSFETs 1,2,1and 2.the circuit condition is as shown.

Therefore the MOSFETs which are to be triggered during a particular instant in order to obtain the required waveform are shown shaded portion in the figure.

Such gating signals can be obtained by making use of IR2110.firing pulses of amplitude 8Vand frequency 100hz obtained from the function generator are used to trigger MOSFETs 1,2and 2.the other MOSFETs 1and 4 can be fired with pulses from IR2110.sinusoidal signal (of amplitude 10V)whose frequency is same as that of the function generator used before(i.e. ,100hz)is being to the IR2110.IR2110 is being fed by a dc source whose amplitude is less than that of the sinusoidal signal. the output of IR2110 is given to the gate of MOSFET 1 and ground of IR2110 being given to gate of 4.the block diagram showing the connection as shown below. the output obtained is viewed in the CRO and is as shown at the load terminals in the block diagram.

5.2.2. Negative cycle

Negative cycle can be obtained similar to that of the positive half cycle. Here we need to get the voltage levels of Vs,-2Vs and 0.the expected waveform is as shown.

Similarly for obtaining a voltage level of -2Vs, MOSFETs 3, 4, 3and4 are to fired and the circuitry during this interval is as shown. The MOSFETs which are to be conducting during a particular instant is shown by shaded region below.

5.2.3. Complete waveform

The instants at which the MOSFETs are to be fired for obtaining the complete Waveform is as shown in the figure below

HARDWARE DESIGN:

OUTPUT WAVE FORM:

CHAPTER 9 CONCLUSIONS
We hereby conclude that Multi-level inverters is a very promising technology in the power industry. In this project, the advantages and applications of Multi-Level Inverters are mentioned and a detailed description of different multi-level inverter topologies is presented.

Single Phase H-Bridge Inverter & Three Phase H-Bridge Inverters functioning is realized virtually using MATLAB SIMULINK. A detailed Multi-Level Inverter is presented from which we concluded that the harmonic content is greatly reduced in Multi-Level Inverter.

A single phase Cascade H-Bridge Inverter is designed and implemented practically. The components used in the practical implementation of H-Bridge Inverter are described in detail.

Future scope of the project

This project can be extended further by increasing the number of levels in multilevel inverter. ICs can be used to generate gating pulses directly rather than designing them by using comparators and NOT gates. By using ICs, complexity in designing gate pulses can be reduced.

Reference
[1] Power Electronics Circuits, Devices & Applications , Muhammad H. Rashid, Third Edition, Prentice Hall India.

[2] Linear Integrated Circuits, D.roy Choudary, Shail B.Jain, Second Edition, New Age International Publishers. [3] Multi-level Converter-A New Breed of Power Converters, Jih-Sheng Lai and Fang Zheng Peng, IEEE Trans. Ind, Applicant Vol.32 [4] Opamps & Linear Integrated Circuits , Ramakanth Gayakward, PHI Publications. [5] Power Electronic for Technology, Ashfaq Ahmed, PEARSON Education.

APPENDIX A SOFTWARE USED EAGLE

EAGLE is an EDA program by Cad soft for creating printed circuit boards. The name is an acronym formed Easy Applicable Graphical Layout Editor. Cad soft Eagle and the company in September 2009, Premier Farnell sells, s supplier of electronic components.[1] The software consists of several components: Layout Editor, Schematic Editor , Auto router and an extensible components database . It is for the platforms Microsoft windows, Linux and Mac OS X available. It exists for non-commercial use, a free version on a schematic sheet , half Euro card num 80 mm and two signal layers is limited to 100.The schematic editor can be used by a special component library for programming a Micro SPS be used.

APPENDIX B

APPENDIX C