Lesson 4 FINITE STATE MACHINES i) Design of Sequential Circuits A sequential circuit is one with memory e.g.

elevators, traffic lights Serial Binary Adder x1

0 0 1 1 1 1 0 1 0 0

Serial Adder

x2 x1, x2: binary numbers to be added Z: sum The addition is performed serially the least significant digits of the numbers x1 and x2 arrive at their input terminals at time t1; a unit time later, the next significant digits arrive; and so on. Circuit clock frequency determines time interval. Addition of two binary numbers: t5 t4 t3 t2 t1 0 1 1 0 0 = x1 + 0 1 1 1 0 = x2 1 1 0 1 0 = Z Note, at t1and t5 inputs are x1x2 = 00 , but required outputs are Z = 0 and Z = 1 respectively Different outputs are required at times t3 and t4 for the same input pair x1x2 = 11 The output at time ti is a function of the inputs x1 and x2 at that time, and of the carry generated at ti-1 Two classes of past input histories, one resulting in a carry of 0 and the other a carry of 1. These classes are referred to as the states of the adder By memorizing the value of the carry, the adder shows some trace of its past inputs Let A = state of adder at ti if carry = 0 is generated at ti-1 B = state if carry = 1 was generated

State Table for a serial adder PS A B x1x2 = 00 A,0 A,1 Ns, Z 01 A,1 B,0 10 B,0 B,1 11 A,1 B,0

State Diagram for a serial adder

11/0 01/1 00/0 10/1

A
00/1

01/0 10/0 11/1

To implement this adder a delay element is required. One choice is a D flip-flop it has two internal states The state of a delay element (D flip-flop here) is specified by its output Y, where y may equal 0 or 1 Present input Y to D flip-flop will equal its next output value i.e. Y(t) = y(t+1) We assign the states of the D flip-flop to those of adder y = 0 is assigned to A and y = 1 to B. The value of y at ti corresponds to the value of the carry generated at ti-1 The process of assigning the states of a physical device to the states of the serial adder state assignment problem Transition and output tables for a serial adder Y 0 1
Y

Next State Y x1x2 00 01 10 11 0 0 1 0 0 1 1 1

Z

Output Z x1x2 00 0 1 01 1 0 10 0 1 11 1 0

00 01 10 11 0 1 1 1 1 1

00 01 10 11 0 1 1 1 1 1

Y = x1x2 + x1y Carry of full adder Serial binary adder

Clock pulse //synchronous

Z = x1x2y + x1x2y + x1x2y + x1x2y Sum of full adder

x1 x2

Full Adder

Z
Co

//Sum //Output carry

D f/f

The addition is accomplished by retransmitting the carry of the FA through the delay unit FAs input ii) Ciphers for Digital Messages A synchronous machine N is a part of a transmitter and is used to code binary serial messages. The coded messages are then transmitted to a receiver Note The Data Encryption Standard (DES) may be implemented in hardware, software, or firmware The receiver contains a synchronous machine M which is used to decode the received messages

1/1 Original message 0/0

1/0 Coded message Received message

A
0/1

Original message

Transmitter N

Receiver M

a) Given that the initial state of N is A, find the state diagram of machine M

b) Suppose the initial state of N is unknown and machine M above received a 10-bit message; which of the ten bits can be uniquely decoded without an error? iii) Fault Detection in Sequential Circuits Consider the following Mealy machine: M1 NS, Output input = 0 output = 1 P.S. A C,0 D,1 B C,0 A,1 C A,1 B,0 D B,0 C,1 a) Show that the output sequence that M1 produces in response to the input sequence 01 is always sufficient to determine uniquely Ms final state

Def: An input sequence Yo is said to be a homing sequence if the final state of the machine can be determined uniquely from the machines response to Yo, regardless of the initial state. So, we wish to show that 01 is a homing sequence for M1. Ms initial state Hence we have: Initial state A B C D A B C D
0/0 0/0

Response to 01 00 00 11 01

Final state B B D A

0/1 0/0

C C B

1/0

1/0 1/1 1/1

B B D A

If output = 00, M1 ends up in state B; output = 11-state and for output 01, the final state of M1 is A Def: Let M be an n-state machine. An input sequence Xo is said to be a distinguishing sequence if the output sequence produced by M in response to Xo is different for each initial state

b) Why is the sequence 01 not a distinguishing sequence for M1? c) Show that the sequence 111 is both a homing sequence and a distinguishing sequence for M1 Ms initial state
1/0 1/1 1/1 1/1

Hence we have: Initial state A B C D B C D Response to 01 110 111 011 101 Final state B C D A

A B C

1/1

1/1

1/0 1/1

D C B A Observe that output produced by M1 is different for each initial state. Hence it is possible to determine M1s initial state Also, the final states are uniquely depending only on M1s initial state Uncertainty and the Successor Tree Suppose that a machine M can initially be in any one of its n states. We say that the initial uncertainty regarding the state of the machine is (Q1Q2Qn). Thus, the initial uncertainty is the minimal subset of Q (including Q itself), which is known to contain the initial state. e.g. if M1 can initially be in any of its four states, then the initial uncertainty is (ABCD) Our aim is to perform experiments M1: A B C D that reduce the initial uncertainty and wherever possible reveal the initial or final state 0 C,0 C,0 A,1 B,0 1 D,1 A,1 B,0 C,1

D A B

1/1

1/1 1/1 1/0

C D A

Level 0
CC occurs homogeneous uncertainty vector

(ABCD)
0 1

output 1 0

(A)(BCC) output 0
1

- // uncertainty vector

output 1 0

(ACD)(B) output 0
1

(AA)
ncertainty components

(A)(BB)(D)
0

(A)(BC)(C)
1

(A)(B)(CD)
0 1

(A)(A)(C)(CC)

(A)(B)(B)(D) (A)(B)(C)(C)

(A)(B)(C)(D)

Homing Experiment The homing tree: A homing sequence for a given machine M may be obtained from a truncated version of its successor tree A homing tree is a successor tree in which a jth-level node becomes terminal when either of the following occur: 1) The node is associated with an uncertainty vector whose non-homogeneous components are associated with some node in a preceding level 2) Some node in the jth-level is associated with a trivial or a homogeneous vector

M2: level P.S. A B C D

0 1 2 3 (AB)(DD) (AB)(DD) (BD)(CC) (A)(D)(DD) (AA)(BC)

NS, Z X=0 X=1 B,0 D,0 A,0 B,0 D,1 A,0 D,1 C,0
(ABCD) (ABCD)
* 0 ** 010 is the shortest homing sequence 1 0 0 1 1 **

nodes terminated * (AB)(DD) since its predecessor is (AB)(DD) ** (ABCD) is identical to its predecessor ** Both nodes terminated as (A)(D)(DD) is homogeneous

The response of M2 to the homing sequence 010 Initial State A B C D Response to 010 000 001 101 101 Final State A D D D

Theorem: A preset homing sequence whose length is at most (n-1)2 exists for every reduced n-state machine (Actually the length needed never exceeds 1/2n(n-1), but the proof of this tight bound is tougher) These notes are based upon material in Switching and Finite Automata Theory by Zvi Kohavi, McGraw-Hill Cp.13 also describes algorithms for finding Distinguishing Sequences, solving the Machine Identification problem, and Fault Detection for Sequential circuits