PN SEQUENCE GENERATOR

Tanvir Manhotra, Amit Kulkarni, Rushab Karani

Abstract Pseudo noise sequence is essentially a

random sequence of binary numbers. So PN sequence generator is nothing but random binary number generator. It is random in a sense that the value of an element of the sequence is independent of the values of any of the other elements. It is 'pseudo' because it is deterministic and after N elements it starts to repeat itself, unlike real random sequences. The implementation of PN sequence generator is based on the linear feedback shift register (LFSR). The PN sequence generator produces a predefined sequence of 1's and 0's, with 1 and 0 occurring with the same probability. A sequence of consecutive (2^n -1) bits comprise one data pattern, and this pattern will repeat itself over time. Our project explores the PN sequence generator in detail along with its applications in spread spectrum

propagates the stored patterns from left to right. The modification that provides the PRBS generation is due to the XOR feedback of the selected flip-flop outputs, named taps. When the taps are chosen properly, the LFSR will traverse through all possible states except for the all 0s state and will produce a maximum length PRBS sequence named M-sequence.

II. PSEUDO NOISE SEQUENCES

Pseudo noise sequences (PRBSs) are widely used for testing hardware for digital communication. Testing of hardware for digital communication requires transmission and reception of a signal that subjects the transmission channel to the characteristics of random digital signal. A PN sequence is a random bit sequence that repeats itself, thus not truly random, as the name implies. A truly random sequence never repeats itself, but truly random sequences are difficult to generate, and would have very little use in practical systems. However PN sequence with long sequence lengths (several billion bits) show close resemblance to truly random signals, and are sufficient for test purposes. PN sequence have well known properties, and the generation and acquisition of them are simple. Knowing how a PRBS is generated makes it possible to predict the sequence. This is a very desirable feature when testing hardware for digital communication, as it allows you to predict how an incoming sequence is supposed to look. This makes it possible to register and count any errors that might occur in the sequence. PN sequence can be generated by shifting bits through a number (N) of cascaded registers, where some of the register outputs (referred to as tap sets) are added modulo-2 and fed back to the input of the first register. The maximal length of the sequence is determined by the number of possible states that the shift register can assume, and the properties of the sequence is determined by which tap sets that are modulo-2 added and feed back to the first register. This type of PRBS generator is called a linear feedback shift

Keywords Psuedonoise, LFSR, spread spectrum

I.

INTRODUCTION

The field of wireless communications is currently growing at an unprecedented rate. This growth, prompted in part by the demand for more high-speed, broadband communication systems, has led to the need for highresolution, broadband wireless measurement equipment. The mobile communication system is one of the most important phenomenon in the history of telecommunication which has enriched human civilization and mankind by bringing business and community together.. In Spread Spectrum CDMA (SS-CDMA) system each user is assigned a pseudo noise (PN) sequence for the purpose of spreading as well as dispreading. Thus PN-sequence generation is considered to be the heart of SS-CDMA system. The maximal length PN-sequence (m-sequence) is the best known PN-sequence whose length is equal to its period. Various PN-codes can be generated using Linear Feedback Shift Register (LFSR).The generator polynomial provides the necessary feedback taps for the LFSR circuit. The implementation of the LFSR circuit with VLSI technology makes it useful in low-power communication system design. LFSR is basically, a shift register configuration that

III. MAXIMUM LENGTH SEQUENCES

LFSR's can have multiple maximal length tap sequences. A maximal length tap sequence also describes the exponents in what is known as a primitive polynomial mod 2. Example,

a tap sequence of 4, 1 describes the primitive polynomial x^4 + x^1 + 1. Finding a primitive polynomial mod 2 of degree n (the largest exponent in the polynomial) will yield a maximal length tap sequence for an LFSR that is n bits long. There is no quick way to determine if a tap sequence is maximal length. However, there are some ways to tell if one is not maximal length: a. Maximal length tap sequences always have an even number of taps. b. The tap values in a maximal length tap sequence are all relatively prime. A tap sequence like 12, 9, 6, 3 will not be maximal length because the tap values are all divisible by 3. Discovering one maximal length tap sequence leads automatically to another. If a maximal length tap sequence is described by [n, A, B, C], another maximal length tap sequence will be described by [n, n-C, n-B, n-A]. Thus, if [32, 3, 2, 1] is a maximal length tap sequence, [32, 31, 30, 29] will also be a maximal length tap sequence. An interesting behaviour of two such tap sequences is that the output bit streams are mirror images in time. CHARACTERISTICS OF OUTPUT STREAM: By definition, the period of an LFSR is the length of the output stream before it repeats. Besides being non-repetitive, a period of a maximal length stream has other features that are characteristic of random streams.

IV. WORKING
Our project comprises of VHDL modelling of four different PN sequence generators. We have depicted the simulation of Maximal length sequences. Hence, the sequence repeats after 2^n-1 bits, where n is the number of LFSR. The different PN generators are as follows:

A. For 3 LFSR- [2,0]

In this case, LFSR(2) receives input which is the result of XOR of output of LFSR(2) and LFSR(0)

a. Sums of ones and zeroes.

In one period of a maximal length stream, the sum of all ones will be one greater than the sum of all zeroes. In a random stream, the difference between the two sums will tend to grow progressively smaller in proportion to the length of the stream as the stream gets longer. In an infinite random stream, the sums will be equal.

b.

Runs of ones and zeroes.

A run is a pattern of equal values in the bit stream. A bit stream like 10110100 has six runs of the following lengths in order: 1, 1, 2, 1, 1, 2. One period of an n-bit LFSR with a maximal length tap sequence will have 2^(n-1) runs (e.g., a 5 bit device yields 16 runs in one period). 1/2 the runs will be one bit long, 1/4 the runs will be 2 bits long, 1/8 the runs will be 3 bits long, etc., up to a single run of zeroes that is n1 bits long and a single run of ones that is n bits long. A random stream of sufficient length shows similar behaviour statistically.

In this PN sequence, the sequence repeats after (2^3-1) i.e., 7 bits. The number of ones are one greater than the number of zeroes. Four runs can be observed: i. 00 ii. 111 iii. 0 iv. 1 If this sequence is used in direct sequence spread spectrum then at the transmitter side we have: Let the modulated data be: 1100101

c.

Shifted stream.

Take the stream of bits in one period of an LFSR with a maximal length tap sequence and circularly shift it any number of bits less than the total length. Do a bitwise XOR with the original stream. A random stream also shows this behaviour. One characteristic of the LFSR output not shared with a random stream is that the LFSR stream is deterministic. Given knowledge of the present state of the LFSR, the next state can always be predicted.

The encoded data is then transmitted over the channel and at receiver end we decode the data using a locally generated synchronised PN sequence:

Gold sequences have the property that the cross-correlation between any two, or between shifted versions of them, takes on one of three values: -t(n), -1, or t(n) - 2, where

The Gold Sequence Generator block uses two PN Sequence Generator blocks to generate the preferred pair of sequences, and then XORs these sequences to produce the output sequence, as shown in the following diagram

B. 5 LFSR-[4,3,1,0]
In this PN sequence generator, 5 LFSR are used. The random sequence repeats after (2^5-1) i.e., 31 bits.

The above sequence generator can be used for data transmission and reception in the same way as 3-LFSR sequence generator We have used two 6-LFSR PN sequence generators [5,0] and [5,4,1,0]:

C. GOLD SEQUENCE
The Gold Sequence Generator block generates a Gold sequence. Gold sequences form a large class of sequences that have good periodic cross-correlation properties. The Gold sequences are defined using a specified pair of sequences u and v, of period N = 2n - 1, called a preferred pair, as defined in the following section, Preferred Pairs of Sequences. The set G(u, v) of Gold sequences is defined by

where T represents the operator that shifts vectors cyclically to the left by one place. Note that G(u,v) contains N + 2 sequences of period N. The Gold Sequence Generator block outputs one of these sequences according to the block's parameters.

D. 8-LFSR-[8,7,6,5,2,1]
In this case, the 8 linear feedback shift registers are used. The sequence repeats after (2^8-1) bits

If an undesired transmitter transmits on the same channel but with a different PN sequence (or no sequence at all), the de-spreading process results in no processing gain for that signal. This effect is the basis for the code division multiple access (CDMA) property of DSSS, which allows multiple transmitters to share the same channel within the limits of the cross-correlation properties of their PN sequences.

The above sequence generator can be used for data transmission and reception in the same way as 3-LFSR sequence generator

V. APPLICATIONS
A. Direct sequence spread spectrum
Direct-sequence spread-spectrum transmissions multiply the data being transmitted by a "noise" signal. This noise signal is a pseudorandom sequence of 1 and 1 values, at a frequency much higher than that of the original signal.

B. Use as Built in self tester (BIST) At the heart of this BIST approach, lie a pseudo-random binary sequence (PRBS) generator and a signature register. The PRBS generator is most easily implemented using a linear feedback shift register (LFSR). A PRBS generator allows us to generate all (well, almost all) of the required binary patterns for the circuit under test. The LFSR can be used to both generate the test sequence for the design that is to incorporate BIST and with slight modification can be used to capture the response of the design and generate a signature (the bit pattern held in the signature register). The signature in the signature register can be compared to a known good signature. Within certain realms of mathematical probablity, if the signature for the circuit being tested is the same as the known good signature, then the tested circuit is deemed as being functionally correct. There is a little maths involved in discovering the known good value for the signature of the circuit being tested but more on that in Part Two. This month we are going to concentrate on the design of an LFSR and one kind of signature register. The maximal length LFSR generates data that is almost random (hence the term pseudorandom'). The output of the LFSR can be taken in parallel-out form or as a serial bit stream. The serial bit stream is usually taken from the MSB of the LFSR. Given taps 6 and 9, it turns out that the only pattern not generated is all zeroes. It is a fairly simple task to add a little extra circuitry to generate this pattern, but we won't tackle this just yet. Naturally this would give us a RBS generator, not a pseudo to be seen

The resulting signal resembles white noise, like an audio recording of "static". However, this noise-like signal can be used to exactly reconstruct the original data at the receiving end, by multiplying it by the same pseudorandom sequence (because 1 1 = 1, and 1 1 = 1). This process, known as "de-spreading", mathematically constitutes a correlation of the transmitted PN sequence with the PN sequence that the receiver believes the transmitter is using. The resulting effect of enhancing signal to noise ratio on the channel is called process gain. This effect can be made larger by employing a longer PN sequence and more chips per bit, but physical devices used to generate the PN sequence impose practical limits on attainable processing gain.

VI. ABOUT XILINX

Xilinx designs, develops and markets programmable logic products including integrated circuits (ICs), software design tools, predefined system functions delivered as intellectual property (IP) cores, design services, customer training, field engineering and technical support. Xilinx sells both FPGAs and CPLDs programmable logic devices for electronic equipment manufacturers in end markets such as communications, industrial, consumer, automotive and data processing. Xilinx FPGAs can run a regular embedded OS (such as Linux or vxWorks) and can implement processor peripherals in programmable logic. Xilinx

delivers programmable platforms to help design engineers make their vision a reality. Xilinx programmable chips are the innovation platform of choice for today's leading companies for the design of tens of thousands of products that improve the quality of our everyday lives. Xilinx designs, develops and markets programmable logic products including integrated circuits (ICs), software design tools, predefined system functions delivered as intellectual property (IP) cores, design services, customer training, eld engineering and technical support.

VIII.

Features of CPLD

VII. CPLD Kit

The design of a digital system using PLD often requires the connection of several devices to produce the complete specification. For these type of applications, Complex Programmable Logic Devices (CPLD) are more suitable. A CPLD is a collection of individual PLDs on a single integrated circuit. A programmable interconnection structure allows the PLDs to be connected to each other in the same way that can be done with the individual PLDs. Now, the switch matrix receives inputs from the I/O block and directs it to the individual macrocells. Similarly, selected outputs from macrocells are sent to the outputs as needed. Each PLD typically contains from 8 to 16 macrocells. The macrocells within each PLD are usually fully connected. If a macrocell has unused product terms they can be used by other nearby macrocells. Different manufacturers use different approaches to make individual PLDs, the type of macrocells, I/O blocks and the programmable interconnection structure. The basic component used in PLD is the gate array. A gate array consists of pattern of gates fabricated in an area of silicon that is repeated thousands of times until the entire chip is covered with the gates.

1. High performance -5 ns pin to pin logic delay Counter frequency 125 MHz 2. Large density range -36-288 macrocells with upto 6000 usable gates. 3. Enhanced pin locking architecture. 4. Programmable power reduction mode in each macrocell. 5. Slew rate control. 6. High drive 24 mA output. 7. Advanced CMOS 5v fast Flash technology. 8. Flexible 36V 18 function block-90 product terms drive any or all of 18 macro cells within function block-global and product term clocks, output enables, set and reset signals. 9. Extensive IEEE std 1149.1 boundary scan(JTAG) support. 10. Programmable power reduction mode in each macrocell. 11. Skew rate controlled on individual outputs. 12. User programmable ground pin capability.

CONCLUSION
This report discussed the concept of pseudo random sequences as applicable to spread spectrum communications. Maximal length sequences were introduced, and used as an introduction to more complicated methods of PN code generation with the help of LFSRS. The linear feedback shift register (LFSR) is a shift register which, using feedback, modifies itself on each rising edge of the clock. The code for implementing the required P N sequences as well as gold code was realized by writing VHDL program and the subsequently, the simulation was observed.

REFERENCES
[1] Circuit Design with VHDL, Volnei A. Pedroni, The MIT Press [2]Digital Design Principles and Practices, John K.Wakerley, Pearson Education [3] Communication Systems, Simon Haykin., John Wiley and Sons. [4] Designing cdma2000 Systems., Leonhard Korowajczuk, Bruno de Souza Abreu Xavier, John Wiley and Sons. [5] WCDMA Design Handbook, Andrew Richardson, Cambridge university press. [6] www.xilinx.com [7] en.wikipedia.org