16-Channel, 8-Channel, Differential 8-Channel and Differential 4-Channel, CMOS Analog MUXs with Active Overvoltage Protection
The HI-506A, HI-507A, HI-508A and HI-509A are analog multiplexers with active overvoltage protection. Analog input levels may greatly exceed either power supply without damaging the device or disturbing the signal path of other channels. Active protection circuitry assures that signal fidelity is maintained even under fault conditions that would destroy other multiplexers. Analog inputs can withstand constant 70VP-P levels with 15V supplies. Digital inputs will also sustain continuous faults up to 4V greater than either supply. In addition, signal sources are protected from short circuiting should multiplexer supply loss occur. Each input presents 1k of resistance under this condition. These features make the HI-506A, HI-507A, HI-508A and HI-509A ideal for use in systems where the analog inputs originate from external equipment, or separately powered circuitry. All devices are fabricated with 44V dielectrically isolated CMOS technology. The HI-506A is a single 16-channel multiplexer, the HI-507A is an 8-channel differential multiplexer, the HI-508A is a single 8-channel multiplexer and the HI-509A is a differential 4-channel multiplexer. If input overvoltage protection is not needed the HI-506/507/508/509 multiplexers are recommended. For further information see Application Notes AN520 and AN521.
Features
Analog Overvoltage . . . . . . . . . . . . . . . . . . . . . . . . 70VP-P No Channel Interaction During Overvoltage Maximum Power Supply . . . . . . . . . . . . . . . . . . . . . . 44V Fail Safe with Power Loss (No Latch-Up) Break-Before-Make Switching Analog Signal Range . . . . . . . . . . . . . . . . . . . . . . . . 15V Access Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . 7.5mW
Applications
Data Acquisition Systems Industrial Controls Telemetry
Ordering Information
PART NUMBER HI1-0506A-2 HI1-0506A-5 HI1-0506A-8 HI3-0506A-5 HI3-0507A-5 HI1-0508A-8 HI3-0508A-5 HI1-0509A-2 HI1-0509A-5 HI1-0509A-8 HI3-0509A-5 TEMP. RANGE (oC) -55 to 125 0 to 75 PACKAGE 28 Ld CERDIP 28 Ld CERDIP PKG. DWG. # F28.6 F28.6 F28.6 E28.6 E28.6 F16.3 E16.3 F16.3 F16.3 F16.3 E16.3
-55 to 125 16 Ld CERDIP + 160 Hour Burn-In +0 to 75 -55 to 125 0 to 75 16 Ld PDIP 16 Ld CERDIP 16 Ld CERDIP
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2003. All Rights Reserved
HI-507A
OUT A
1K IN 1 1K IN 2
OUT
DIGITAL INPUT
PROTECTION VREF A0 A1 A2 A3 EN
5V REF
LEVEL SHIFT
DIGITAL INPUT
PROTECTION
VREF A0
A1
A2
EN
HI-508A
1K IN 1A 1K IN 4A DECODER/ DRIVER 1K IN 8 IN 4B OVERVOLTAGE CLAMP AND SIGNAL ISOLATION 5V REF LEVEL SHIFT 1K 1K IN 1B
HI-509A
OUT A
1K IN 1 1K IN 2
OUT
OUT B
DECODER/ DRIVER
DIGITAL INPUT
PROTECTION A0
5V REF
LEVEL SHIFT
A1
A2
EN
DIGITAL INPUT
PROTECTION A0
A1
EN
OVERVOLTAGE PROTECTION V+ D2
R2 R5 R3 N N R4 R6 N N N N R8 N N R7
R1 200
D1
N GND V-
VADD IN
ADDRESS DECODER
V+
N A0 OR A0
A1 OR A1
A2 OR A2
A3 OR A3
ENABLE DELETE A3 OR A3 INPUT FOR HI-507A, HI-508A, HI-509A DELETE A2 OR A2 INPUT FOR HI-509A
V-
V+ P Q5
R11 1K IN
D6
D7
D4
D5
N OUT
N Q6
VP FROM DECODE
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) JC (oC/W) 28 Ld CERDIP Package. . . . . . . . . . . . 55 18 16 Ld CERDIP Package. . . . . . . . . . . . 75 22 28 Ld PDIP Package . . . . . . . . . . . . . . 60 N/A 16 Ld PDIP Package . . . . . . . . . . . . . . 90 N/A Maximum Junction Temperature CERDIP Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175oC PDIP Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
Operating Conditions
Temperature Ranges HI-506A/507A/508A/509A-2, -8 . . . . . . . . . . . . . . -55oC to 125oC HI-506A/507A/508A/509A-5. . . . . . . . . . . . . . . . . . . . 0oC to 75oC
CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
Supplies = +15V, -15V; VREF Pin = Open; VAH (Logic Level High) = 4V; VAL (Logic Level Low) = 0.8V, Unless Otherwise Specified. For Test Conditions, Consult Test Circuits Section TEST CONDITIONS TEMP (oC) -2, -8 MIN TYP MAX MIN -5 TYP MAX UNITS
Note 2
25 Full
25 -
25 -
s s ns ns ns ns ns s s s s dB pF
Note 2 Note 2
25 25 Full
Note 2
25 Full
Settling Time, tS HI-506A and HI-507A To 0.1% To 0.01% HI-508A and HI-509A To 0.1% To 0.01% Off Isolation Channel Input Capacitance, CS(OFF) Channel Output Capacitance, CD(OFF) HI-506A HI-507A HI-508A HI-509A Digital Input Capacitance, CA Input to Output Capacitance, CDS(OFF) DIGITAL INPUT CHARACTERISTICS Input Low Threshold, TTL Drive, VAL Input High Threshold, VAH (Note 9) Input Leakage Current (High or Low), IA Note 2 Note 2 Notes 2, 6 Full Full Full 4.0 0.8 1.0 4.0 0.8 1.0 V V A 25 25 25 25 25 25 52 30 25 12 10 0.1 52 30 25 12 10 0.1 pF pF pF pF pF pF Note 7 25 25 25 25 25 25 50 1.2 3.5 1.2 3.5 68 10 50 1.2 3.5 1.2 3.5 68 10 -
PARAMETER MOS Drive, VAL , HI-506A/HI-507A MOS Drive, VAH , HI-506A/HI-507A ANALOG CHANNEL CHARACTERISTICS Analog Signal Range, VIN On Resistance, rON
Note 2 Notes 2, 3
Full 25 Full
-15 -
+15 1.5 1.8 50 300 200 200 100 2.0 300 200 200 100 50
-15 -
+15 1.8 2.0 50 300 200 200 100 300 200 200 100 50
V k k nA nA nA nA nA nA nA nA A nA nA nA nA nA nA
Notes 2, 4
25 Full
Off Output Leakage Current, ID(OFF) HI-506A HI-507A HI-508A HI-509A ID(OFF) With Input Overvoltage Applied
Notes 2, 4
Note 5
25 Full
On Channel Leakage Current, ID(ON) HI-506A HI-507A HI-508A HI-509A Differential Off Output Leakage Current, IDIFF , (HI-507A, HI-509A Only) POWER SUPPLY CHARACTERISTICS Current, I+ Current, IPower Dissipation, PD NOTES:
Notes 2, 4
Notes 2, 8 Notes 2, 8
2.0 1.0 -
2.0 1.0 -
mA mA mW
2. 100% tested for Dash 8. Leakage currents not tested at -55oC. 3. VOUT = 10V, IOUT = +100A. 4. 10nA is the practical lower limit for high speed measurement in the production test environment. 5. Analog Overvoltage = 33V. 6. Digital input leakage is primarily due to the clamp diodes (see Schematic). Typical leakage is less than 1nA at 25oC. 7. VEN = 0.8V, RL = 1K, CL = 15pF, VS = 7VRMS , f = 100kHz. 8. VEN , VA = 0V or 4V. 9. To drive from DTL/TTL Circuits, 1k pull-up resistors to +5V supply are recommended.
V2
IN
OUT V2 100A
VIN
rON =
1.4 1.3 ON RESISTANCE (k) 1.2 1.1 25oC 1.0 0.9 0.8 0.7 0.6 -10 -55oC NORMALIZED RESISTANCE (REFERRED TO VALUE AT 15V) 125oC 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 -8 -6 -4 -2 0 2 4 ANALOG INPUT (V) 6 8 10 5 6 7 8 9 10 11 12 13 14 15 SUPPLY VOLTAGE (V) -55oC TO 125oC VIN = +5V
FIGURE 1. ON RESISTANCE
100nA
ID(OFF)
100pA
10pA
25
50
75
100
125
TEMPERATURE (oC)
10V
10V
OUT A ID(ON)
10. Two measurements per channel: 10V and +10V. (Two measurements per device for ID(OFF) 10V and +10V.) FIGURE 2. LEAKAGE CURRENTS
18 ANALOG INPUT CURRENT (mA) 15 12 9 6 3 0 15 18 21 24 27 30 33 36 ANALOG INPUT OVERVOLTAGE (V) OUTPUT OFF LEAKAGE CURRENT ID(OFF) ANALOG INPUT CURRENT (IIN)
6 5 4 3 2 1 0
14 -55oC 12 SWITCH CURRENT (mA) 10 8 6 4 2 0 0 2 4 6 8 10 12 14 VOLTAGE ACROSS SWITCH (V) VIN A 25oC
10V
10V
10V
4V
IIN
ID(OFF)
VIN
125oC
10
TA = 25oC, VSUPPLY = 15V, VAH = 4V, VAL = 0.8V, VREF = Open, Unless Otherwise Specified (Continued)
+15V/+10V +ISUPPLY
50
10V/
10 M
A -ISUPPLY -15V/-10V
900 800 ACCESS TIME (ns) 700 600 500 +4V 400 300 3 4 5 6 7 8 9 10 11 12 LOGIC LEVEL (HIGH) (V) 13 14 15 VA 50 VREF = OPEN FOR LOGIC HIGH LEVEL 6V VREF = LOGIC HIGH FOR LOGIC HIGH LEVELS > 6V A3 A2 A1 A0 EN GND VREF
+15V
V+ IN 1
10V
10 k
-15V
VAH = 4.0V
1/ V 2 AH
VA INPUT 2V/DIV. S1 ON
OUTPUT 5V/DIV.
-10V
S16 ON 200ns/DIV.
11
5V
14 pF
50 pF
A3 A2
HI-506A IN 1 IN 2 THRU
VA
50
A1 A0
+4.0V
EN
OUTPUT
tOPEN
VA INPUT 2V/DIV.
S1 ON
S16 ON
OUTPUT 0.5V/DIV.
100ns/DIV.
12
A3 A2
HI-506A IN 1 IN 2 THRU IN 7/IN 15 IN 8 /IN 16 +10V VAH = 4.0V 50% 50% ENABLE DRIVE (VA) 0V OUT GND 1k VOUT 50pF
A1 A0 EN VA 50
tOFF(EN)
DISABLED
OUTPUT 2V/DIV.
100ns/DIV.
13
WORST CASE CURRENT DENSITY: 1.4 x 105 A/cm2 TRANSISTOR COUNT: 485 PROCESS: CMOS-DI
HI-507A
A1 A2 (16) (15) NC VREF (14) (13) GND (12)
IN 1 (19) IN 2 (20)
IN 9 (11) IN 10 (10)
IN 1A (19) IN 2A (20)
IN 1B (11) IN 2B (10)
IN 3 (21) IN 4 (22)
IN 11 (9) IN 12 (8)
IN 3A (21) IN 4A (22)
IN 3B (9) IN 4B (8)
IN 5 (23) IN 6 (24)
IN 13 (7) IN 14 (6)
IN 5A (23) IN 6A (24)
IN 5B (7) IN 6B (6)
IN 7 (25) IN 8 (26)
IN 15 (5) IN 16 (4)
IN 7A (25) IN 8A (26)
IN 7B (5) IN 8B (4)
V- (27)
OUT (28)
+V (1)
NC (2)
V- (27)
OUT A (28)
+V (1)
OUT B(2)
14
WORST CASE CURRENT DENSITY: 1.4 x 105 A/cm2 TRANSISTOR COUNT: 253 PROCESS: CMOS-DI
IN 6 (11)
IN 7 IN 8 (10) (9)
OUT (8)
IN 4 IN 3 (7) (6)
OUT A (8)
IN 4A IN 3A (7) (6)
A2 (15)
A1 (16)
A0 (1)
EN (2)
GND (15)
A1 (16)
A0 (1)
EN (2)
15
HI-506A, HI-507A, HI-508A, HI-509A Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
c1 -A-DBASE METAL E b1 M -Bbbb S BASE PLANE SEATING PLANE S1 b2 b ccc M C A-B S A A C A-B S D Q -CA L D S M (b) SECTION A-A (c) LEAD FINISH
F28.6 MIL-STD-1835 GDIP1-T28 (D-10, CONFIGURATION A) 28 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
INCHES SYMBOL A b b1 b2 b3 c MIN 0.014 0.014 0.045 0.023 0.008 0.008 0.500 MAX 0.232 0.026 0.023 0.065 0.045 0.018 0.015 1.490 0.610 MILLIMETERS MIN 0.36 0.36 1.14 0.58 0.20 0.20 12.70 MAX 5.92 0.66 0.58 1.65 1.14 0.46 0.38 37.85 15.49 NOTES 2 3 4 2 3 5 5 6 7 2, 3 8 Rev. 0 4/94
eA
c1 D E e eA eA/2 L Q S1
e
D S
eA/2
0.100 BSC 0.600 BSC 0.300 BSC 0.125 0.015 0.005 90o 28 0.200 0.060 105o 0.015 0.030 0.010 0.0015
2.54 BSC 15.24 BSC 7.62 BSC 3.18 0.38 0.13 90o 28 5.08 1.52 105o 0.38 0.76 0.25 0.038
aaa M C A - B S D S
NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturers identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH.
16
MILLIMETERS MIN 0.39 3.18 0.356 0.77 0.204 35.1 0.13 15.24 12.32 MAX 6.35 4.95 0.558 1.77 0.381 39.7 15.87 14.73 NOTES 4 4 8 5 5 6 5 6 7 4 9 Rev. 1 12/00
MIN 0.015 0.125 0.014 0.030 0.008 1.380 0.005 0.600 0.485
A
E A2 L A C L
A1 A2
-C-
B B1 C D D1 E E1 e eA eB L N
eA eC
C
C A B S
eB
NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the MO Series Symbol List in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
17
HI-506A, HI-507A, HI-508A, HI-509A Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
c1 -A-DBASE METAL E b1 M -Bbbb S BASE PLANE SEATING PLANE S1 b2 b ccc M C A-B S A A C A-B S D Q -CA L D S M (b) SECTION A-A (c) LEAD FINISH
F16.3 MIL-STD-1835 GDIP1-T16 (D-2, CONFIGURATION A) 16 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
INCHES SYMBOL A b b1 b2 b3 c MIN 0.014 0.014 0.045 0.023 0.008 0.008 0.220 MAX 0.200 0.026 0.023 0.065 0.045 0.018 0.015 0.840 0.310 MILLIMETERS MIN 0.36 0.36 1.14 0.58 0.20 0.20 5.59 MAX 5.08 0.66 0.58 1.65 1.14 0.46 0.38 21.34 7.87 NOTES 2 3 4 2 3 5 5 6 7 2, 3 8 Rev. 0 4/94
eA
c1 D E e eA eA/2 L Q S1
e
D S
eA/2
0.100 BSC 0.300 BSC 0.150 BSC 0.125 0.015 0.005 90o 16 0.200 0.060 105o 0.015 0.030 0.010 0.0015
2.54 BSC 7.62 BSC 3.81 BSC 3.18 0.38 0.13 90o 16 5.08 1.52 105o 0.38 0.76 0.25 0.038
aaa M C A - B S D S
NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturers identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH.
18
-C-
A2 B B1 C D D1 E E1 e eA eB L N
eA eC
C
C A B S
eB
NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the MO Series Symbol List in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
2.93
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