CpE358/CS381 Switching Theory and Logical Design Class 8

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CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

1-291

Today
Fundamental concepts of digital systems (Mano Chapter 1) Binary codes, number systems, and arithmetic (Ch 1) Boolean algebra (Ch 2) Simplification of switching equations (Ch 3) Digital device characteristics (e.g., TTL, CMOS)/design considerations (Ch 10) Combinatoric logical design including LSI implementation (Chapter 4) Flip-flops and state memory elements (Ch 5) Sequential logic analysis and design (Ch 5) Hazards, Races, and time related issues in digital design (Ch 9) Synchronous vs. asynchronous design (Ch 9) Counters, shift register circuits (Ch 6) Memory and Programmable logic (Ch 7) Minimization of sequential systems Introduction to Finite Automata

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CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

1-292

Typical Sequential Circuit

Description by State Equations

D Q Q

D Q Q

D Q Q

A(t + 1) = x C (t ) B(t + 1) = A(t ) C (t + 1) = B(t )

Clock

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CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

1-294

Typical Sequential Circuit

Present State Input C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 A Next State B C Output 1-295

Description by State Table

A 0 0 0 0

B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

D Q Q

D Q Q

D Q Q

0 0 0 1

Clock

1 1 1 1 1 1 1
CpE358/CS381 Switching Theory and Logical Design Summer-1 2004 Copyright 2004 Stevens Institute of Technology All rights reserved

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Typical Sequential Circuit

Present State Input C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 A Next State B 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 C 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Output 1-296

Description by State Table

A 0 0 0 0

B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

D Q Q

D Q Q

D Q Q

0 0 0 1

Clock

1 1 1 1 1 1 1
CpE358/CS381 Switching Theory and Logical Design Summer-1 2004 Copyright 2004 Stevens Institute of Technology All rights reserved

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Typical Sequential Circuit

Present State Input C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 A 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 Next State B 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 C 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Output 1-297

Description by State Table

A 0 0 0 0

B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

D Q Q

D Q Q

D Q Q

0 0 0 1

Clock

1 1 1 1 1 1 1
CpE358/CS381 Switching Theory and Logical Design Summer-1 2004 Copyright 2004 Stevens Institute of Technology All rights reserved

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Typical Sequential Circuit

Description by State Diagram

001 1 x
D Q Q A D Q Q B D Q Q C

0 000 1

0 1 010 110 0 1 111 1 101 0 1

100

0 1

Clock

0 011

0 1

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CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

1-298

Sequential System Design

Start with a description of the system operation: Design a sequential circuit to output a 1 if there have been an even number of 1s received since the last 0. Output 0 otherwise

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CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

1-299

Sequential System Design

Start with a description of the system operation: Design a sequential circuit to output a 1 if there have been an even number of 1s received since the last 0. Output 0 otherwise (Generally) The next step is to draw the state diagram 1 0 even/1 0 odd/0

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CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

1-300

Sequential System Design

Start with a description of the system operation: Design a sequential circuit to output a 1 if there have been an even number of 1s received since the last 0. Output 0 otherwise (Generally) The next step is to draw the state diagram 1 0 even/1 0 odd/0

1 See if any states can be eliminated. From the number of states, determine the minimum number of flip-flops needed. Also determine if there is a simple way to assign states that might use more flipflops, but would make combinatorial logic simpler. In this case, there are two states. Nff = log2(Nstates) = log2(2) = 1
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CpE358/CS381 Switching Theory and Logical Design Summer-1 2004 Copyright 2004 Stevens Institute of Technology All rights reserved

1-301

Sequential System Design

Write the state equations or state table (or both)
Present State even even odd odd Input 0 1 0 1 Next State even odd even even Output 1 0 1 1

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CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

1-302

Sequential System Design

Write the state equations or state table (or both)
Present State even even odd odd Input 0 1 0 1 Next State even odd even even Output 1 0 1 1

Number states in some logical fashion Here, it makes sense to use the states 0 and 1, and let these values correspond to the output, so even=1 and odd=0

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CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

1-303

Sequential System Design

Write the state equations or state table (or both)
Present State even even odd odd Input 0 1 0 1 Next State even odd even even Output 1 0 1 1

Number states in some logical fashion Here, it makes sense to use the states 0 and 1, and let these values correspond to the output, so even=1 and odd=0 Assign flip-flops to state number to make decoding straightforward There is only one flip-flop in this case, so the assignment is direct

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CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

1-304

Sequential System Design

Write the state equations or state table (or both)
Present State even even odd odd Input 0 1 0 1 Next State even odd even even Output 1 0 1 1

Number states in some logical fashion Here, it makes sense to use the states 0 and 1, and let these values correspond to the output, so even=1 and odd=0 Assign flip-flops to state number to make decoding straightforward There is only one flip-flop in this case, so the assignment is direct Relabel state table with state assignments
Present State 1 1 0 0
CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Input 0 1 0 1

Next State 1 0 1 1

Output 1 0 1 1

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1-305

Sequential System Design

Decide on type of flip-flop Lets try a D-type flip-flop
Present State 1 1 0 0 Input 0 1 0 1 Next State 1 0 1 1 Output 1 0 1 1

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CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

1-306

Sequential System Design

Decide on type of flip-flop Lets try a D-type flip-flop Derive and minimize switching equations for FF inputs Din=(QI) And (as necessary) outputs
Present State 1 1 0 0 Input 0 1 0 1 Next State 1 0 1 1 Output 1 0 1 1

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CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

1-307

Sequential System Design

Decide on type of flip-flop Lets try a D-type flip-flop Derive and minimize switching equations for FF inputs Din=(QI) And (as necessary) outputs Init In
S D Q Q
Present State 1 1 0 0 Input 0 1 0 1 Next State 1 0 1 1 Output 1 0 1 1

1-even

Clock

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CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

1-308

Sequential System Design

Verify operation of design Init In
D Q Q S
Present State 1 1 0 Input 0 1 0 1 Next State 1 0 1 1 Output 1 0 1 1

1-even

Clock

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CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

1-309

Sequential System Design

Verify operation of design Init In
D Q Q S
Present State 1 1 0 Input 0 1 0 1 (QI) 0 1 0 0 (QI) 1 0 1 1 Next State 1 0 1 1 Next State 1 0 1 1 Output 1 0 1 1 Output 1 0 1 1

1-even
Present State 1 1 0 Input 0 1 0 1

Clock

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CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

1-310

Sequential System Design

Verify operation of design Init In
D Q Q S
Present State 1 1 0 Input 0 1 0 1 (QI) 0 1 0 0 (QI) 1 0 1 1 Next State 1 0 1 1 Next State 1 0 1 1 Output 1 0 1 1 Output 1 0 1 1

1-even
Present State 1 1 0 Input 0 1 0 1

Clock Clock In Din 1-even 0 0 1 2 3 4 0 0 1

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CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

1-311

Homework 8 due in Class 10

No homework

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CpE358/CS381 Switching Theory and Logical Design Summer-1 2004

Copyright 2004 Stevens Institute of Technology All rights reserved

1-312