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EC1401VLSIDesign

QuestionandAnswers Preparedby N.SHANMUGASUNDARAMAssistantProfessor DepartmentofECEMahendraEnggCollegeNamakkalDt.637503.

MahendraEngineeringCollegeEC1401VLSIDesign

EC1401VLSIDesign2MarksQuestionandAnswers UnitI 1.WhatisIntrinsicandExtrinsicSemiconductor? ThepureSiliconisknownasIntrinsicSemiconductor. WhenimpurityisaddedwithpureSilicon,itselectricalpropertiesarevaried.Thisisknownas ExtrinsicSemiconductor. 2.WhatisCMOSTechnology? The fabrication of an IC using CMOS transistors is known as CMOS Technology. CMOS transistor is nothing but an inverter, made up of an nMOS and pMOS transistorconnected in series. 3.GivetheadvantagesofCMOSIC? Sizeisless HighSpeed LessPowerDissipation 4.WhatarefourgenerationsofIntegrationCircuits? SSI(SmallScaleIntegration) MSI(MediumScaleIntegration) LSI(LargeScaleIntegration) VLSI(VeryLargeScaleIntegration) 5.GivethevarietyofIntegratedCircuits? MoreSpecializedCircuits ApplicationSpecificIntegratedCircuits(ASICs) SystemsOnChips 6.WhyNMOStechnologyispreferredmorethanPMOStechnology? NchanneltransistorshavegreaterswitchingspeedwhencomparedtoPMOStransistors. Hence,NMOSispreferredthanPMOS. 7.WhatarethedifferentMOSlayers? ndiffusion pdiffusion Polysilicon Metal 1

NSS/ECE

MahendraEngineeringCollegeEC1401VLSIDesign

8.WhatarethedifferentlayersinMOStransistor? ThelayersareSubstrate,diffusedDrain&Source,Insulator(SiO
2

)&Gate. 9.WhatarethedifferentoperatingregionsforanMOStransistor? CutoffRegion NonSaturated(Linear)Region SaturatedRegion 10.WhatisEnhancementmodetransistor? ThedevicethatisnormallycutoffwithzerogatebiasiscalledEnhancementmodetransistor. 11.WhatisDepletionmodedevice? TheDevicethatconductswithzerogatebiasiscalledDepletionmodedevice. 12.Whenthechannelissaidtobepinchedoff? IfalargeV
ds

isapplied,thisvoltagewilldepletetheinversionlayer.ThisVoltageeffectively pinchesoffthechannelnearthedrain. 13.WhatarethestepsinvolvedinmanufacturingofIC? SiliconwaferPreparation EpitaxialGrowth Oxidation Photolithography Diffusion IonImplantation Isolationtechnique Metallization Assemblyprocessing&Packaging 2 NSS/ECE

MahendraEngineeringCollegeEC1401VLSIDesign

14.WhatismeantbyEpitaxy? Epitaxymeansarrangingatomsinsinglecrystalfashionuponasinglecrystalsubstrate. 15.Whataretheprocessesinvolvedinphotolithography? (1)Maskingprocess(2)Photoetchingprocess. Theseareimportantprocessesinvolvedinphotolithography. 16.WhatisthepurposeofmaskinginfabricationofIC? MaskingisusedtoidentifythelocationinwhichIonImplantationshouldnottakeplace. 17.Whatlirethematerialsusedformasking? Photoresist,Si02,SiN,PolySilicon. 18.WhatarethetypesofPhotoetching? Wetetchinganddryetchingarethetypesofphotoetching. 19.Whatisdiffusionprocess?Whataredopingimpurities? DiffusionisaprocessinwhichimpuritiesarediffusedintotheSiliconchipat1000 C temperature.B
2

0
3

andP
2

0
5

areusedasimpuritiesused. 20.WhatisIonImplantationprocess? ItisprocessinwhichtheSimaterialisdopedwithanimpuritybymakingtheaccelerated impurityatomstostriketheSilayerathightemperature. 21.WhatarethevariousSiliconwaferPreparation? Crystalgrowth&doping Ingottrimming&grinding Ingotslicing Waferpolishing&etching Wafercleaning. 22.Whatarethedifferenttypesofoxidation?

ThetwotypesofoxidationareDry&WetOxidation. 3 NSS/ECE

MahendraEngineeringCollegeEC1401VLSIDesign

23.WhatisIsolation? Itisaprocessusedtoprovideelectricalisolationbetweendifferentcomponentsand interconnections. 24.GivethedifferenttypesofCMOSprocess? pwellprocess nwellprocess twintubprocess SOIprocess 25.WhatisChannelstopImplantation? In nwell fabrication, nwell is protected with the resist material. (Because, it should not be affected during Boron implantation). Then Boron is implanted except nwell. The above said process is done using photo resist mask. This type of implantation is known as Channelstop implantation. 26.WhatisLOCOS? LOCOSmeanLocalOxidationofSilicon.Thisisonetypeofoxideconstruction. 27.WhatisSWAMI? SWAMImeansSideWallMaskedIsolation.Itisusedtoreducebird'sbeakeffect. 28.WhatisLDD? LDDmeansLightlyDopedDrainStructures.Itisusedforimplantationofnregioninnwell process. 29.WhatisTwintubprocess?Whyitiscalledso? Twintub process is one of the CMOS technologies. Two wells (the other name for well isTub) are created in this process. So, because of these two tubs, this processis known asTwintub process. 30.Whatarethestepsinvolvedintwintubprocess? TubFormation ThinoxideConstruction Source&DrainImplantation Contactcutdefinition Metallization. 4 NSS/ECE

MahendraEngineeringCollegeEC1401VLSIDesign

31.WhatarethespecialfeaturesofTwintubprocess? InTwintubprocess,Thresholdvoltage,bodyeffectsofnandpdevicesareindependently optimized. 32.WhataretheadvantagesofTwintubprocess? AdvantagesofTwintubprocessare(1)Separateoptimizedwellsareavailable.(2)Balanced performanceisobtainedfornandptransistors. 33.WhatisSOI?WhatisthematerialusedasInsulator? SOImeansSilicononInsulator.Inthisprocess,aSiliconbasedtransistorisbuiltonan insulatingmateriallikeSapphireorSiO


2

. 34.WhataretheadvantagesanddisadvantagesofSOIprocess? AdvantagesofSOIprocess:1.Thereisnowellformationinthisprocess.2.Thereisno fieldInversionproblem.3.Thereisnobodyeffectproblem. DisadvantagesofSOIprocess:1.Itisverydifficulttoprotectinputsinthisprocess.2.Device gainislow.3.Thecouplingcapacitancebetweenwiresalwaysexists. 35.WhataretheadvantagesofCMOSprocess? LowInputImpedance LowdelaySensitivitytoload. 36.WhatarethevariousetchingprocessesusedinSOIprocess? VariousetchingprocessesusedinSOIare, 5 NSS/ECE (A.FULLYANISTROPHICETCHING)

MahendraEngineeringCollegeEC1401VLSIDesign

(C.ISOTROPHICETCHING) 37.WhatisBiCMOSTechnology? ItisthecombinationofBipolartechnology&CMOStechnology. 38.WhatarethebasicprocessingstepsinvolvedinBiCMOSprocess? AdditionalmasksdefiningPbaseregion NCollectorarea BuriedSubcollector(SCCD) ProcessingstepsinCMOSprocess 39.Whatismeantbyinterconnect?Whatarethetypesareofinterconnect? InterconnectmeansconnectionbetweenvariouscomponentsinanIC. TypesofInterconnect:1.MetalInterconnect2.PolySiliconInterconnect3.LocalInterconnect. 40.WhatisSilicide? ThecombinationofSiliconandtantaleumisknownasSilicide.Itisusedasgatematerialin PolysiliconInterconnect. 6 NSS/ECE (B.PREFERENTIALETCHING)

MahendraEngineeringCollegeEC1401VLSIDesign

41.WhatisPolycide? ThecombinationofSilicideandPolysiliconisknownasPolycide.Itisusedasgatematerial. 42.WhatisStickdiagram? Thediagramwhichconveysthelayerinformationthroughtheuseofvariouscoloursisknownas Stickdiagram.Itisalsothecartoonofachiplayout. 43.WhataretheusesofStickdiagram? Itcanbedrawnmucheasierandfasterthanacomplexlayout. Theseareespeciallyimportanttoolsforlayoutbuiltfromlargecells. 44.Givethevariouscolorcodingusedinstickdiagram? Greenndiffusion Redpolysilicon Bluemetal Yellowimplant Blackcontactareas. 45.ComparebetweenCMOSandbipolartechnologies. CMOSTechnologyBipolarTechnology Lowstaticpowerdissipation Highinputimpedance(lowdrivecurrent) Scalablethresholdvoltage Highnoisemargin Highpackingdensity Highdelaysensitivitytoload(fanoutlimitations) Lowoutputdrivecurrent Lowgm(gmVin) Bidirectionalcapability Anearidealswitchingdevice 7 NSS/ECEHighpowerdissipation Lowinputimpedance(highdrivecurrent) Lowvoltageswinglogic Lowpackingdensity Lowdelaysensitivitytoload

Highoutputdrivecurrent Highgm(gmaeVin) Highftatlowcurrent Essentiallyunidirectional 46.DefineThresholdvoltageinCMOS? The Threshold voltage, VT for a MOS transistor can be defined as the voltage applied between the gate and the source of the MOS transistor below which the drain to source current, IDS effectivelydropstozero.

MahendraEngineeringCollegeEC1401VLSIDesign

47.WhatisBodyeffect? ThethresholdvoltageV
Th

is not a constant with respect to the voltage difference between the substrate and the source of MOS transistor. This effect is called substratebias effect or body effect. 48.WhatisChannellengthmodulation? The current between drain and source terminals is constant and independent of the applied voltage over the terminals. This is not entirely correct. The effective length of the conductive channelisactuallymodulatedbytheappliedV
DS

,increasingV
DS

causesthedepletionregionatthedrainjunctiontogrow,reducingthelengthof theeffectivechannel. 49.WhatisLatchup? Latchupisaconditioninwhichtheparasiticcomponentsgiverisetotheestablishmentoflow resistanceconductingpathsbetweenV


DD

andV
SS

with disastrous results. Carefulcontrolduringfabricationisnecessarytoavoidthisproblem. 50.Whatisdemarcationline? Demarcationlineisanimaginarylineusedinstickdiagram,toseparatepMOSandnMOS transistors. AllpMOStransistorsareplacedabovedemarcationlineandnMOSbelowthedemarcationline 51.WhatarethetwotypesofLayoutdesignrules? Lambdadesignrulesandmicronrulesaremajortypesoflayoutdesignrules. 52.WhatisLayoutdesignrule? TherulesfollowedtopreparethephotomaskareknownasLayoutdesignrules. 8 NSS/ECE

MahendraEngineeringCollegeEC1401VLSIDesign

53.WhatareLVSandDRLtools? LVSmeansLayoutVersusSchematic.Itcheckslayoutagainstschematicdiagram.Itisvery importanttoverifylayout. DRCmeansDesignRuleChecker.Thistoolcheckseveryoccurrenceofdesignruleliston layout.Width,spacingofeverymetallineinlayoutarecheckedwiththistool. 54.Whatisinstance?Whatisinstancing? Toconstructbigcomplexcircuit,thebasiccells(smallcells)canbecopied.Thisprocessis knownasInstancing.ThecellwhichiscopiedisknownasInstance. 55.Whatisflatcell? Thecellwhichisindependentandnotrelatedtootherobjectsisknownasflatcell. 56.Whatarethecellsavailableinprimitivelibrary? NOT,NAND,NOR,arethebasiccellsinprimitivelibrary. 57.WhatisDesignHierarchy? When we want to design AND4 input gate, we use NAND2 and NOR2 basic blocks. By combining NAND2 and NOR2, we create AND4 input gate. This is known as Design Hierarchy. 9 NSS/ECE