Vhdl semaforo

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;

entity semaforo is Port ( clk : in STD_LOGIC; luces : out STD_LOGIC_VECTOR (11 downto 0)); end semaforo;

architecture Behavioral of semaforo is type estados is (s0,s1,s2,s3,s4,s5,s6,s7); signal q,qmas: estados; signal cuenta: STD_LOGIC_VECTOR(6 downto 0); constant verderojo: STD_LOGIC_VECTOR(6 downto 0):= "1111000"; constant amarillo: STD_LOGIC_VECTOR(6 downto 0):= "0001111";

begin process(clk,q,cuenta) begin

if (clk'event and clk= '1') then

q <= qmas; end if;

case q is

when s0 =>

if cuenta < verderojo then qmas <= s0; cuenta <= cuenta + 1; else qmas <= s1; cuenta <= "0000000"; end if;

when s1 =>

if cuenta < amarillo then qmas <= s1; cuenta <= cuenta + 1;

else qmas <= s2; cuenta <= "0000000"; end if;

when s2 => qmas <= s3;

when s3 =>

if cuenta < amarillo then qmas <= s3; cuenta <= cuenta + 1; else qmas <= s4; cuenta <= "0000000"; end if;

when s4 =>

if cuenta < verderojo then qmas <= s4; cuenta <= cuenta + 1; else qmas <= s5; cuenta <= "0000000"; end if;

when s5 =>

if cuenta < amarillo then qmas <= s5; cuenta <= cuenta + 1; else qmas <= s6; cuenta <= "0000000"; end if;

when s6 =>

qmas <= s7;

when s7 =>

if cuenta < amarillo then qmas <= s7; cuenta <= cuenta + 1; else qmas <= s0; cuenta <= "0000000"; end if; when others => qmas <= s0;

end case; end process;

Funcion_de_salida: process(q) begin

case q is

when s0 => luces <= "100100001001";

when s1 => luces <= "010010001001"; when s2 => luces <= "001001001001"; when s3 => luces <= "001001011011"; when s4 => luces <= "001001100100"; when s5 => luces <= "001001010010"; when s6 => luces <= "001001001001"; when s7 => luces <= "011011001001";

end case; end process;

end Behavioral;

vhdl alu library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;

entity alu is Port ( A : in STD_LOGIC_VECTOR (4 downto 0); B : in STD_LOGIC_VECTOR (4 downto 0); G: in STD_LOGIC_VECTOR(2 downto 0); z : out STD_LOGIC_VECTOR (4 downto 0)); end alu;

architecture Behavioral of alu is begin process(G,A,B)

begin

case G is

when "000" => z <= "00000"; when "001" => z <= A + B; when "010" => z <= B - A; when "011" => z <= A - B; when "100" => z <= A and B; when "101" => z <= A or B; when "110" => z <= A xor B; when "111" => z <= "11111"; when others => z <= "00000"; end case; end process;

end Behavioral;

Vhdl para secuenciadores (maquina)

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;

entity maquinas is Port ( clk : in STD_LOGIC; y : in STD_LOGIC; m : out STD_LOGIC_VECTOR (3 downto 0)); end maquinas;

architecture Behavioral of maquinas is

type estados is (s0,s1,s2,s3,s4,s5,s6); signal q,qmas : estados; signal cuenta: STD_LOGIC_VECTOR(5 downto 0); constant sesenta: STD_LOGIC_VECTOR(5 downto 0):="111100"; constant treinta: STD_LOGIC_VECTOR(5 downto 0):="011110";

begin process (clk,y,cuenta,q) begin

if (clk'event and clk = '1') then q <= qmas;

end if;

case q is

when S0 => if cuenta < sesenta then qmas <= s0; cuenta <= cuenta + 1; else if y = '1' then qmas <= s1; cuenta <= "000000"; else qmas <= s4; cuenta <= "000000"; end if; end if; when S1 => if cuenta < sesenta then qmas <= s1; cuenta <= cuenta + 1; else if y = '1' then qmas <= s2; cuenta <= "000000"; else qmas <= s0; cuenta <= "000000"; end if;

end if;

when S2 => if cuenta < sesenta then qmas <= s2; cuenta <= cuenta + 1; else if y = '1' then qmas <= s3; cuenta <= "000000"; else qmas <= s0; cuenta <= "000000"; end if; end if;

when S3 => if cuenta < sesenta then qmas <= s3; cuenta <= cuenta + 1; else if y = '1' then qmas <= s0; cuenta <= "000000"; else qmas <= s0; cuenta <= "000000"; end if; end if;

when S4 => if cuenta < treinta then qmas <= s4; cuenta <= cuenta + 1; else if y = '1' then qmas <= s0; cuenta <= "000000"; else qmas <= s5; cuenta <= "000000"; end if; end if;

when S5 => if cuenta < treinta then qmas <= s5; cuenta <= cuenta + 1; else if y = '1' then qmas <= s0; cuenta <= "000000"; else qmas <= s6; cuenta <= "000000"; end if; end if;

when S6 => if cuenta < treinta then qmas <= s6; cuenta <= cuenta + 1; else if y = '1' then qmas <= s0; cuenta <= "000000"; else qmas <= s0; cuenta <= "000000"; end if; end if;

end case; end process;

FUNCION_DE_SALIDA: process (q) begin case (q) is when S0 => m <= "0000"; when s1 => m <= "1000"; when s2 =>

m <= "1100"; when S3 => m <= "1110"; when s4 => m <= "0100"; when s5 => m <= "0110"; when s6 => m <= "0111"; when others => m <= "0000"; end case; end process;

end Behavioral;

Vhdl para bcd library IEEE; use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code.

--library UNISIM; --use UNISIM.VComponents.all;

entity bcd is Port ( clk : in STD_LOGIC; S : in STD_LOGIC; contador : out STD_LOGIC_VECTOR (3 downto 0)); end bcd;

architecture Behavioral of bcd is type estados is (s0,s1,s2,s3,s4,s5,s6,s7,s8,s9); signal q,qmas :estados;

begin process(clk) begin if (clk'event and clk = '1') then q <= qmas;

end if; end process;

process(S,q) begin case (q) is

when s0 => if S = '1' then

qmas <= s1; else qmas <= s9; end if;

when s1 => if S = '1' then qmas <= s2; else qmas <= s0; end if;

when s2 => if S = '1' then qmas <= s3; else qmas <= s1; end if;

when s3 => if S = '1' then qmas <= s4; else qmas <= s2; end if;

when s4 => if S = '1' then qmas <= s5;

else qmas <= s3; end if;

when s5 => if S = '1' then qmas <= s6; else qmas <= s4; end if;

when s6 => if S = '1' then qmas <= s7; else qmas <= s5; end if;

when s7 => if S = '1' then qmas <= s8; else qmas <= s6; end if;

when s8 => if S = '1' then qmas <= s9; else

qmas <= s7; end if;

when s9 => if S = '1' then qmas <= s0; else qmas <= s8; end if;

when others =>

qmas <= s0;

end case; end process;

process(q) begin

case q is

when s0 => contador <= "0000"; when s1 => contador <= "0001"; when s2 => contador <= "0010"; when s3 =>

contador <= "0011"; when s4 => contador <= "0100"; when s5 => contador <= "0101"; when s6 => contador <= "0110"; when s7 => contador <= "0111"; when s8 => contador <= "1000"; when s9 => contador <= "1001";

end case; end process;

end Behavioral;