DATASHEET

INCISIVE UNIFIED SIMULATOR

The Incisive Unified Simulator is the core of the Cadence Incisive functional verification platform. Its also the first simulator to natively support Verilog, SystemVerilog, VHDL, SystemC, SystemC Verification Library, PSL, SVA, and OVL. With dynamic assertion checking, full transaction-level support, HDL analysis, unified test generation, and optional Acceleration-on-Demand, the Incisive platform delivers the fastest, most efficient verification for nanometer-scale ICs.

IP Algorithm development Analog/ Mixed-signal Acceleration/ Emulation Accelerationon-Demand Unified test generation HDL analysis Assertions Comprehensive coverage Transaction support Debug/analysis Simulation Third-party EDA support

Incisive verification IP CoWare SPW Incisive AMS Incisive Palladium systems Incisive XLD Incisive Unified Simulator

INCISIVE FUNCTIONAL VERIFICATION PLATFORM

The functional verification of nanometer-scale ICs requires speed and efficiency. Yet today's fragmented methodologies make it impossible to optimize either. Each verification stage has its own methodology, tools, models, and user interface. Engineers must re-create almost everything at every stage. The Incisive verfication platform is the world's first functional verification platform that supports a unified methodology to deliver the fastest, most efficient verification in the industry.

NC-SC Simulator NC-VHDL Simulator NCVerilog Simulator

Figure 1: The Incisive Unified Simulator is the core of the Incisive platform

INCISIVE UNIFIED SIMULATOR

The Incisive Unified Simulator provides everything you need to verify todays toughest designs. Its single-kernel architecture natively supports Verilog, SystemVerilog, VHDL, SystemC, SystemC Verification (SCV) Library, PSL, SVA, and OVL. The Incisive platform includes a comprehensive verification environment including dynamic assertion checking, full transaction-level support, and unified test generation. You can extend the functionality of the Incisive simulator with other elements from the Incisive platform, including Acceleration-on-Demand, analog/mixed-signal/RF verification, and algorithm development and verification.

Unified Simulator produces efficient machine code for high-speed execution. Linked-list scheduling of the resulting data structures pre-processes signal actions while maximizing effectiveness of modern caching algorithms available in the leading compute platforms. UNIFIED SIMULATION AND DEBUG ENVIRONMENT A unified simulation and debug environment allows the Incisive Unified Simulator to manage multiple simulation runs easily and analyze your design and testbench at any point in the verification process regardless of the composition. Throughout the design and verification flow, the Incisive simulator provides hardware analysis checks, source browsing,

transaction/waveform viewing, and code/transaction/assertion coverage analysis. Application programming interfaces based on industry standards are available at all levels to enable user-defined checks and analysis. All engineers on a project learn one and only one environment. INTEGRATED TRANSACTION ENVIRONMENT The Incisive Unified Simulator includes an integrated transaction environment that supports transaction specification, simulation, recording, aggregation, analysis, and debug. Raising the level of abstraction from the signal level (enable, r/w, address, and data) to the transaction level (data events such as read and write) speeds verification. Transaction-level models and testbenches

BENEFITS
Offers the ultimate simulation-based speed and efficiency Increases RTL performance by 100 times with native transaction-level simulation and optional Acceleration-on-Demand Reduces testbench development up to 50% with transaction-level support, unified test generation, and verification component re-use Shortens verification time, finds bugs faster, and eliminates exhaustive simulation runs with dynamic assertion checking Decreases debug time up to 25% through unified transaction/signal viewing, HDL analysis capability, and unified debug environment for all languages

Analog HDL

Verilog SystemVerilog

VHDL

SystemC C, C++

PSL, SVA, OVL

Mixed-level

Multilanguage

Mixed-signal

Interleaved native-compiled architecture

Figure 2: Incisive single-kernel native-compiled architecture

FEATURES
HETEROGENEOUS SINGLE-KERNEL ARCHITECTURE The Incisive single-kernel architecture enables unified simulation through behavioral, transaction, registertransfer, and gate-levels of abstraction. It utilizes a unique interleaved nativecompiled architecture that supports Verilog, SystemVerilog, VHDL, SystemC, SCV Library, PSL, SVA, and OVL. Design and testbench models can be interleaved in any language and any level of abstraction without the performance and integration overhead caused by co-simulation. The Incisive

Figure 3: Incisive simulation integrates transaction/waveform debugging and simulation analysis software

take a fraction of the time to write as equivalent RTL and typically simulate 100 times faster. Debugging modules at the transaction level increase efficiency as well. DYNAMIC ASSERTION SUPPORT The Incisive functional verification platform delivers simulation-based dynamic assertion-checking technology that operates within the block-level HDL flow, familiar to design and verification teams. Assertion-based verification is a fast-growing technique to shorten verification time. NATIVE PSL, SVA, AND OVL SUPPORT The Incisive single-kernel architecture provides native PSL, SVA, and OVL support. Also included in the Incisive Assertion Library (IAL), which allows users to quickly insert common assertions into their designs. Assertions enable design teams to instrument their interfaces and logic with monitors that automatically detect specified error conditions or critical coverage situations. The resulting increase in observability lets designers detect more bugs, detects bugs nearer their source, ensure all interface activity is legal, identify coverage holes, and more. Native kernel support means that assertions have minimal impact on runtime and capacity (typically 1-5%). This ensures the appropriate assertions are always active so that bugs will not slip by unnoticed. OPTIONAL ACCELERATION-ON-DEMAND The Incisive Unified Simulator is upgradeable to Incisive XLD, the industrys only product that allows users to choose simulation, acceleration, or in-circuit emulation at runtime. Acceleration typically provides 100 times the performance over simulation, enabling teams to run four days worth of simulation during their lunch hour or more than a months worth of simulation overnight. In-circuit emulation replaces the testbench with real-world stimulus and software. This hardware/ software co-verification mode runs at up to 10,000 times the simulation performance. One investment delivers all three runtime modes for the ultimate in verification speed and flexibility.

HDL ANALYSIS Incisive HDL analysis catches design bugs and coding surprises early in the design cycle. HDL analysis performs over 500 checks to flag syntactic, semantic, and functional errors. A flow that includes HDL analysis before simulation will check the code for race conditions, clock domain synchronization problems, semantic ambiguity issues, and synthesizability traps. Incisive HDL analysis comes standard with rules that check compliance with the Reuse Methodology Manual and can be expanded to include corporate style guidelines. Its powerful rule definition GUI and graphical analysis tools help engineers write working code the first time. COMPREHENSIVE COVERAGE Incisive comprehensive coverage allows engineers to create first-pass silicon by ensuring that all functionality is fully tested. Comprehensive coverage adds a critical dimension to coverage information by enhancing code coverage with functional coverage. The Incisive Unified Simulators integrated code coverage ensures that a test exercises all the code in a design; while functional coverage shows when tests have fully exercised a test specification. OPTIONAL MIXED-SIGNAL AND ALGORITHM DESIGN The Incisive Unified Simulator is extendable to mixed-signal and algorithm design domains, with a single-kernel architecture that ensures maximum speed and efficiency across domains. Incisive AMS adds analog/ mixed-signal verification to the Incisive environment, ensuring that critical on-chip analog circuitry works correctly in the context of digital logic. Incisive SPW signal processing worksystem provides efficient development, implementation, and verification of algorithmic design.

Verilog (IEEE 1364-1995, majority of IEEE 1364-2001 extensions) SystemVerilog (IEEE-1800) VHDL (IEEE 1076-1987, IEEE 10761993, IEEE 1076.4-2000 (VITAL 2000)) SystemC (OSCI SystemC v2.01) SystemC Verification Library (OSCI SCV 1.0) Compile Native compilation technology goes directly to host processor machine code for maximum performance Intelligent incremental compile to reduce compile times Capacity Typical 10M gate equivalents in 32-bit OS (4GB addressable) Typical 100M gate equivalents in 64-bit OS Server farm Platform computing LSF Sun Microsystems gridware PSL, SVA, (IEEE - 1800) ASSERTION SUPPORT Supports PSL and SVA, the standard assertion languages from Accellera Handles Verilog, VHDL, and SystemC versions of PSL Supports OVL, the Open Verification Library standard Includes the Incisive Assertion Library (IAL) Common compile and elaboration mechanism with rest of Incisive platform Common user interface with rest of Incisive platform Dynamic assertion evaluation Natively compiled with HDL for highest performance Assertions can be embedded in the HDL or in separate file(s) Recorded as transactions for direct display in waveform window PSL and SVA assertions treated as first-class simulation objects for easy debugging HDL ANALYSIS

SPECIFICATIONS
SIMULATION Single-kernel simulation engine 500+ checks to lint and analyze code: Synthesizability Race conditions

 Code reusability Clock domain synchronization FSM coding Acceleration policy checks Gate-level netlist analysis for any DFT errors introduced during synthesis Verilog, SystemVerilog, VHDL, and mixed-language support Powerful customization capability using VPI/VHPI Graphical interface to sort, filter, and analyze messages with source code RESULT ANALYSIS Debug and GUI Waveform window Register window Unified transaction/signal viewing Schematic tracer Expression calculator Signal flow browser Source viewer Error browser Tcl/Tk scripting for customizable displays Log signal and transaction data to SST database Performance analysis software outlines areas of code where most simulation time is spent Code coverage Supports Verilog, SystemVerilog, VHDL, and mixed-language designs Automatic finite state machine extraction Coverage attributes supported include blocks, paths, expressions, variables, gates, FSM (states, sequences), and toggle Coverage re-use Rank order coverage contributions Bit-wise expression scoring Functional coverage analysis Supports Verilog, System Verilog, VHDL, SystemC, SCV, PSL, SVA, and OVL Logs data to SST2 database Tcl/Tk scripting for custom analysis THIRD-PARTY SUPPORT ASIC libraries

More than 30 ASIC vendors have certified their libraries for the Incisive platform More than 150 unique libraries Models Third-party model support through the Cadence verification IP partner program Software Third-party software support through the Cadence Connections program with more than 30 verification company partners INTERFACES PLI (IEEE 1364) VPI (PLI 2.0, IEEE 1364) OMI (IEEE 1499) VHPI Compiled SDF PLATFORMS Sun Solaris HP-UX Linux

Supports simulation acceleration and in-circuit emulation INCISIVE PALLADIUM FAMILY OF ACCELERATORS/EMULATORS Simulation acceleration and in-circuit emulation in one system Provides up to 100x-10,000x RTL performance Run-time performance with up to 750KHz speed Compiles up to 30M gates per hour on a single workstation Expandable to 256M gates Allows up to 32 simultaneous users Leader in microprocessor and IP support

CADENCE SERVICES AND SUPPORT

Customer-focused solutions that increase ROI, reduce risk, and achieve your design goals faster Collaborative approach and design infrastructure virtual teaming Proven methodology and flow tuned to your design environment Design and EDA implementation expertise Product and flow training to fit your needs and preferred learning style More than 80 instructor-led courses certified instructors, realworld experience More than 25 Internet Learning Series (iLS) online courses Cadence customer support that keeps your design team productive Cadence applications engineers provide technical assistance SourceLink online support gives you access to software updates, technical documentation, and more 24 hours a day, 7 days a week

INCISIVE PLATFORM PRODUCT LINE-UP

INCISIVE UNIFIED SIMULATOR Unified simulator with heterogeneous single-kernel architecture Native Verilog, SystemVerilog, VHDL, and SystemC support Native SystemC Verification Library PSL, SVA, and OVL support Fast, unified test generation Acceleration policy checks and HDL analysis Unified simulation and debug environment Unified kernel supports analog/ mixed-signal and algorithm design INCISIVE XLD TEAM VERIFICATION Provides 10 Incisive Unified Simulator licenses Adds 1M gates Acceleration-on-Demand Enables local or remote access Increases capacity with Cadence EDA card

FOR MORE INFORMATION

Email us at info@cadence.com or visit www.cadence.com.

2005 Cadence Design Systems, Inc. All rights reserved. Cadence, the Cadence logo, Connections, NC-Verilog, SourceLink, and Verilog are registered trademarks, and Incisive is a trademark of Cadence Design Systems, Inc. OSCI and SystemC are registered trademarks of Open SystemC Initiative, Inc. in the United States and other countries and are used with permission. All others are properties of their respective holders. 5418C 04/05