EXP NO:2 DATE: CMOS INVERTER LAYOUT DESIGN

AIM: To design cmos inverter layout and from schematic entry to post layout simulation using mentor graphics EDA tools.

TOOLS REQUIRED: Mentor Graphics.

CMOS INVERTER THEORY: An inverter circuit outputs a voltage representing the opposite logic level to its input.inverters can be constructed using a single nmos transistor or a single pmos transistor coupled with a resistor.since this resistive drain approach uses only a single type of transistor it can be fabricated at low cost.However because current flows through the resistor in one of the two states ,the resistive drain configuration is disadvantaged for power consumption and processing speed.

CMOS inverter consists of a pull-up transistor and a pull-down transistor. Pull-up transistor is made up of p-type transistor and pull-down is of n-type. These pull-down and pull-up transistors are connected in series. When we are applying a low voltage (0v) n-type transistor will be off and p-type transistor will be conducting. Thus we will have vdd as the output (5V). When the input voltage is high the n-type transistor will conduct and p-type transistor will be in off state. Now we will get 0V as the output.

CMOS INVERTER SCHEMATIC DIAGRAM:

CMOS INVERTER SIMULATION:

SCHEMATIC DIAGRAM OF CMOS INVERTER: For drawing a schematic diagram enter into pyxis schematic window and open a new schematic file. Pick and place 4-pin nmos , 4-pin pmos ,vdd and gnd from the library. Wire all the compound and connect input output ports. After check and save generate a symbol for the schematic and again apply check and save. Close all the windows. For drawing a schematic diagram enter into pyxis schematic window and open a new schematic file.

1.In the schematic_edit palette, select Library. Click on Device Lib to place the transistors - an
NMOS(4-pin) and a PMOS(4-pin) 2.Click on Generic Lib to place Portin, Portout, VDD. 3. In the schematic_edit palette, select WIRE (or press F3). For adding a wire between two points click once at the starting point and at all intermediate points to define the net route and double click at the end point to complete the routing. D, and Ground. 4.Change the instance name of the component 5.To change the reference number (INST), select the component, click right mouse button, and then select Properties > Modify Multiple. In the box of Instance, change the ASIM_MODEL, INST, L, and W values . To change the reference number automatically highlight all components, click the right mouse button, Instance > Alter Click on Check & Save in the schematic edit palette 6.After schematic is completed, want to create a block symbol to represent this circuit. This symbol can be used in other schematics to perform the same function as this circuit. Open add -> Generate Symbol.Again apply check and save. Close all the windows.

SIMULATION: The electrical performance and the functionality of the circuit must be verified using a Simulation tool. The simulation phase also serves in detecting possible design errors that may have been created during the schematic entry step. Open a new file and add the symbol which

is generated previously. From the library add pattern, dc source, vdd and gnd. Place and wire the input and output ports. Enter into the simulation mode. Include the rule file and go to analysis. Select transient analysis and set the transient analysis times. In probes add the input output ports for analysis. Select run eldo and view the waves.

CMOS INVERTER LAYOUT DIAGRAM:

DRC FOR CMOS INVERTER:

LAYOUT OF CMOS INVERTER: The creation of the mask layout is one of the most important steps in the full-custom (bottom-up) design flow. This is where the designer describes the detailed geometries and the relative positioning of each mask layer to be used in actual fabrication, using a Layout Editor. Physical layout design is very tightly linked to overall circuit performance (area, speed and power dissipation) since the physical structure determines the transconductances of the transistors, the parasitic capacitances and resistances, and obviously, the silicon area which is used to realize a certain function. On the other hand, the detailed mask layout of logic gates requires a very intensive and time-consuming design effort. The physical design of cmos logic gates is an iterative process which starts with the circuit topology and the initial sizing of the transistors. Enter into the IC station and open the simulation file of the inverter in new layout file. Both schematic and layout window will open. Select metal1. Instantiate nmos ,pmos ,input and output ports, vdd and gnd. Draw polysilicon to join the gates. Draw a 5*5 polysilicon and a 2*2 polycontact . Place polycontact in side the 5*5 polysilicon and attach to the gates. Use metal for wire the input , output , vdd and gnd. Place the p-well and n-well contacts and save the layout.

DESIGN RULE CHECK: ASIC designers perform two major checks before fabrication. The first check is a designrule check ( DRC ) to ensure that nothing has gone wrong in the process of assembling the logic cells and routing. For the DRC ,from the tools go to calibre and select DRC. Select the rule file and run DRC. The checking result will be the layout passed all checking. If error exists check the design rule violations. And repeat DRC.

The created mask layout must conform to a complex set of design rules, in order to ensure a lower probability of fabrication defects. A tool built into the Layout Editor, called Design Rule Checker, is used to detect any design rule violations during and after the mask layout design. The designer must perform DRC, and make sure that all errors are eventually removed from the mask layout, before the final design is saved. Layout is constructed based on lambda based design rule and the technology .DRC is used to check the layout whether that any violation have occurred with respect to rule file.

CMOS INVERTER LVS CHECKING:

CMOS INVERTER PEX RESULT:

LVS CHECKING:

Layout versus schematic ( LVS ) check to ensure that what is about to be committed to silicon is what is really wanted. After the mask layout design of the circuit is completed, the design should be checked against the schematic circuit description created earlier. By comparing the original network with the one extracted from the mask layout the designer can check that the two networks are indeed equivalent. The LVS step provides an additional level of confidence for the integrity of the design, and ensures that the mask layout is a correct realization of the intended circuit topology. Note that the LVS check only guarantees a topological match. In other words, a successful LVS will not guarantee that the extracted circuit will actually satisfy the performance requirements. Any errors that may show up during LVS such as unintended connections between transistors, or missing connections/devices, etc should be corrected in the mask layout - before proceeding to post-layout simulation.

An electrical schematic is extracted from the physical layout and compared to the netlist. This closes a loop between the logical and physical design processes and ensures that both are the same. From file go to GDSII and text on ports. Go to tools and form calibre select LVS. Add the rule file and .spi file for the input. Apply run LVS and check the result.

PARASITIC EXTRACTION AND POST LAYOUT SIMULATION: Parasitic extraction is performed after the mask layout design is completed in order to create a detailed net-list for the simulation tool. The circuit extractor is capable of identifying the individual transistors and their interconnections as well as the parasitic resistances and capacitances that are inevitably present between these layers. The extracted net-list can provide a very accurate estimation of the actual device dimensions and device parasitics that ultimately determine circuit performance. The extracted net-list file and parameters are subsequently used in Layout-versus-Schematic comparison and in detailed transistor-level simulations (post-layout simulation). From calibre select PEX. Select the rule file. In input select the .spi file and in output select the parameters to be analyzed. The run RVE and check the results. Reenter into the simulation mode and view waves and compare the results.

SIMULATION DIAGRAM AFTER PEX:

WAVE FORM:

RESULT: Thus designed cmos inverter layout and from schematic entry to post layout simulation using mentor graphics EDA tools is done.