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NE242 LAB 5 Introduction to CAD using MicroTec Software Report Executive Summary

This lab uses MicroTec software to demonstrate semiconductor device. The first part of the lab is to analyze the conduction band of MOS Capacitance under different conditions such as varying gate voltage, drain voltage, width, and the doping concentration of source. For this lab, semiconductor testing software, called MicroTec, will be used to examine the transistor behaviours. MOSFET consists of a channel, body, source and drain. Electrodes are deposited on the source and drain to control the potentials in the regions.

3. 1 MOS Capacitance and Conduction Band Diagrams

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Conduction band edge (e.V.) at Y = 0.0107068 Conduction band edge (e.V.) at Y = 0.0107068

Conduction band edge (e.V.) at Y = 0.0107068 Conduction band edge (e.V.) at Y = 0.0107068

Conduction band edge (e.V.) at Y = 0.0107068

Conduction band edge (e.V.) at Y = 0.0107068

Question 1: Explain the effect of changing the gate voltage on the conduction band diagram, with reference to MOS capacitance and how the distribution of electrons in the inversion layer changes with changing VG.

-As the gate voltage increases the height of conduction band decreases. Blue is the conduction band when the gate is 0V and next band 0.25V,0.75V,1.25V,1.75V and,2.0V As the gate voltage is increased from 0 to 2, the conduction band edge decreases. We notice the decrease from around 0.6eV to 0.37eV. This can be explained since the gate voltage creates inversion layer. The greater the inversion layer the easier it is to conduct electricity. With more electrons gathering between the drain and the source, the conduction band is decreased. This is shown from the graph above as explained.

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Conduction band edge (e.V.)

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-1. 0. 0.2 0.4 0.6 Distance X (microns) Conduction band edge (e.V.) at Y = 0.0107068 Conduction band edge (e.V.) at Y = 0.0107068 0.8 1.

Question 2: How does the conduction band diagram change when the gate voltage is increased and the drain voltage is 1V? For both VG = 0V, 1V, how will the charge carriers in the inversion layer be affected by the fact that VD is now 1V? Practically, why would such an effect be useful in a transistor?
-The conduction band decreased when the gate voltage is changed from 0V to 1V. We can control the conductance in the inversion layer. Due to positive potential on the drain, conduction band edge is lowered in drain area (0.645m~x~1.2m). Also conduction band edge at the middle has decreased compared to VG = 0V because when VG = 1V is applied, conduction band edge decreases as the question (1). The applied voltage between source and drain creates electric field which causes charge carriers to flow in the direction according to the

electric field. The VD is useful in a transistor since it is the main cause of conduction when the inversion layer is created.

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-1. 0. 0.2 0.4 0.6 Distance X (microns) Conduction band edge (e.V.) at Y = 0.0109598 Conduction band edge (e.V.) at Y = 0.0109625 0.8 1.

Question 3: Examine your conduction band diagram. Why is the voltage dropping linearly in the source/drain regions? What are the values of EC for both cases? Why does changing the relative physical size of the source/drain regions affect EC? What are the consequences of lowering EC? Note: Refer to figure 2 for a description of EC. -What we notice is a shift from the left to the right as the source voltage is increased. This is because the area under the drain increases and this decreases the voltage drop. In result, there is an increase in the conduction band edge. EC of drain width 0.40 um is around 0.23eV and EC of drain width 0.74um is around 0.20eV. Changing the size of the source and drain changes the EC. This is because the carrier concentration changes with the change in the size of an inversion layer. Lowered EC will increase the conductance of the MOS.
The voltage drop across the oxide by the drain terminal decreases with the increase of drain voltage. What we notice is that as the area under the drain increases it decreases the voltage drop, thus resulting in a higher conduction band edge. EC of drain width 0.37um is around 0.23eV while EC of drain width 0.74um is

around 0.2eV. The change in the source and drain size affects EC because the charge carrier concentrations change with the change in the inversion layer size. When you lower the EC it increases the MOS conductance.

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Question 4: Explain any noticeable change in the conduction band diagrams for the three different doping concentrations. (Hint: Think about the factors that affect the resistivity of a material) -There really isnt much change as you can see in the graph. However, if we look carefully we see that lowering doping concentration the conduction band is increased slightly. This is because higher doping means more carriers that lead to lower conduction band in the channel area and a higher band in the source area. If the dopant concentration becomes high the interation between dopand molecules becomes significant.

From the diagram above, the noticeable change is not great. After close analysis, we notice that there is a lowering in the conduction band edge when the doping concentration is increased. There are more carriers with increased doping and this leads to lower conduction band around where the channel is. With lowered conduction band at the channel and higher band at the source, the EC is decreased

3. 2 Examining Transconductance Id Vs Vd
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initial value of contact 3 (VG) = 0.25(green), 0.50, 1, 1.5(blue) Question 5: How/why does changing VG affect the ID vs. VD curve? Think back to your responses from questions one and two when answering this question. -With the VG increase in the graph, clearer linear slopes appear. This is because high gate voltage expands the inversion layer and the bigger it is the more current may flow.

From the above graph we can see that the slope of Id vs. VDS increases as the gate voltage increases. This can be explained since high gate voltage creates bigger inversion layer which allows more current to flow. Higher voltage gate lowers EC which allows higher flow of currents under high voltage g

Id Vs Vd
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Question 6: How does the ID-VDS characteristic of the transistor change as the length of the channel is reduced? Why would this effect present a challenge to industry?
-Similar to the previous question, with the channel length decreasing, the slope increased. This tells us that more current has flowed in the shorter channel. However, this may cause a problem to the industry. There could be high heat generated by the high current that could damage the circuit. This is because in a short

channel transistor, even a small voltage could yield large electric field. This would induce hot carrier effect in the MOSFET. We notice from the graph that the slope of ID vs. VDS increases as the length of the channel is decreased. This means that more current flows as the channel becomes shorter. This could present a challenge to the industry because in a short channel MOSFET, small voltage could ultimately cause a large electric field across the channel, which leads to electron velocity saturation. This could lead to hot carrier effect which may form a space charge that causes the device to be damaged. This is due to the higher kinetic energy of the hot carriers that are being injected. Furthermore, the heat could damage the circu

Question 7: What do you notice about the value of Ion/Ioff as the length of the channel is reduced? Why would this effect present a challenge to industry?

-With the decrease in channel length, the line had an upward vertical displacement, leading to higher Ion/Ioff value. However, decreasing the channel length could cause the problem for the industry for the same reason as explained in question 6 (generation of heat).
Decreasing the channel length straitens the line. The bending near the 0 gate voltage straightens out. Short channel length would create leakage that would reduce the energy efficiency. This would be the main problem to the industry. Furthermore, the leakage may also generate unwanted heat.

Question 8: How does the IV plot change as the channel length is varied?

We see the plot shifting to the right with increase in channel length and shifting to the left with decreasing channel length.

Question 9: How does the IV plot change as the work function is varied? How could this effect be useful to industry? -Similar to the previous question the plot shifts to the right when work function increases. Similarly it shifts to the left when it decreases. This can be useful in the industry because we can tune the work function by changing the doping levels. This would change the threshold voltages and by changing this value we can use it as an advantage. For example, lower threshold voltage is good for high speed circuit.
Similar to question 8, when the work function is decreased the plot shifts to the left. This effect could be useful to the industry by tuning the work function. This can be done by changing the levels of doping, which would change the threshold voltage. This controlling of the threshold voltage is useful as lowering is good for high speed circuits for example.

Question 10: Why would physically altering the relative size of the source/drain affect the current through the drain? Refer to your response from question three in your answer (i.e. Think about how EC was affected by changing the size of the source and drain, and then relate that to why EC affects the current).
-When the source width is decreased the EC value is reducded. This causes higher electron current to flow. Decreasing the width of source lowers EC. When EC is low, higher current can flow from the source. This is shown from our graph above. The reason is the lowered barrier.

Recommendation
For question number 6, a plot for Id Versus Vd should be corrected in such a way that no any lines intersect each other. It was a mistake I made during the lab and I didnt enough time to correct it. In this case, data for the pink curve should have been entered wrong. It should be lower than any other curve. It is recommended, as usual, to read the lab instructions carefully before the lab. The two parts of the experiments are based on MOS capacitance/conduction band diagram and trans-conductance. You should have background knowledge in these principles beforehand.