Introduction ............................................................................................................................................................. 2 The Design Process ................................................................................................................................................. 2 Eagle Light Edition PC Board Design Tool ........................................................................................................... 3 Create a New Project and Schematic .................................................................................................................. 3 Add Components to Your Schematic ................................................................................................................. 4 Wire Modules, Then Connect Modules ............................................................................................................ 11 Generate Board from Schematic ....................................................................................................................... 13 Eagle Autorouter ............................................................................................................................................... 19 Advanced Circuits Design Rules ...................................................................................................................... 21 The High Cost of Vias ...................................................................................................................................... 27 Traces: Top or Bottom? .................................................................................................................................... 27 Eagle Fonts........................................................................................................................................................ 27 Adding Useful Text........................................................................................................................................... 28 Resizing the Border........................................................................................................................................... 29 Checking Drill Sizes ......................................................................................................................................... 30 Pouring a Ground Plane .................................................................................................................................... 30 Eagle CAM Processors ..................................................................................................................................... 37 Graphicode GC-Prevue Gerber File Viewer ......................................................................................................... 40 Files to submit ....................................................................................................................................................... 46 PC Board Design Steps Review............................................................................................................................ 46 Ordering a Board from Advanced Circuits ........................................................................................................... 47 Addenda ................................................................................................................................................................ 51 Reading Data Sheets ......................................................................................................................................... 51 Making custom parts ......................................................................................................................................... 57 Create SN74LVC4245ADW ........................................................................................................................ 57 Create LTL-14 Bi-Polar LED ....................................................................................................................... 74 Create SW-PB-MOM.................................................................................................................................... 75 Copying Library Parts ....................................................................................................................................... 76 Editing Packages to Correct Pin Numbering .................................................................................................... 76 Changing All Pads in a Library ........................................................................................................................ 76 Approving Errors .............................................................................................................................................. 79 Correcting Overlap Errors................................................................................................................................. 79 Autorouting a SMD Device .............................................................................................................................. 85 Stop Mask Errors .............................................................................................................................................. 86 Value as Text in Layer 27 ................................................................................................................................. 88 Changing Header Numbering ........................................................................................................................... 88 Dimension wont Delete ................................................................................................................................... 89 Manual routing tricks: ....................................................................................................................................... 89 Panelizing Boards ............................................................................................................................................. 89
Introduction
In this tutorial, we will wade through the process of creating a printed circuit (pc) board. These steps illustrate some principles of project management, trouble-shooting, trade-offs, and reading data sheets. It is tempting to skim a document, looking for quick answers. Students should work through their own design process, sometimes spending hours studying data sheets and experimenting with tools. This document aims to clarify certain procedures, for which the author found no satisfying explanations. There are known inconsistencies in the screen captures. The author attempted to document techniques for correcting schematic and board errors in the Addenda. As the outline for this document was refined, only the best examples remained, regardless of version. You can improve this document by contacting the author with suggested clarifications.
Add the PIC18F4550_40, from the microchip library. We chose the 40 pin DIP package to allow soldering with a pencil iron and to simplify adding sockets next to each pin for creative expansion.
Left click the mouse to anchor the part on the grid. Escape twice gets you out of add mode.
What is an ICSP port? What does it look like? What library part? How much time do we need to spend browsing Eagle libraries before we have a good feel for what parts are available? By studying the PICkit 2 documents, especially 44-Pin Demo Board User's Guide and PICkit 2 Users Guide, I found the pinout and mechanical considerations for this jack.
By loading the Hack A Day 18F4550 Proto Board Eagle schematic, using the i (info button), I identified the Eagle library, con-lstb.
The part, MA06-1 looked close, so I added it to our schematic page. To add a USB connector, I studied the Hack A Day 18F4550 board page, which revealed a Berg library. This helped me find a Berg 61729 connector, which is available at Digikey.
When I was adding the USB connector, I found that right-clicking the mouse rotated the connector, before placing it. You can also use the Move tool and the right mouse button to rotate parts. Test this function before you need it. How many mouse buttons did you use? In what sequence? I did not find a LM1117 voltage regulator in the default Eagle library. However, by searching the libraries page at http://www.cadsoft.de/download.htm I found v-reg-2.lbr had the part, so I copied it to my installed version of ~\Eagle\lbr\ From the Eagle control panel, I scrolled down to the new library and highlighted the dot to include it in my project. This makes it easier to choose from a smaller set of libraries when adding parts.
The next part is a Texas Instruments SN74LVC4245ADW Octal Bus Transceiver in a 24-SOIC package. The texas.lbr did not contain a similar device. A google search did not reveal a library part. So lets make a part. Refer to: Create SN74LVC4245ADW in this documents Addenda. Add the newly created component, 74LVC4245.
I wanted to rotate the chip before anchoring, so I right-clicked, while the part was hovering, then left-clicked to anchor it.
I want to add sockets for easy connections from this board to a standard breadboard. Also, I want to connect a signal to on-board diagnostic LEDs. I look through the con*.lbr for appropriate connectors. Remember we used the con-lstb.lbr for pin headers. Con-lsta.lbr has socket headers.
Add a 20 pin socket header to the schematic page. Right-click to rotate, then left-click to anchor. Leave enough room for Labels, which can be used to connect Nets. Sometimes it is easier than drawing a lot of wires. Move Groups as needed to organize your design. Select Group button Draw a rectangle around the group of components Right-click the middle of the group and select Move Group Right-click to rotate Left-click to anchor Add additional sockets as desired.
We also need sockets for LED indicators. Bi-color LEDs would be nice. SIP resistor packs would simplify assembly.
I did not find all the exact parts, so I chose similar parts, based on the electrical and mechanical data found in the component data sheet. Above is resistor-sil.lbr.
Above is a first trial of the LED indicators. I was not pleased with the LED symbols. There were no appropriate bi-polar LED devices in the standard Eagle libraries and I could not find one online. Refer to: Create LTL-14 Bi-Polar LED in this documents Addenda.
As an experiment, I attempted to add a Net to the connector pin, as the User Manual instructed. The Net turned into a Wire, with a Net Name, and Naming the Net produced the same dialog as Labeling a Wire. There is no one correct method to producing a working design. In the next screen capture, a wire was added between the connector and resistor (Name=R6, Value=221). A wire was added to the end of R6 so we could add a Label Name (RB5). Eagles Electrical Rule Checker (ERC) complained that we needed to add a junction symbol between SV1-Pin1 and R6.
Wire each module separately. Run ERC often. Dont ignore warnings or errors. Dont automatically approve all exceptions. Take the time to understand why Eagle is complaining. In our design, we will approve several exceptions.
I like to place power and ground pins directly inside the rectangle of the symbol view. Eagle doesnt like that. After making absolutely sure these connections were correct, I approved these exceptions. When I was laying out the Board view (next section), several component values overlapped useful text and Eagles Smash command did not work for me. I wanted most values to remain on the Board, to help mount components, so I chose to remove some value fields for clarity. Eagle didnt like this. In most cases, I added Text in the Value layer, which is similar to the Value field associated with a component, but easier to move independently. After making absolutely sure the Text matched the Value, I approved these exceptions. Our complete schematic has many standard resistors and capacitors, which closely match the data sheets and the library parts. Transfer important component dimensions from the data sheets to the parts spreadsheet to make our library search easier.
It is critical that the Schematic and Board remain consistent. Some edits to the Board view will damage this relationship. Eagle will generally display an error message before allowing such actions. ERC will indicate if the views and their links are consistent.
The components are initially drawn outside the default board border. Each component will need to be moved into the boards border. The border size can be adjusted later. If you need an exact border size, you should set this before placing components. The border snaps to the grid, so you should set the grid size to the needs of the project. ViewGridDisplay=On, Size=0.05 inch
Rotate components so the airwires are short, straight and not crossed. This exercise involves some trial and error; you can move these components repeatedly as you finalize your board routing. The next screen capture shows an obvious crossing of airwires.
In the next screen capture, all the components are placed compactly, but the airwires are not optimized. Zoom in to an area to untangle the airwires. The problem areas may become clearer when we start auto routing the board.
When the board is first generated, the default visible layers (Display tool under the info tool) are:
Review the Eagle User Guide, Chapter 10, Layers and their Usage. As we place components, we may find that a layers information overlaps another layer, interfering with a clear visualization of how our board will turn out. You may toggle any layer on or off. It is tempting to turn on all layers, to be safe, but this will produce some unexpected errors. See Stop Mask Errors in the Addenda. The following screen capture shows overlapping information.
We need to see the values in the board view, to be able to easily mount our components, but we dont really need to know that the resistors are named R4 and R3. We may decide to select or deselect layers in the cam processors when generating our Gerber files later in this document.
All 4 of these errors indicate that we have placed the double socket connector too close to the edge of the board. We move the connector. We will need to check the default Eagle rules against the requirements for Advanced Circuits before deciding we have found all relevant errors. If there is no popup window, generally there are no DRC errors. You can select the yellow exclamation mark to see that indeed there are no errors. This is a good sign.
Eagle Autorouter
Important: Read the Eagle Users Manual chapter on the Autorouter before running these tools.
After running the Ratsnest tool, several components obviously need to be rotated, like the LED header:
From the Board view, select the Auto route tool button and save the default settings for future use.
Read the Eagle Users Manual section on What Has to be Defined Before Autorouting.
From the Eagle Board view, choose EditDesign Rules. Save the default before modifying. To the best of my knowledge, the default Eagle Design Rules meet all of the specifications required by Advanced Circuits. Lets run the default Auto router and see how bad it is. Even though auto routers are crude, you can trick them by using restrict layers.
Note that the SMD did not get routed. Refer to: Autorouting a SMD Device in this documents Addenda. After the Routing Grid has been changed from 50 to 25, the Auto router completes, but there are some obvious areas for improvement.
Component layer traces (or vias) under a SMD will hide any problems. Traces beneath a SMD may be damaged if the SMD needs to be replaced.
Choose the Ripup tool, then the Green Traffic Light button to rip up all signals.
Change the layer to bRestrict. Draw a Rect around the SMD. Ripup all signals. Ratsnest, then Auto route again.
The SMD traces are still very close to the SMD pads. If our soldering technique is not perfect, we may have a short circuit. Lets increase the wire to pad clearance in the Design Rules.
Through trial and error, 12mil clearance gave the best results while minimizing vias. Save as SMD1.dru
We could manually move the trace, which contains the via, but this could create more problems. Refer to: Dimension wont Delete in this documents Addenda. Instead, lets try to restrict it. Change layer to vRestrict. Draw a Rect to specify the rectangle where we want to restrict vias. Ripup all signals, Ratsnets, and Auto route. Now no vias are obvious. An easy way to look for vias is to Display only the via layer (18). We have a blank page. To get back to a reasonable Display of layers, select all, then de-select: tNames(25) and tStop(29). Refer to: Stop Mask Errors in this documents Addenda.
Eagle Fonts
http://www.cadsoftusa.com/faq.htm#06022701 EAGLE uses and shows in the Layout Editor (also in the Schematic) a proportional font by default. But this one can't be used for generating manufacturing data by the CAM Processor. The CAM Processor can only work with the EAGLE internal vector font. The appearance of the vector font however, differs from the proportional font in size and length. Thus we recommend to write all texts - at least those in copper layers - in vector font. Besides, there is the option Always vector font in the Options/User Interface menu which displays and prints all texts in vector font, independent of the originally defined font. If this option is active, the texts on the screen will look exactly the same as they will do on the printed circuit board. A particularly suitable example to demonstrate the differences would be inverted text in a polygon (therefore the text is written in one of the Restrict layers). If you pass on the BRD file directly to your Board House in order to let the operator there generate the manufacturing data, it's recommended to activate the option Persistent in this drawing, too. In this case his EAGLE system will display the vector font as it is on yours. It does not matter if the option Always vector font is set or not then.
Use the Zoom tool for a more precise view. Feel free to turn off some board layer views if it will make the final board clearer. You may want to turn off the bottom layer, since it wont interfere with text on the top layer. Important: If you have to move a component, Ripup all first, Move the component, Ratsnest, and Auto route again. Here, we have finished annotating our board. We used several areas of tRestrict to make component identification clearer. o We forced the USB connections to be on the bottom side of the connector. Note that if you cover all 4 pads of the USB connector with tRestrict, DRC will complain. o We placed tRestrict over several component Values, to avoid the process of removing value, adding text, approving an ERC error, for each component.
If you need an exact border size, you should set this before placing components. The border snaps to the grid, so you should set the grid size to the needs of the project.
Choose the Name tool; double-click a polygon blue dot; connect the pour to DGND.
To view the results, select Ratsnest (obviously). To increase the Pour area, decrease the Spacing and Isolate values. If you need to Modify your design, Delete the Polygon first. With the Move tool, left-click near the edge of the Pour to reveal a dotted polygon line. Move the line outside the boards border. Now the full Polygon is revealed and can be deleted. Make any changes in the Schematic view, then in the Board view, then Ratsnest and Auto route. When you are satisfied, you can add the Pour. If you make modifications with the Pour in place, signals will automatically tie to the Pour and create other routing problems that you have already solved. Coverage with Spacing and Isolate = 0.024
How do we trick the program into Pouring under the PIC processor? Bogus parts. Lets add some 1.0M resistors under the PIC, which we will not populate (R9 and R10). We chose these signals because the traces were already running under the PIC.
Some information will be on both the Top and Bottom layers, like pads. It is helpful to automate a mapping of layers to output files. A component can be replaced in the Schematic view, routed in the Board view, ERC and DRC checked, and CAM processed in minutes. From the Board view, choose FileCAM Processor. We need tabs for each output file. The section name should be descriptive and clear. The Device output is critical. All output files use GERBER_RS274X, except the Drill section, which uses EXCELLON. The output file names should be meaningful and have the correct extension. Default Solder Settings:
Note that we Added a tab for each new output file. Default Component Settings:
Custom Top Silkscreen settings. For our board, we will not use the tNames layer in this cam processor. The tNames clutter the silkscreen. The tValues are more important for this design. The LED flat is in layer tDocu. We want to add this layer to the top silkscreen cam processor tab.
Save these settings in a dot cam file. Process Job to generate all the output files.
You may check all the imported information, but usually multiple Enter key strokes displays the imported layer.
Continue importing at least the border (.bor), bottom (.sol), top (.cmp), top silkscreen (.plc), and drills (.drd). Once you are satisfied with these layers, you may add any other layers you generated. The order of importing affects the view. Importing the border layer first automatically sizes the viewing frame. Import the bottom layers before the top ones.
I installed the current version of GC-Prevue and all my layers were yellow. Double-click any layer (left column) to open a properties dialog. Make choices for each layer, Apply, and OK. I have not found a way to automatically apply a specific color each time I input a layer.
The Layer Information of the Drill layer gives us a good idea if we have undersized a substantial number of pads and drills for our component selection.
Eagle Lite version 5.0 is more accurate than previous versions. We still want an independent view of the files we will be sending to our board house. Remember that we can control which information is present in each layer using the CAM processors. Lets compare Eagles view to GC-Prevue:
Files to submit
Follow the instructions given in your assignment. Who is your audience? Who is your customer? Assemble all the files specified in the CAM processor section with the current schematic and board files. This would include: .sol, .cmp, .plc, .pls, .sts, .stc, .drd, .bor, .sch, and .brd files. Zip all these files with a file name that identifies who you are, what the project is, the version of the project, and the date of submission. Abbreviations are fine.
Immediately, their software recognizes all of the layers, except .bor, for which we choose Drawing/Other. They may ignore this file by using the extents of the components as the border size.
The bottom of the page requires some thought. Since I am a registered user, my name a telephone number are filled in from their database. We are ordering a prototype, so follow those guidelines. If you submit top and bottom silkscreen and solder mask, you must choose both for those fields, or receive an error. 0.062 is a standard board thickness. Use the Layer Information for the border file in GC-Prevue to find the X and Y dimensions.
You must view DFM results before concluding that your design is OK.
The standard price is $83.58 each in quantities of 5. Thats too expensive. The last time I ordered, I was able to change the quantity field to 1 and re-calculate.
Even though I ran all my designs through their FreeDFM design rule checker, my boards still ended up in Cam Hold after placing my order. After working with a board house for several years, through dozens of designs, you may appreciate why they red flag certain techniques and you may choose a more conservative design approach. http://www.4pcb.com/
You may be able to panelize your design and further reduce the cost. For instance, I could fit 6 copies of the board used in this document on a panel. See Panelizing Boards in the Addenda. Be careful not to let another group hold up the production of your board and adversely affect your grade. Update: We panelized a board this summer and ordered a $33.00 special. They charged us an extra $50.00 for multiple parts, even though there was really only one part. I argued with them for a half hour. Even if you connect multiple boards with some bogus traces, they will find it and charge the extra $50.00. With shipping, 9 boards cost around $100.00. Let us know if you find a better deal.
Addenda
Reading Data Sheets
The following part requires 0.039 +0.004 -0.002 drills, on 0.100 centers. If the leads are closer to the maximum diameter, will they fit into your drilled pad?
The following part requires 0.43 mm drills, on 4.88 mm centers. No tolerances are specified, but we should allow for manufacturing variations.
The following part has mounting holes and very large drills.
Tantalum capacitors are extremely stable and have a low effective series resistance (ESR). They also have a polarity and tend to explode when reverse-biased (installed backwards).
The following voltage regulator will shut down if it gets hot. Note that a TO-220 case with no heat sink will exhibit an average temperature rise of 79 degrees C above ambient if you try to dissipate a Watt through it. That will burn you.
The following tranceivers require two voltages, three grounds, and logic referenced to Vcca.
You might want to protect this device, since it is a surface mount package and difficult to replace.
Create SN74LVC4245ADW
The 74xx-us.lbr contains a SO24W package. But I cant add it to the schematic.
There are 3 essential representations of a component: package, symbol, and device. The package is the physical representation. The symbol is the representation on the schematic page. The device representation maps the logical pins to the physical package. Page 14 of the SN74LVC4245ADW datasheet gives the dimensions of the DW package.
The most difficult function I encountered was copying a package group to the paste buffer. I changed versions from 4.16r2 to 5.0.0 (recently released) to see if there were any improvements. I checked to see if there was a SN74LVC4245ADW or similar part in the Eagle 5.0 package. I was back to making a new device. In this part creation process, we are going back and forth between an existing library and a new library we are creating. Eagle allows only one library to be open at a time.
Select the Cut button. One option is to choose the Go button (next to the Stop sign) after the Cut button:
Another option is to right-click over the selected group and choose Cut Group. Another option is to right-click outside of the group and choose Cut Group. The appearance is very different for each option, but the result is the same. This places the group in the Paste Buffer. FileNew (opens new library) FileSave As (74LVC)
We have created the 74LVC library. There are no completed components in it yet. Select the Package button
There is an octal bidirectional bus transceiver, similar to our device. This closes the 74LVC library, because Eagle Light only allows one library to be open at a time. Load an existing symbol, similar to our bidirectional buffer.
Use the same general procedure to copy this symbol to the paste buffer: Group Select All Cut Group
Use the left mouse button to select a pin (not the name string) to change a pins name. In our example, we selected the left end of the pin named G. We will change its name to match the data sheet.
Note we have used !OE in the dialog box. On the Symbol editor, OE, with a bar on top, appears. This is an Eagle feature. To enlarge the symbol footprint, in order to add more pins, select Move, left-click an edge, drag the outline, and left-click to anchor.
To move pins, choose the Move button. Left-click the end of a pin to select it, move it to the desired location, and left-click to anchor it.
On the symbol view Left-click >Value, move cursor, left-click to anchor. Change layer back to Symbols Finish adding pins, names, and properties, so that our symbol matches the data sheet. Note that Eagle was not happy naming two pins with the same string, so we had to be creative (3.3VA and 3.3VB).
The final step is mapping a device variant. Select the Device button Add a New device
ADW is our package variant for the SOIC or SO24W in the SN74LVC4245A data sheet. A is for chip revision A. DW is for SOIC.
Have your SN74LVC4245A data sheet open. Select the Connect button Highlight corresponding pin and pad and choose Connect. You should connect a pin name to each pad name.
OK. File--Save
Open the Library editor (led.lbr) Copy an existing package (LED3MM.pac) to the Paste Buffer (Group, Cut, Go) Open a new or existing library PackageNew--Name Paste Buffer and Save (library) Open led.lbr again Copy an existing symbol (DUOLEDRG-A) to the Paste Buffer Open the same library you pasted the Package into SymbolNew--Same Name as Package, above Paste Buffer and Save (library) Edit symbol layer to match our chosen component Save (library) Create new device (Same Name as Package) Add symbol we just created New (variant), Package name as above, variant named something useful Connect: Map our symbol to our package Save (library)
Create SW-PB-MOM
Refer to Create SN74LVC4245ADW for a more detailed description of creating a part. Steps:
Open the Library editor (switch-dil.lbr) Copy an existing package (DS01.pac) to the Paste Buffer (Group, Cut, Go) Open a new or existing library PackageNew--Name Paste Buffer and Save (library) Open switch-misc.lbr Copy an existing symbol (DT) to the Paste Buffer Open the same library you pasted the Package into SymbolNew--Same Name as Package, above Paste Buffer and Save (library) Edit symbol layer to match our chosen component Save (library) Create new device (Same Name as Package) Add symbol we just created New (variant), Package name as above, variant named something useful Connect: Map our symbol to our package Save (library)
Library Editor: Save PIC_kludge_040 library. Repeat for the other 3 parts. Control Panel: View PIC_kludge_040 library to see that it contains all 4 parts. Library Editor: PIC_kludge_040 Run ULP:
This will change all drills within +/- 50% of 1.016 mm.
Schematic View: Replace the original parts with the enlarged-drill size parts. Make sure the changes are consistent between the board and schematic views by running ERC and DRC. In my case, I had to move a trace to increase the clearance between it and a switch pad. Split is a good tool to move only a small section of a trace. Continue refining until ERC and DRC produce no (unapproved) errors
Approving Errors
Schematic (ERC Errors and Warnings) I like to include the power and ground pins in the Symbol view. Eagle complains when +5V, GND, VDD, or VSS are connected to such pins. Approving such errors or warnings moves them to a folder that can be safely ignored. When the Value of a component clutters a board layout, I remove the value. This is reflected in the Schematic view and can be safely approved and ignored. Board (DRC Errors) Board errors are more serious, usually indicating short circuits or mechanical conflicts. These should be fixed. If you are designing a special board, with special mechanical features, you may carefully approve errors. Board errors will probably be caught by the board manufacturer, so be prepared for a delay.
ERC errors are expected. Generate the board layer. Move components into board outline, rotating for straightest airwire placement
Simplify. Cut the problem in half. Check the library part, which we created. User error is generally a good place to start troubleshooting.
This should be pin 1. Somehow, the library part became corrupted. So we generate a new library part: We copy the package from 74xx-us.lbr, SO24W, as before. We name the new package LVC4245 to distinguish it from the corrupted part. We check the name of each pin. They are in order from 1 to 24 as required. We copy the symbol we created from 74LVC.lbr, 74LVC4245, to save all the time we spent editing. We name the new symbol LVC4245 to distinguish it from the corrupted part. We add a new device, named LVC4245. We add the LVC4245 symbol, we created. We add a new variant, called ADW, to make our part match the manufacturers data sheet. We connect the pin description to the pin number. We save our work often. Use the replace command to replace the 74LVC4245 part with the newly created LVC4245 part in our test schematic.
We have some expected ERC errors, which can be approved and ignored. Our test board looks almost identical.
Now the Overlap errors are gone. The SMD project still wont auto route, but that is covered in another section of this document.
The test project now autoroutes, but the routes are obviously not optimized.
To ripup all routes, choose Ripup, then the green stoplight icon.
After replacing the 74LVC4245 part with the LVC4245 part in the PIC_kludge schematic, perform ERC. Switch to the Board layer Perform DRC. 541 Stop Mask errors. Oh joy! Simplify the problem. Create another test project. Load testLVC4245 Notice that not all layers are shown. Turn on all layers and re-run DRC Now we have multiple Stop Mask errors. Consistent.
Increasing Min and Max values increases the number of Stop Mask errors. Setting both to 0 does not eliminate Stop Mask errors. Changing 100% to 50% does not reduce the number of Stop Mask errors. Are these really important? http://www.cadsoftusa.com/version50.htm
The DRC now reports an error if an object in the t/bPlace, t/bNames or t/bValues layer overlaps with an object in the t/bStop layer (provided these layers are active when the DRC is run). This is odd behavior. So in the Board view, we choose Layers and display None. Then select layers: Top, Bottom, Pads, Vias, tStop, bStop, Drills, Holes. We dont care if the solder mask overlaps the silkscreen. Run DRC again and we have no errors. So we can probably safely ignore stop mask errors, if all layers are turned on.
If you are adding text, type the text in the box, then adjust the size and ratio, before pasting.
Before we lose all this work, close the board view, save schematic as PIC_kludge_2.sch. Now regenerate a new board to see if the extra via dimensions are still there. Realizing that placing the parts was taking too long, I created a temp folder, copied PIC_kludge.brd into the folder, renamed it to PIC_kludge_2.brd, and copied it back to the PIC_kludge project folder. With PIC_kludge_2.sch open, I opened the .brd file and magically the extra dimension marks (drills from deleted vias) were not there. Much faster than starting from scratch.
Panelizing Boards
These techniques worked better in Windows than linux. Your mileage may vary.
http://claymore.engineer.gvsu.edu/~steriana/Python/gerbmerge/ http://gerbv.sourceforge.net/