PLL-Based Repetitive Control Applied to the Single-Phase Power Factor Correction Using Boost Converter

L.M.F. Morais1, R. M. Santos Filho2, P. C. Cortizo1, S.I. Seleme Jr1, P.F. Donoso Garcia1, P.F. Seixas1
Federal University of Minas Gerais UFMG Dept. of Electronic Engineering, Belo Horizonte, MG - Brazil lenin@cpdee.ufmg.br
1 2

Federal Center of Technological Education CEFET/MG Dept. of Electronics, Belo Horizonte, Minas Gerais, Brazil rsantos@deii.cefetmg.br

Abstract-The low frequency ripple in single-phase power factor correction (PFC) boost converters dramatically limits the bandwidth in standard control strategies, deteriorating the overall system performance. This paper presents the study and the implementation of a Phase-Locked Loop (PLL)-based repetitive controller in order to improve the dynamics and the input current distortion in a PFC boost converter. The repetitive control applied to the PFC presents a straightforward implementation with satisfactory results when compared to other techniques, as described in the paper. Experimental results validate this claim.

I.

INTRODUCTION

Active switched-mode input power factor correction using the boost converter is the most used alternative to obtain quasi-unity power factors in electronic loads such as electronic ballasts and power supplies. In single-phase applications with corrected power factor, the input power oscillates at twice the line frequency, which leads to low frequency voltage ripple at the output of the boost converter. From the control perspective, this low frequency ripple acts as a periodic disturbance and dramatically affects the system overall performance. Typical PFC control schemes use two cascaded loops: the external loop aims to regulate the boost output voltage and provides the amplitude reference to the inner controller, which controls the (ideally) sinusoidal current absorbed from the grid. Since the low frequency ripple appears in the error signal of the output voltage loop, the controller bandwidth must be reduced in order to avoid distortion in the reference signal to the input current controller. In other words, the controller gains must be reduced (and so the bandwidth) in order to avoid the degradation of the input current THD and of the resulting input power factor. As a result, load transients are poorly rejected due to the slow controller [1]-[3]. For instance, the output voltage may rise beyond safety limits under load rejection. One way to reduce the low frequency oscillation in the error signal without degrading the controller bandwidth is to oversize the output boost capacitor, what will impact the final weight, size and cost. Another approach is to sample the output voltage exactly at the zero crossing points of the line voltage [4], such that the second harmonic ripple is canceled

out in the sampled signal. It is a simple method that avoids the use of an oversized capacitor but it leads to poor performance due to its inherent low speed of response. A very attractive solution to this problem is the use of the plugged-in repetitive controller [5]. The repetitive controller is responsible for the periodic perturbation rejection and operates in conjunction with standard linear controllers. This approach allows the use of a small boost capacitor and at the same time enables high speed of response, while maintaining low input current THD. In addition to the aforementioned issues, standard PFC control strategies use the line voltage waveform in order to produce the input current sinusoidal reference signal. In fact, this sampled line voltage waveform is multiplied by the output voltage controller signal. However, the line voltage waveform itself is often highly distorted due to non-linear equipment supplied by the same grid. As a result, in principle the input current THD can not be smaller than the line voltage THD. Moreover, in the standard PFC control strategies the line voltage amplitude variations will disturb the boost output voltage by two paths, i.e. by disturbing the current reference in the input current control loop and the by the direct power path as well. In order to overcome these problems the implementation of the repetitive control scheme together with a distortion-free constant unity amplitude sinusoidal current reference waveform synthesized by a Phase Locked Loop PLL is proposed in this paper. The increased performance of the PFC control using this PLL-based repetitive control is verified experimentally. In Sections II and III the PLL implementation and repetitive control as applied to the PFC boost converter are respectively presented. In Section IV the PFC boost converter and the different control strategies are presented in details. Experimental results are presented in Section V. In the Conclusions section the results obtained are analyzed and discussed. II. PLL STRUCTURE FOR THE REPETITIVE CONTROL In grid-connected equipment, the primary objective of a PLL is to correctly inform the phase-angle of the input signal fundamental component under real conditions, i.e. in the

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presence of noise, harmonics and other kinds of disturbances often found in the utility mains voltage. Among the several single-phase PLL structures that can be found in the literature, the power based PLL (pPLL) has been pointed out as one of the most robust structures [6], and has been chosen to be used in the present application. The PLL block takes the rectified line voltage, which may be noisy, distorted and may change its amplitude, and outputs a pure unity amplitude rectified sinusoid. Fig. 1 displays the block diagram of the single-phase pPLL, which is a classical structure [7]. Since its phase detector (PD) section is based on a single multiplier, the analogy with electric power can be used in order to understand its behavior more intuitively. If the fictitious power mean p is held to zero, then the fictitious current is will be in quadrature with the fundamental of the input voltage ei. Assuming a purely sinusoidal input voltage ei in the form V cos , in that situation the estimated phase-angle equals . The expression of the signal p( , ) in Figure 1 is: (1) p = V cos sin

V ) + V sin( + ) sin( (2) 2 2 The low pass filter extracts the mean power p , which is given by the first term of (2). Considering = t + , p=
= and allowing , for small phase differences t +

or

harmonic and small phase lag at the desired open loop crossover frequency. Thus, the careful design of the low pass filter and compensator must be performed in order to provide good dynamic response and disturbance rejection. It is worth noticing that either a DC or a 2nd harmonic component in the input signal would produce a fundamental frequency component in the PD output signal which must also be filtered out. Indeed, according to (2), each harmonic component of order h and amplitude Vh will produce two components of orders h1 and amplitude Vh/2 in PD output. Moreover, sub-harmonic components in very low frequency range (1Hz-2Hz) will produce components around the fundamental frequency in the PD output. Hence, it is desirable to have some attenuation at fundamental frequency so that large oscillations in the estimated frequency and phase are avoided. In the present application the PLL locks directly to the rectified line voltage signal, avoiding the need for extra isolating circuits that would be needed in the measurement of the line voltage itself. Hence, the feed-forward term ff must be set to twice the line frequency, i.e. ff=120Hz (754rad/s). Based on the guidelines suggested in [6], we have chosen the open loop crossover frequency c=10Hz, the allowable ripple in estimated angle as <10-3rad@120Hz and the desired phase margin m>30o for 0.8pu input voltage amplitude, what demanded a 4th order Butterworth type filter with cutoff frequency of 42Hz, yielding: m=34o, kp=160, ki=3500, |GPFI(s)|= -28dB@60Hz, -58dB@120Hz. III. REPETITIVE CONTROL APPLIED TO THE PFC The repetitive control is an appropriate strategy for tracking signals in the presence of periodic disturbances, which, in its most common version, presents itself as a plugin type control associated with standard feedback compensation. It is based on the Internal Model Principle IMP and in the decomposition of the control and disturbance signals in Fourier series. According to the IMP [8], in order to achieve tracking error convergence to zero in steady-state it is necessary and sufficient that the generator for the reference signal be included in the closed stable loop. The generator for the reference signal is understood as the linear system (a compensator), which for certain initial condition and null input, generates the reference command as an output. Based on the IMP, a compensator that generates all the periodic references must be incorporated in the closed loop of the controller in order to track periodic signals of known period T, in steady-state. If stable, the repetitive control will guarantee zero tracking error without exact knowledge of the

, p can be approximated by: V p ( ) (3) 2 which exhibits the small signal static PD gain. The PD dynamics will rely entirely on the filter structure. As pointed out by (2), there is a strong drawback to this structure: the product of input voltage and fictitious current is yields a second harmonic component which has to be filtered out. Thus, at first sight the low pass filter should have a low cutoff frequency, which degrades system speed response. Nevertheless, this drawback can be minimized if the filter order is increased simultaneously to its cutoff frequency, while maintaining adequate attenuation at the second
kp

ff
+

e p*=0 + + p
LPF

ki s

1 s

ei

is

sin(x)
Fig. 2. Block diagram of a) the repetitive control and b) the periodic signal generator (PSG).

Fig. 1. Single-phase power PLL.

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plant. Fig. 2(a) shows the diagram of a generic feedback control and the additional structure of a repetitive control in continuous time. P is the plant to be controlled, Ks is the standard stabilizing controller and Kg is the command generator used to track a periodic signal . The output variable y is fed back and compared with the reference, generating the error signal z. A periodic signal generator of period T, with infinite frequency spectrum, is a pure delay of the type eTs, (or zN, in discrete time notation) connected in unity feedback, as shown in Fig. 2(b). Although suitable for any type of periodic signal, there is no admissible controller Ks capable of stabilizing strictly proper plants P [10]. In order to stabilize systems described by the diagram shown in Fig. 2(a), for strictly proper plants (which constitute physical systems such as the PFC boost converter of the present application) it is necessary that the periodic signal generator be limited somehow in its frequency spectrum. A trade-off solution in this case is the inclusion of a lowpass filter coupled to the pure delay Q(z1) as shown in Fig. 3. The repetitive controller scheme used in the present work has the structure shown in Fig. 4, in discrete time. This technique, commonly called Modified Repetitive Control MRC [11], operates the removal of the high frequency poles of the generator rendering the plant stabilizable by the control action Ks(z), which is the stabilizing controller to be defined. The repetitive control block, Kg(z) [14] is described, in discrete time, in Fig. 4. Note that the block zN delays the input signal (the error ry) of N sampling periods, which correspond to one period of the reference signal. The same zN block is inserted previous to the filter C(z1) in order to render it causal. In this structure, the blocks Q(z1) and C(z1) are lowpass filters aiming to guarantee stability margins to the close loop system, according to the idea of the Modified Repetitive Control, which is to limit the bandwidth of the periodic signal capable of being tracked by the control. For further details on this control scheme, see [5].

IV. PLL-BASED REPETITIVE CONTROL APPLIED TO THE PFC BOOST CONVERTER Repetitive control has been applied successfully in UPS (Uninterruptible Power Supply) inverters, aiming at the rejection of periodic disturbances due to nonlinear loads consisted of e.g. a rectifier followed by a capacitor filter and a resistive load [13], [14]. In the present application, as in [5], the main objective of the repetitive action is to reject the effects of the inherent low frequency oscillation in the DC Link due to the input rectifier. Applications of the repetitive control in AC-DC PWM converters can be found in the literature [15], [16]. The main difference between these applications and the one presented here is that the power factor correction in the referred papers is done in the (three phase) rectifier stage which is controlled, whereas in our work the rectifier is uncontrolled and the power factor correction is done by controlling the boost converter. Therefore, in the present application the low frequency oscillation of the DC link, caused by the uncontrolled rectifier has also to be rejected by the boost converter control stage. The PLL was digitally implemented to synthesize a clean current reference waveform whose amplitude is given by the output voltage controller, as described in the previous sections. The boost converter was implemented as shown in Fig. 5. Two different techniques were employed in the boost converter control stage: 1. The classical approach with current sampling done at the switching frequency and a PI; 2. The repetitive plug-in control added to the main classical PI control. In this second approach, two different strategies were tested: a. The standard repetitive control, taking the measured rectified line voltage to build the reference to the current controller, as depicted in Fig. 6; b. The PLL-Based Repetitive Control, using a synthesized waveform reference for the controller, as shown in Fig. 7.

Fig. 3. Block diagram of the repetitive control plug-in and the main stabilizing control.

Fig. 5. The boost PFC power circuit.

Fig. 4. Block diagram of the repetitive control.

Fig. 6. Control loops for the PFC converter without the PLL block.

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Fig. 7. Control loops for the PLL-based PFC converter with the PLL block.

V.

EXPERIMENTAL RESULTS

In order to validate the proposed technique, the boost converter was implemented as pre-regulator PFC circuit to a generic resistive load of 150W. The controllers were implemented in a Texas Instruments DSP (T320F2812). The main system characteristics are: rated power PN=150W; boost output voltage Vo=250V; switching frequency fs= 24kHz; nominal line voltage E=127Vrms, nominal line frequency fs=60Hz. The boost reactive elements are Lboost=6.7mH and Cboost=22 F. The input filter elements are Lf=850H and Cf=470nF. The PI gains in the current control loop have been set to kpc=0.5 and kic=20x103 for all tests. The PI gains in the voltage control loop have been set to kpv=1.0x10-2 and kiv=2.5 for all tests, leading to acceptable response to load transients. Fig. 8 shows the input (line) current and line voltage waveforms using the standard PI control only. The high distortion in the current waveform can be easily noticed, what is a consequence of the small sized DC link capacitor and the bandwidth of the PI controller in the voltage loop. Fig. 9 shows the line current and voltage waveforms for the same rms line voltage but now with the plug-in repetitive control. As can be seen, the current distortion has been clearly improved due to the repetitive controller. Fig. 10 and Fig. 11 present results for the PLL-Based Repetitive control. Notice that the input voltages and output power used are different from the previous tests, although the rms input current is the same. This had to be done due to technical problems with the prototype.

Fig. 9. Input (line) current and voltage waveforms for the repetitive control without PLL Vline = 147Vrms, THDi=8.9%, THDv=7.5%, Po=150W.

Fig. 10. Input (line) current (red) and voltage (blue) waveforms for the repetitive control with PLL Vline=37Vrms. THDi=3.04%, THDv=8.6%, Po=40W.

Fig. 8. Input current and voltage waveforms for the PI (classical) controller Vline=147Vrms, THDi=22.6%, THDv=7.4%, Po=150W.

Fig. 11. Input (line) current (red) and voltage (blue) waveforms for the repetitive control with PLL Vline=65Vrms. THDi=3.7%, THDv=8.4%, Po=40W.

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TABLE I Harmonic Components in the Standard PI, PI+Repetitive, and PI+PLL+Repetitive Approaches Standard Repetitive + Repetitive + PI PI PLL + PI Vin=147V Vin=35V Vin=65V Harm IEC Std. Vin=147V n % % % % % 2 2 0.3 0.32 0.10 0.42 3 30*PF 20.6 4.25 0.46 0.53 5 10 8.37 6.23 0.62 1.79 7 7 1.47 1.41 0.26 0.80 9 5 1.27 0.86 0.34 1.09 11 3 1.29 1.51 0.43 0.11 Current THD(%) 22.64 8.91 3.04 3.69 Voltage THD(%) 7.45 7.5 8.59 8.36 Power Factor 0.92 0.987 0.989 0.996

waveforms for the same test. It can be seen that, although the THDs are roughly the same, the output voltage overshoot for the classical control is much higher, even unacceptable, which indicates the limitation of this method regarding low input current THDs. Fig. 15 and Fig. 16 depict the output voltages and the input current waveforms for the same load transient of the former test, but now the PI gains are the same. As can be seen, the voltage overshoots are nearly the same for both control strategies, though the settling time is much larger when the repetitive control is present. The input current distortion is much higher for the classical control. Table II presents the gains and summarizes the results obtained in the simulation tests
450

400

Voltage (V)

350

300

a) Cboost = 1500F. 100V/div

b) Cboost = 22F. 100V/div

250 Repetitive control Classic control 1 Time (s) 1.5 2

Fig. 12. Output voltage waveform for a) Cboost = 1500F, (100V/div) and classical controller; b) Cboost = 22F (100V/div) and repetitive controller. Time scale: 10ms/div.

200 0.5

Nevertheless, these results clearly indicate the advantages of the proposed approach. Table I summarizes the THDs as well as the amplitude of each harmonic component for each test. The power factors are also shown. Fig. 12(a) shows the voltage waveform at the output of the boost converter for Cboost = 1500F. Fig. 12(b) shows the same voltage waveform for Cboost = 22F, that led 100V ripple (peak-to-peak) for an input voltage of 147V. It is worth mentioning that the test with a 22F capacitor was made in order to emphasize the good rejection capability and the robustness of the repetitive control. Note that the IEC standard is satisfied for a capacitance Cboost = 220F. VI. TRANSIENT RESPONSE ANALISYS Some tests that could not be performed on the bench were simulated. These tests aim to allow the evaluation of both control strategies concerning the trade-off between transient response to load disturbances and input current distortion. The load disturbance was chosen as a load rejection from 100% down to 10%. Two scenarios were chosen for these simulations. On the first, the PI gains were set such that the input current distortions were similar. On the second, the same PI gains were used for both control strategies, leading to similar overshoots in the output voltages but to different harmonic distortions. Fig. 13 shows the output voltages behaviors to the load disturbance and PI gains set to produce approximately the same input currents THDs. Fig. 14 shows the input current

Fig. 13. Transient responses of the output voltages to load rejection from 100% to 10%. The PI gains are set to produce similar harmonic distortions in the input currents.

1.5 1 Current (A) 0.5 0 -0.5 -1 -1.5 0.95 0.96 0.97 0.98 0.99 1 1.01 Time (s) 1.02

Repetitive control Classic control

1.03

1.04

1.05

Fig. 14. Input currents when the PI gains are set to produce similar harmonic distortions. THD (repetitive)5.5%, THD (classic)6.5%.

Table II PI gains, overshoots and THDs for both tests.

Standard PI kpv kiv THD(%) Overshoot (V) Same current THDs Repetitive + PI 0.004 0.01 0.4 2.5 6.5 5.5 415 340 Standard PI Same overshoots Repetitiv e + PI 0.02 0.02 5 5 22 5 310 312

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320

Repetitive control Classic control

REFERENCES
[1]. A. Prodic, D. Maksimovic, and R.W. Erickson, Dead-zone digital controllers for improved dynamic response of low harmonic rectifiers, IEEE Trans. Power Electronics, vol. 21, no. 1, pp. 173-181, Jan. 2006. [2]. A. Prodic, D. Maksimovic, and R.W. Erickson, Dead-zone digital controller for improved dynamic response of power factor preregulators, in Proc. IEEE Appl. Power Electron. (APEC), Miami, FL, Feb. 2003, pp. 382388. [3]. S. Buso, P. Mattavelli, L. Rossetto, and G. Spiazzi, Simple digital control improving dynamic performances of power factor preregulators, IEEE Trans. Power Electron., vol. 13, no. 5, pp. 814 823, Sep. 1998. [4]. D. Van de Sype, K. De Gussem, A. Van den Bossche, and J. Melkebeek, A sampling algorithm for digitally controlled boost PFC converters, IEEE Transactions on Power Electronics, vol. 19, no. 3, pp. 649657, May 2004. [5]. L.M.F. Morais, P.F. Donoso-Garcia, S.I. Seleme Jr., and P.C. Cortizo, Repetitive Control Applied to the Power Factor Correction Using Boost Converter, in Proc. of COBEP-Brazilian Power Electronics Conference, pp. 860-865, 2007. [6]. R.M. Santos Filho, P.F. Seixas, P.C. Cortizo, L.A.B. Torres, and A.F. Souza, Comparison of three single-phase PLL algorithms for UPS applications, IEEE Transactions on Industrial Electronics, vol. 55, no. 8, pp. 2923-2932, Aug., 2008. [7]. F.P. Marafo, S.M. Deckman, J.A. Pomlio, and R.Q. Machado, Metodologia de projeto e anlise de algoritmos de sincronismo PLL, Eletrnica de Potncia: SOBRAEP magazine, vol. 10, no.1, junho de 2005. [8]. B.A. Francis and W.M. Wonham, The internal model principle for linear multivariable regulators, SIAM Journal of Applied Mathematics and Optimization, 1975. [9]. S. Hara and Y. Yamamoto, Stability of repetitive control systems, Conference on Decision and Control, pp. 326-327, vol. 25, 1985. [10]. G. Curtelin, B. Caron, and H. Saari, Analysis of Repetitive Control System Robustness, IEEE International Conference on Systems, Man, and Cybernetics, vol. 3, pp. 2663-2668, 1994. [11]. A. Langari, Sampled-Data Repetitive Control Systems, PhD Thesis, University of Toronto-CA,1996 [12]. L. Michels, H. Pinheiro, and H. A. Grndling, Design Procedure of Plug-In Repetitive Controllers for Single-Phase PWM Inverters, IEEE Industry Applications Society Annual Meeting, 2004, Seattle, vol. 1. pp. 163-170. [13]. K. Zhang, Y. Kang, and J. Xiong, Direct Repetitive Control of SPWM Inverter for UPS Purpose, IEEE Trans. on Power Electronics, vol. 3, no. 3, pp.784-792, 2003. [14]. K. Zhou, D. Wang, and K.-S. Low, Periodic errors elimination in CVCF PWM DC/AC converter systems: repetitive control approach, IEE Proceedings - Control Theory and Applications, vol. 147, no. 6, pp. 694-700, 2000. [15]. K. Zhou, and D. Wang, Digital Repetitive Controlled Three-Phase PWM Rectifier, IEEE Transactions on Power Electronics, vol. 18, no. 1, January 2003. [16]. S-L. Jung, H-S. Huang, and Y-Y. Tzou, A three-phase PWM AC-DC converter with low switching frequency and high power factor using DSP based repetitive control technique, IEEE Power Electronics Specialists Conference - PESC, 1998, vol. 1, no. 29, pp. 517-523.

300

280 Voltage (V)

260

240

220

200 0.5

Time (s)

1.5

Fig. 15. Output voltages during load rejection from 100% down to 10%. PI gains are the same for both converters.
2 Repetitive control Classic control

1 Current (A)

-1

-2 0.95 0.96 0.97 0.98 0.99 1 1.01 Time (s) 1.02 1.03 1.04 1.05

Fig. 16. Input currents when using the same PI gains in each control strategy. The distortions in steady-state before the load rejection are THD (repetitive)5%, THD (classic)22%.

VII. CONCLUSIONS This paper proposes the utilization of a PLL together with a plug-in repetitive controller in order to improve the input current distortion and the dynamic response of the boost PFC pre-regulator. No additional hardware is required to implement the proposed control strategy and the extra algorithms do not have high computational burden. The PLL locks directly to the rectified line voltage, avoiding the use of isolation circuits, and outputs a synchronized sine wave that is used to generate the current reference to the input current controller. This way, in opposition to traditional approaches, the input current distortion is decoupled from the line voltage distortion, and is now able to be smaller than that. The experimental results so far obtained show that other than having a simple structure, appropriate for on-line implementation, the repetitive control led to good harmonic distortion reduction from 22.6% in the standard PI to 8.9%, while maintaining adequate speed of response. The results with the PLL (current THD around 3%) showed that the current distortion can be decreased beneath the line voltage distortion. ACKNOWLEDGEMENTS The authors would like to thank CAPES and FAPEMIG for funding this research project.

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