User's Guide
2
Copyright 2010, Texas Instruments Incorporated
Contents
Preface 1
....................................................................................................................................... 5 Interface Protocol ................................................................................................................ 7 1.1 Projector Control I2C Commands ......................................................................................... 7 1.1.1 Slave Receive Mode (Write to Chipset) ......................................................................... 7 1.1.2 Slave Transmit Mode (Read from Chipset) ..................................................................... 8 1.1.3 Reserved Areas .................................................................................................... 8 1.2 I2C Interface .................................................................................................................. 9 1.2.1 I2C Control Commands ............................................................................................ 9 1.2.2 I2C Alternate Address Select Pin ................................................................................. 9 1.2.3 Momentary Image Corruption During Command Writes ...................................................... 9 1.3 I2C Projector Control Commands ......................................................................................... 9 1.3.1 Configuration Register Projector Control Commands ......................................................... 9 1.3.2 Color Coordinate Adjustment (CCA) Command/Field Definitions .......................................... 21 1.3.3 Structured Light Control Command/Field Definitions ........................................................ 24 1.3.4 LED Color Mask Command/Field Definitions ................................................................. 25 1.3.5 Structured Light Control Command/Field Definitions (continued) .......................................... 26 1.3.6 Internal Pattern Structured Light Command/Field Definitions .............................................. 27 1.3.7 Options for Input Image Resolutions/Orientations and DMD Displayed Images ......................... 33 Powerup and Powerdown Considerations ............................................................................ 39 2.1 Powerup .................................................................................................................... 39 2.2 Powerdown ................................................................................................................. 39 Command Quick Reference ................................................................................................ 41
Contents
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List of Figures
1-1. 1-2. 1-3. 1-4. 1-5. 1-6. 1-7. 1-8. 1-9. 1-10. 1-11. I2C Interface Write Register ................................................................................................ 8 I2C Interface Read Register................................................................................................ 8 Portrait QVGA to HVGA .................................................................................................. 33 Portrait HVGA to HVGA .................................................................................................. 34 Portrait VGA to HVGA .................................................................................................... 35 Landscape QVGA to HVGA .............................................................................................. 36 Landscape HVGA to HVGA .............................................................................................. 36 Landscape VGA to HVGA ................................................................................................ 37 Landscape NTSC to HVGA .............................................................................................. 37 Landscape PAL/SECAM to HVGA ...................................................................................... 38 Landscape VGA Cropped to HVGA (Not Scaled) ..................................................................... 38
List of Tables
3-1.
...............................................................................................................................
41
List of Figures
Copyright 2010, Texas Instruments Incorporated
Preface
DLPU002A February 2010 Revised July 2010
Reference Documents
DLPC100 DLP Pico Processor Datasheet, DLPS019 Using Pico 2.0 Kit for Structured Light Applications, DLPA021
DLP is a registered trademark of Texas Instruments. Pico is a trademark of others. DLPU002A February 2010 Revised July 2010
Copyright 2010, Texas Instruments Incorporated
Chapter 1
DLPU002A February 2010 Revised July 2010
Interface Protocol
The I2C protocol used in communicating information to the Pico Chipset consists of a serial data bus conforming to the Philips I2C specification, up to 400 KHz. The I2C interface timing waveforms are shown in Figure 1-1 and Figure 1-2. The chipset operates as an I2C F/S mode slave.
1.1
Read Command: Address Sub-Address (8-bit) (8-bit) x36 x15 (8-bit) x37
Read Part 1 (Write address of requested register) Read Part 2 (Read data of requested register)
Interface Protocol
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SCL SDA
0x36 0x15 0x04
SCL SDA
0x37 0x00 0x00 0x00 0x00
Interface Protocol
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I2C Interface
1.2
I2C Interface
1.3
Interface Protocol
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1.3.1.1
When a command x04 is received by the projector, the 32 bits of data define the projector input image mode.
BIT(S) 2:0 DESCRIPTION Select the input source and interface mode: 0 - Parallel RGB I/F (1) 1 - Internal test patterns (2) 2 - Splash screen (3) 3 - RESERVED 4 BT.656 format (with embedded syncs) 5-7 RESERVED Spare Unused RESET b000 TYPE wr
15:3 31:16
(1) (2)
x0000
(3)
See Pixel Format command (I2C: x06) for supported input pixel format options. Internal test patterns uses command (I2C: x0B) to define the test pattern source and command (I2C: x05) for resolution. Internal test patterns mode should be selected when using internal stripe pattern structured light modes (see Display Mode command, I2C: x1F). For Splash screens, Free-run sequence synchronization mode must be used (see Sequence Sync Mode register, I2C: x24). A pre-determined set of splash screens are stored in the chipset in QVGA landscape format. Chipset must be set to display in QVGA landscape mode.
1.3.1.2
(2)
15:4 31:16
(1)
x000
(2)
Behavior of QVGA landscape and VGA landscape modes are further modified by settings of the Aspect Ratio Modification command (I2C: x0A). VGA landscape mode is required for structured light applications to prevent unwanted scaling of patterns. In this mode, the chipset expects to see VGA landscape input frame, but then the left and top portions of VGA input image frame are ignored (cropped). This results in only the lower right hand 480x320 corner being displayed.
For each of the input resolutions listed, the first parameter is the number of pixels in the horizontal (x-axis) and the second parameter is the number of pixels in the vertical (y-axis). 1.3.1.3 Pixel Format: (I2C: x06)
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www.ti.com BIT(S) 2:0 Select the pixel format: 0 - RGB565 (1) 1 - RGB666 (1) 2 - RGB888 (2) 3+ - RESERVED Spare Unused DESCRIPTION
15:3 31:16
(1) (2)
x0000
The splash screen interface uses RGB565 Internal test patterns and the BT.656 interface use RGB888
1.3.1.4
When this command is received by the projector, the data defines if the input image is rotated by -90 degrees on the DMD. This command is used when the portrait image is to be displayed as landscape.
BIT(S) 0 DESCRIPTION Image rotation (only used if input is 'portrait', should be set to 0 if input is landscape) 0 - no rotation (center image on DMD and pad w/ black bars) 1 - 90 degree rotation (input portrait is scaled and rotated on DMD) Spare Unused RESET b0 TYPE wr
15:1 31:16
x0000
Section 1.3.7 shows diagrams of the valid image rotation options. 1.3.1.5 Image Flip Long Axis: (I2C: x08)
When this command is received by the projector, the data defines if the input image is flipped across the long axis of the DMD.
BIT(S) 0 DESCRIPTION Flips image along long axis on DMD: 0 - Disable flip 1 - Enable flip Spare Unused RESET b1 TYPE wr
15:1 31:16
x0000
Flip Disabled
Flip Enabled
DMD
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1.3.1.6
When this command is received by the projector, the data defines if the input image is flipped across the short axis of the DMD.
BIT(S) 0 DESCRIPTION Flips image along short axis on DMD: 0 - Disable flip 1 - Enable flip Spare Unused RESET b1 TYPE wr
15:1 31:16
x0000
Flip Disabled
Flip Enabled
DMD
1.3.1.7 DMD Aspect Ratio: (I2C: x0A) This command modifies the scaling behavior of two specific Input Resolution command (I2C: x05) modes: QVGA Landscape (x1) and VGA Landscape (x5). Based on the value of the aspect ratio modification command, these two 4:3 aspect ratio input sources are either a) stretched horizontally slightly to fit the DMDs native 3:2 aspect ratio, or b) displayed in a 427x320 line sub-region of DMD, thereby preserving the 4:3 aspect ratio of the input source. For all other settings of Input Resolution command, this aspect ratio correction command has no effect.
BIT(S) 0 DESCRIPTION QVGA/VGA Landscape Mode Aspect Ratio Modification: 0 force 4:3 input aspect ratio source to fill 3:2 display 1 preserve 4:3 aspect ratio of source Spare Unused RESET b0 TYPE w
15:1 31:16
x0000
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1.3.1.8
15:4 31:16
x000
The test patterns are internally injected into the beginning of the image processing path. Therefore all image processing is performed on the test images. All command registers should be set up as if the test images are input from an external source. To achieve single pixel resolution for test images, the Input Resolution (I2C: x05) should be set to HVGA landscape (x3). The test pattern generator (TPG) generates the test patterns such that they mimic the resolution selected by the Input Resolution command (I2C: x05). For example, if NTSC landscape (720h*240v) is selected, then the TPG will input a 720x240 image into the image processing path. For typical test pattern usage, these command settings should be used: Input Source and Interface Mode: (I2C: x04) x1 - Internal Test Patterns Input Resolution: (I2C: x05) x3 - HVGA landscape (480h*320v) Pixel Format: (I2C: x06) x2 - RGB888 1.3.1.9 Pixel Interface Clock Edge: (I2C: x0C)
BIT(S) 0 DESCRIPTION Defines the clock edge (for PCLK) on which pixel data is sampled: 0 - Sample on falling edge 1 - Sample on rising edge Spare Unused RESET b1 TYPE wr
15:1 31:16
x0000
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b0
wr
b1
wr
15:3 31:16
x0000
15:10 31:16
x00
This command directly controls the pulse width of the red LED PWM modulation output pin. Equation 1 provides the approximate ungated LED current specifically for the light module included in the Pico 2.0 kit. The equation is not applicable for other external light modules.
ILED = 70 + 0.74 * (1023 unsigned(PWM(9:0))) mA, rms (1)
Note that choice of display mode also impacts total LED current and average power by gating the LED on periods during video frames via the R/G/B LED enable pins in the chipset. See Section 1.3.1.18 for further details. Care should be taken when using this command in practice. Depending on many system design dependent factors (including projector thermal design, LED specifications, selected display mode, etc.), recommended and absolute maximum settings will vary. 1.3.1.12 Green LED Current PWM Output Control: (I2C: x0F)
BIT(S) 9:0 DESCRIPTION Green LED current control PWM output pin duty cycle Valid range: x000 (0% PWM output pin duty cycle) to x3FF (100% PWM output pin duty cycle) Spare Unused RESET x3FF TYPE wr
15:10 31:16
x00
This command directly controls the pulse width of the green LED PWM modulation output pin. Equation 2 provides the approximate ungated LED current specifically for the light module included in the Pico 2.0 kit. The equation is not applicable for other external light modules.
ILED = 70 + 0.74 * (1023 unsigned(PWM(9:0))) mA, rms (2)
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Note that choice of display mode also impacts total LED current and average power by gating the LED on periods during video frames via the R/G/B LED enable pins in the chipset. See Section 1.3.1.18 for further details. Care should be taken when using this command in practice. Depending on many system design dependent factors (including projector thermal design, LED specifications, selected display mode, etc.), recommended and absolute maximum settings will vary. 1.3.1.13 Blue LED Current PWM Output Control: (I2C: x10)
BIT(S) 9:0 DESCRIPTION Blue LED current control PWM output pin duty cycle Valid range: x000 (0% PWM output pin duty cycle) to x3FF (100% PWM output pin duty cycle) Spare Unused RESET x3FF TYPE wr
15:10 31:16
x00
This command directly controls the pulse width of the blue LED PWM modulation output pin. Equation 3 provides the approximate ungated LED current specifically for the light module included in the Pico 2.0 kit. The equation is not applicable for other external light modules.
ILED = 70 + 0.74 * (1023 unsigned(PWM(9:0))) mA, rms (3)
Note that choice of display mode also impacts total LED current and average power by gating the LED on periods during video frames via the R/G/B LED enable pins in the chipset. See Section 1.3.1.18 for further details. Care should be taken when using this command in practice. Depending on many system design dependent factors (including projector thermal design, LED specifications, selected display mode, etc.), recommended and absolute maximum settings will vary. 1.3.1.14 Enable Red LED: (I2C: x11) When this command is received by the projector, the data defines if the Red LED is enabled.
BIT(S) 0 DESCRIPTION Enable red LED: 0 - disable LED / forces LED enable output pin to disable state 1 - enable LED / enable output pin toggles per color field sequential pattern as determined by Display Mode Select (I2C: x1F) setting Spare Unused RESET b1 TYPE wr
15:1 31:16
x0000
1.3.1.15 Enable Green LED: (I2C: x12) When this command is received by the projector, the data defines if the Green LED is enabled.
BIT(S) 0 DESCRIPTION Enable green LED: 0 - disable LED / forces LED enable output pin to disable state 1 - enable LED / enable output pin toggles per color field sequential pattern as determined by Display Mode Select (I2C: x1F) setting Spare Unused RESET b1 TYPE wr
15:1 31:16
x0000
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1.3.1.16 Enable Blue LED: (I2C: x13) When this command is received by the projector, the data defines if the Blue LED is enabled.
BIT(S) 0 DESCRIPTION Enable blue LED: 0 - disable LED / forces LED enable output pin to disable state 1 - enable LED / enable output pin toggles per color field sequential pattern as determined by Display Mode Select (I2C: x1F) setting Spare Unused RESET b1 TYPE wr
15:1 31:16
x0000
16
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1.3.1.17 Degamma Curve Select: (I2C: x1E) When this command is received by the projector, the chipset will load the selected degamma curve according to the table below. If an image is being displayed, momentary image corruption may be observable while the curve table update is proceeding. Shortly after power on reset, the chipset will load the reset default table.
BIT(S) 3:0 DESCRIPTION Degamma curve select: x0 - Degamma curve #1 (1) x1 - Degamma curve #2 (2) x2 - Degamma curve #3 (3) x3 - Degamma curve #4 (4) x4 to xF - RESERVED Spare Unused RESET x0 TYPE wr
15:4 31:16
(1) (2) (3) (4)
x000
Enhanced Graphics (power on reset default, an s-curve) recommended.. Power Law 2.2 (NTSC and also almost identical to sRGB except for very dark shades of colors) Power Law 2.5 (NTSC-like but tends to look better on projectors than Power Law 2.2) Linear (for test and structured light-mode applications. See Using Pico 2.0 Kit for Structured Light Applications, TI literature number DLPA021, for more details )
1.3.1.18 Display Mode Select: (I2C: x1F) When this command is received by the projector, the data defines the display mode selected.
BIT(S) 3:0 DESCRIPTION Normal Video/Graphics modes: x0 60 Hz video/graphics, LED duty cycles: R39%, G48%, B13% (1) (2) x1 60 Hz video/graphics, LED duty cycles: R40%, G45%, B15% (1) (2) x2 50 Hz video/graphics, LED duty cycles: R39%, G48%, B13% (1) (2) x3 50 Hz video/graphics, LED duty cycles: R40,% G45%, B15% (1) (2) External Pattern Structured Light modes: x4 120 Hz, 8 bit green only, LED duty cycles: R0%, G100%, B0% (3) (4) x5 180 Hz, 7 bit green only, LED duty cycles: R0%, G100%, B0% (3) (4) x6 1440 Hz, 1 bit green only, LED duty cycles: R0%, G100%, B0% (4) x7 120 Hz, 4 bit per color, LED duty cycles: R33%, G33%, B33% (4) x8 240 Hz, 2 bit per color, LED duty cycles: R33%, G33%, B33% (4) x9 480 Hz, 1 bit per color, LED duty cycles: R33%, G33%, B33% (4) Internal Stripe Pattern Structured Light modes: xA 1200Hz pattern rate, LED duty cycles: R33%, G33%, B33% (4) xB 2400Hz pattern rate, LED duty cycles: R33%, G33%, B33% (4) xC-xF RESERVED Spare Unused RESET x0 TYPE wr
15:4 31:16
(1)
x000
(2)
(3)
(4)
The LED duty cycles listed for each mode represent the percentage of net frame time allocated to each LED, determined by sequential gating of the R/G/B LED enable signals. (For example: R39% means that over a video frame period, 39% of the time the red LED will be enabled, 61% of the time it will be disabled.) To calculate net RMS current, ungated current levels supplied by the LED drive circuit should be multiplied by this duty cycle percentage for total average current. See Section 1.3.1.11 for more information about controlling LED current. 60 Hz modes support up to a maximum of 60.3 Hz. 50 Hz modes support up to a maximum of 50.3 Hz. Above these frame rates, subtle image anomalies may be observable. When using these 100% green duty cycle modes, Green LED current should be reduced to approximately 45% of the current levels associated with Normal Video/Graphics Display Modes (x0-x3 above). This is recommended to maintain similar thermal loading on green LED as found in normal modes. See Section 1.3.1.12 for more information about controlling LED current. These modes are specially designed to enable significant performance enhancements for structured light applications. See Using Pico 2.0 Kit for Structured Light Applications, TI literature number DLPA021, for more details.
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1.3.1.19 Sync Mode: (I2C: x24) When this command is received by the projector, the vertical synchronization method is selected.
BIT(S) 0
(1) (2) (3)
DESCRIPTION Sync mode 0 - Lock to internally generated vertical sync 1 - Lock to incoming vertical sync (frequency of the input source is 60Hz or 50Hz) Spare Unused
RESET b0
TYPE wr
3:1 31:4
(1)
b000
(2)
(3)
Generally, when displaying externally generated 50 Hz or 60 Hz sources, lock to incoming sync will produce the best results. In this mode, display frame reads are synchronous with input write frames. For input frames less than 50 Hz, or internal splash screens, or internal test patterns, internally generated sync mode should be used. If lock to incoming sync mode is selected but the source does not supply a valid vertical sync signal, the chipset will turn off the LEDs for protection after expiration of a watchdog timer.
1.3.1.20 Splash Image Select: (I2C: x25) When this command is received by the projector, one of the preloaded splash screen images is selected. Splash screens are stored in landscape QVGA format.
BIT(S) 3:0 DESCRIPTION Splash screen image select x0 - Splash image #1 x1 - Splash image #2 x2 - Splash image #3 x3 to xF - RESERVED Unused RESET x0 TYPE wr
31:4
To properly display a splash screen image, the following set of command settings should be used in addition to the image select command above: Input Source and Interface Mode: (I2C: x04) x2 - Splash Screen Input Resolution: (I2C: x05) x1 - QVGA landscape (320h*240v) Pixel Format: (I2C: x06) x0 RGB565 Sync Mode : (I2C: x24) x0 Lock to internally generated sync AGC Control: (I2C: x82) x0 AGC Disabled When returning to displaying input images from an external source, these registers should be subsequently returned to their original values. 1.3.1.21 Video/Graphics Enhancement Enable: (I2C: x26) When this command is received by the projector, video/graphics enhancement is turned on or off. Video/graphics enhancement function seeks to visually smooth discrete steps in gradually transitioning shades (such as facial skin tones). Video/graphics enhancement should be disabled for any non-periodic source or when using one of the structured light modes (see Section 1.3.1.18). Otherwise video/graphics enhancement should be enabled to maximize image quality.
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(1) (2)
3:1 31:4
(1)
b000
(2)
Video/graphics enhancement Enable recommended for us in all video/graphics modes to maximize image quality. Video/graphics enhancement should be disabled in all structured light Display Modes. See Using Pico 2.0 Kit for Structured Light Applications, TI literature number DLPA021, for more details
1.3.1.22 VSYNC DELAY: (I2C: x27) When this command is received by the projector, an adjustable delay on VSYNC can be added internal to the DLPC100. This delay is sometimes necessary if the vertical front porch in the input video is unusually short.
BIT(S) 14:0 DESCRIPTION VSYNC delay time interval (Used to effectively add vertical front porch to the external video/graphics input timing. Adjustments are in increments of four pixel clocks.) Valid range is x0000 to x7FFF RESERVED 15 31:16 Spare Unused b0 RESET x0000 TYPE w
1.3.1.23 Structured Light Output Display Inhibit: (I2C: x29) When this command is received by the projector, DMD output display will stop updating. For internally generated structured light patterns, it is necessary to toggle this command to ensure proper synchronization of output strobes. See Using Pico 2.0 Kit for Structured Light Applications, TI literature number DLPA021, for more details. CAUTION This command should not be used other than as recommended in the aforementioned application note. Leaving the display in the disabled state for a prolonged periods of time can result in device degradation. However, infrequent short durations in inhibit state (i.e., much less than one second) are harmless.
BIT(S) 0
DESCRIPTION Structured light output display inhibit 0 Disable output display processing 1 Enable output display processing Spare Unused
RESET b1
TYPE w
3:1 31:4
b000
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1.3.1.25 Structured Light Non-Linear Processing Inhibit: (I2C: x62) This command disables certain internal video processing blocks that perform non-linear actions on the video path. For normal video, these blocks are necessary to produce visually pleasing images. But, for structured light applications, it is desirable to have a straight forward linear relationship between projector input pixel data bits and light output.
BIT(S) 0 DESCRIPTION Structured Light Non-Linear Processing Inhibit (1) 0 Inhibit certain non-linear processing blocks to support linear input to output transfer function for structured light processing modes 1 Do not inhibit: all normal video processing blocks enabled, per governing command settings Spare Unused RESET b1 TYPE wr
3:1 31:4
(1)
See Using Pico 2.0 Kit for Structured Light Applications, TI literature number DLPA021, for more details.
DESCRIPTION Structured Light Auxiliary Output Signal Mux Control Valid selections: x00 normal x19 baseline structured light output configuration
RESET x00
TYPE w
31:8
(1)
Unused
See Using Pico 2.0 Kit for Structured Light Applications, TI literature number DLPA021, for more details.
DESCRIPTION
RESET b1
TYPE I
1 2 3 31:4
(1)
b1 b1 b0
I I
Should be disabled when using structured light modes. See Using Pico 2.0 Kit for Structured Light Applications, TI literature number DLPA021, for more details.
1.3.1.28 AGC Strength: (I2C: x85) The AGC adaptively gains up images on a frame-by-frame basis. This AGC Strength command sets the maximum gain that the AGC may apply to any input image frame.
BIT(S) 4:0 DESCRIPTION AGC Strength Maximum gain is equal to: ((STRENGTH+1)/32) * 4.0 Valid range is x00 to x1F. Spare Unused RESET x10 TYPE b
7:5 31:18
b000
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C1R1 C2R1 C3R1 C4R1 C5R1 C6R1 C7R1 C1R2 C2R2 C3R2 C4R2 C5R2 C6R2 C7R2 C1R3 C2R3 C3R3 C4R3 C5R3 C6R3 C7R3
1.3.2.1
DESCRIPTION
RESET b0
TYPE I
3:1 31:4
(1)
b000
Should be disabled when using structured light modes. See Using Pico 2.0 Kit for Structured Light Applications, TI literature number DLPA021, for more details.
1.3.2.2
1.3.2.3
1.3.2.4
1.3.2.5
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1.3.2.6
1.3.2.7
1.3.2.8
1.3.2.9
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b0
b0
11:10 31:12
b00
1.3.3.2
11:8 31:12
x0
1.3.3.3
11:8 31:12
x0
1.3.3.4
11:8
x0
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1.3.3.5
11:8 31:12
x0
31:8
1.3.4.2
31:8
1.3.4.3
31:8
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31:8
1.3.5.2
15 31:16
b0
1.3.5.3
15 31:16
b0
1.3.5.4
15 31:16
b0
1.3.5.5
15 31:16
b0
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Pattern Pointer = xA
Pattern Pointer = xB
Pattern Pointer = xC
Pattern Pointer = xD
Pattern Pointer = xE
(Pattern Pointer = xF invalid.) Synchronization strobes from the chipset mark the display times of these patterns, and can be used for camera/projector synchronization. See Using Pico 2.0 Kit for Structured Light Applications, TI literature number DLPA021, for more details. 1.3.6.1 Internal Structured Light Configuration Command: (I2C: xD2)
BIT(S) 0 DESCRIPTION Internal Structured Light Pattern Function Enable 0 - Disable 1 Enable Spare Internal Structured Light Pattern Count Number of structured light patterns minus one that will be displayed before pattern sequence repeats Spare RESET b0 TYPE w
3:1 8:4
b000 x00 w
11:9
b000
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1.3.6.2
31:8
1.3.6.3
31:8
1.3.6.4
31:8
1.3.6.5
31:8
1.3.6.6
1.3.6.7
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1.3.6.8
1.3.6.9
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1.3.7 Options for Input Image Resolutions/Orientations and DMD Displayed Images
FOR NORMAL IMAGE Scale factor: Height 1:1 Width 1:1 240
320
320
FOR ROTATED IMAGE Scale factor: Height 1:1.33 Width 1:1.50 240 480
320
320
QVGA Portrait (Addr x05 = x0) Rotation(90 degrees) (Addr x07 = x1)
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FOR NORMAL IMAGE Scale factor: Height 1:1.5 Width 1:1.5 320
480
320
FOR ROTATED IMAGE Scale factor: Height 1:1 Width 1:1 320 480
480
320
HVGA Portrait (Addr x05 = x2) Rotation(90 degrees) (Addr x07 = x1)
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FOR NORMAL IMAGE Scale factor: Height 1:0.5 Width 1:0.5 480
640
320
FOR ROTATED IMAGE Scale factor: Height 1.50:1 Width 1.33:1 480 480
640
320
VGA Portrait (Addr x05 = x4) Rotation(90 degrees) (Addr x07 = x1)
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Scale factor:
240
320
320
320
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Scale factor:
480
320
720
480
240
320
Figure 1-9. Landscape NTSC to HVGA 72x240 is the image size output by the TVP5150 video decoder for each 60Hz NTSC field. The image is only 240 lines tall because every other line is missing due to interlacing. The DLPC100 scales the field to create a full frame of data to display on the DMD at a 60Hz frame rate. The scaling operation achieves a low-cost method of deinterlacing.
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Scale factor:
720
480
288
320
Figure 1-10. Landscape PAL/SECAM to HVGA 72x288 is the image size output by the TVP5150 video decoder for each 60Hz PAL or SECAM field. The image is only 288 lines tall because every other line is missing due to interlacing. The DLPC100 scales the field to create a full frame of data to display on the DMD at a 50Hz frame rate. The scaling operation achieves a low-cost method of deinterlacing.
Scale factor: Height 1:1 Width 1:1 640 480
480
320
Figure 1-11. Landscape VGA Cropped to HVGA (Not Scaled) Input pixels within the HVGA input sub-image map one-for-one to pixels on the HVGA DMD. This is useful for inputting optical test patterns.
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Chapter 2
DLPU002A February 2010 Revised July 2010
2.1
Powerup
The Pico Chipset electronics and I2C command processor interface inside the DLPC100 will be initialized and ready to process commands 1.0 seconds after signal PWRGOOD goes high. Detailed power-up timing is given in the DLPC100 data sheet, TI literature number DLPS019 . Commands input prior to 1.0 second after PWRGOOD goes high may not be decoded properly.
2.2
Powerdown
No commands are required at power down of the Pico Chipset. The DC power supplies must be turned off, and PWRGOOD must be set low, according to the timing in the DLPC100 data sheet.
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Chapter 3
DLPU002A February 2010 Revised July 2010
Table 3-1 provides a quick reference summary of all available projector commands. Table 3-1.
I2C ADDRESS x04 x05 x06 x07 x08 x09 x0A x0B x0C x0D x0E x0F x10 x11 x12 x13 x14-1D x1E x1F x20-23 x24 x25 x26 x27 x28 x29 x2A-x3F x40 x41-x61 x62 x63-x7F x80 x81 x82
(1) (2)
REGISTER
(1)
SIZE 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 4 4 4 15 4 12 4 8 3
TYPE WR WR WR WR WR WR WR WR WR WR WR WR WR WR WR WR WR WR WR WR WR WR WR R WR WR WR
(2)
DEFAULT ACTION Splash QVGA landsc. RGB888 No rotate Disabled Disabled 3:2 (48x320) Checkerboard Rising edge DATEN high Min current Min current Min current Disabled Disabled Disabled Enhanced Gr. R39G48B13 Free Run Logo in Flash Disabled No delay Not Inhibited n/a Not Inhibited Normal Enabled
Input Source and Interface Mode Input Resolution Pixel Format Input Rotation (for portrait inputs only) Image Flip Long Axis Image Flip Short Axis Aspect Ratio Modification Internal Test Patterns Pixel Interface Clock Edge Pixel Interface Sync Polarity Red LED Driver Current Green LED Driver Current Blue LED Driver Current Enable Red LED Enable Green LED Enable Blue LED * RESERVED Degamma Curve Select Display Mode Select * RESERVED Sync Mode Splash Image Select Video/graphics enhancement Enable VSYNC Delay * RESERVED SL Output Display Inhibit * RESERVED Firmware Revision * RESERVED SL Non-Linear Processing Inhibit * RESERVED SL Aux Output Mux Setup * RESERVED AGC Control
RESERVED registers should never be written to. WR type is writeable and data is also readable. R type is read-only. Writes to these fields will have no effect. S type is a latched status bit. Reading a 1 in this field means that the signal has gone high since the last clear. Writing a 1 to this field clears the status bit. * RESERVED registers should never be written to. Command Quick Reference
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REGISTER
(1)
SIZE
TYPE
(2)
DEFAULT VALUE x10 x1 x400 x0C5 x099 x125 x400 x0ED x000 x000 x400 x000 x400 x400 x400 x000 x400 x400 x400 x000 x400 x400 x400 x00 x00 x00 x00 x00 x08 x10 x20 x40 x0001 x0001 x0001 x0001 x000 x00 x00 x00 x00
* RESERVED AGC Strength * RESERVED CCA Enable CCA Column 1 Row 1 Coefficient CCA Column 1 Row 2 Coefficient CCA Column 1 Row 3 Coefficient CCA Column 2 Row 1 Coefficient CCA Column 2 Row 2 Coefficient CCA Column 2 Row 3 Coefficient CCA Column 3 Row 1 Coefficient CCA Column 3 Row 2 Coefficient CCA Column 3 Row 3 Coefficient CCA Column 4 Row 1 Coefficient CCA Column 4 Row 2 Coefficient CCA Column 4 Row 3 Coefficient CCA Column 5 Row 1 Coefficient CCA Column 5 Row 2 Coefficient CCA Column 5 Row 3 Coefficient CCA Column 6 Row 1 Coefficient CCA Column 6 Row 2 Coefficient CCA Column 6 Row 3 Coefficient CCA Column 7 Row 1 Coefficient CCA Column 7 Row 2 Coefficient CCA Column 7 Row 3 Coefficient * RESERVED SL Auxiliary Control Register SL Aux Input Bit 0 Control SL Aux Input Bit 1 Control * RESERVED SL Aux Input Bit 4 Control SL Aux Input Bit 5 Control * RESERVED Red LED Enable Mask Green LED Enable Mask Blue LED Enable Mask SL Aux Internal Pattern Sync Control SL Aux Internal Bit 4 Delay SL Aux Internal Bit 4 Pulse Width SL Aux Internal Bit 5 Delay SL Aux Internal Bit 5 Pulse Width * RESERVED Internal Structured Light Config Internal SL Inversion Mask 1 Internal SL Inversion Mask 2 Internal SL Inversion Mask 3 Internal SL Inversion Mask 4 12 8 8 8 8 WR WR WR WR WR Disabled No inversion No inversion No inversion No inversion 8 8 8 8 16 16 16 16 WR WR WR WR WR WR WR WR 8 8 WR WR Normal Normal 8 8 8 WR WR WR n/a Normal Normal 1 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 WR WR WR WR WR WR WR WR WR WR WR WR WR WR WR WR WR WR WR WR WR WR 5 WR
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SIZE 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
TYPE WR WR WR WR WR WR WR WR WR WR WR WR WR WR WR WR
(2)
DEFAULT VALUE x00 x00 x00 x00 x00 x00 x00 x00 x00 x00 x00 x00 x00 x00 x00 x00
DEFAULT ACTION Pattern 0 Pattern 0 Pattern 0 Pattern 0 Pattern 0 Pattern 0 Pattern 0 Pattern 0 Pattern 0 Pattern 0 Pattern 0 Pattern 0 Pattern 0 Pattern 0 Pattern 0 Pattern 0
Internal SL Pattern Pointer 1 Internal SL Pattern Pointer 2 Internal SL Pattern Pointer 3 Internal SL Pattern Pointer 4 Internal SL Pattern Pointer 5 Internal SL Pattern Pointer 6 Internal SL Pattern Pointer 7 Internal SL Pattern Pointer 8 Internal SL Pattern Pointer 9 Internal SL Pattern Pointer 10 Internal SL Pattern Pointer 11 Internal SL Pattern Pointer 12 Internal SL Pattern Pointer 13 Internal SL Pattern Pointer 14 Internal SL Pattern Pointer 15 Internal SL Pattern Pointer 16 * RESERVED
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REVISION HISTORY
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REVISION HISTORY
REVISION * A DATE 2/2010 7/2010 SECTION(S) All 1.3.1.26 Revision History Initial release Bit(7:0) description corrected Added Revision History table COMMENT
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
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Revision History
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