FUJITSU SEMICONDUCTOR DATA SHEET

DS07-12531-2E

8-bit Proprietary Microcontroller

CMOS

F2MC-8L MB89630R Series

MB89635R/T635R/636R/637R/T637R MB89P637/W637/PV630
s OUTLINE
The MB89630R series has been developed as a general-purpose version of the F2MC*-8L family consisting of proprietary 8-bit, single-chip microcontrollers. In addition to a compact instruction set, the microcontrollers contain a variety of peripheral functions such as dual-clock control system, five operating speed control stages, a UART, timers, a PWM timer, a serial interface, an A/D converter, an external interrupt, and a watch prescaler. *: F2MC stands for FUJITSU Flexible Microcontroller.

s FEATURES
High-speed operating capability at low voltage Minimum execution time: 0.4 s@3.5 V, 0.8 s@2.7 V F2MC-8L family CPU core Multiplication and division instructions 16-bit arithmetic operations Test and branch instructions Bit manipulation instructions, etc.

Instruction set optimized for controllers

Five types of timers 8-bit PWM timer: 2 channels (Also usable as a reload timer) 8-bit pulse-width count timer (Continuous measurement capable, applicable to remote control, etc.) 16-bit timer/counter 21-bit timebase timer UART CLK-synchronous/CLK-asynchronous data transfer capable (6, 7, and 8 bits) Serial interface Switchable transfer direction to allows communication with various equipment. 10-bit A/D converter Start by an external input capable

(Continued)

This datasheet has been downloaded from http://www.digchip.com at this page

MB89630R Series
(Continued) External interrupt: 4 channels Four channels are independent and capable of wake-up from low-power consumption modes (with an edge detection function). Low-power consumption modes Stop mode (Oscillation stops to minimize the current consumption.) Sleep mode (The CPU stops to reduce the current consumption to approx. 1/3 of normal.) Subclock mode Watch mode Bus interface function With hold and ready function

s PACKAGE
64-pin Plastic SH-DIP 64-pin Plastic QFP 64-pin Plastic QFP

(DIP-64P-M01)

(FPT-64P-M06)

(FPT-64P-M09)

64-pin Ceramic SH-DIP

64-pin Ceramic MQFP

64-pin Ceramic MDIP

(DIP-64C-A06)

(MQP-64C-P01)

(MDP-64C-P02)

MB89630R Series
s PRODUCT LINEUP
Part number Item

MB89635R MB89636R MB89637R MB89T635R MB89T637R MB89P637 MB89W637 MB89PV630

Classification Mass-produced products (mask ROM products) External ROM products One-time PROM product

Piggyback/ evaluation EPROM product (for product evaluation and development)

ROM size

16 K 8 bits 24 K 8 bits 32 K 8 bits 32 K 8 bits (internal (internal (internal (Internal PROM, to be 32 K 8 bits mask ROM) mask ROM) mask ROM) Fixed to external ROM programmed with (external general-purpose ROM) EPROM programmer)

RAM size CPU functions

512 8 bits 768 8 bits 1024 8 bits 512 8 bits The number of instructionns: Instruction bit length: Instruction length: Data bit length: Minimum execution time: Interrupt processing time: Input ports: Output ports (N-ch open-drain): I/O ports (N-ch open-drain): Output ports (CMOS): I/O ports (CMOS): Total:

1024 8 bits

1 K 8 bits

136 8 bits 1 to 3 bytes 1, 8, 16 bits 0.4 to 6.4 s/10 MHz, 61 s@32.768 kHz 3.6 to 57.6 s/10 MHz, 562.5 s@32.768 kHz 5 (All also serve as peripherals.) 8 (All also serve as peripherals.) 4 (All also serve as peripherals.) 8 (All also serve as bus control.) 28 (27 ports also serve as bus pins and peripherals.) 53

Ports

Clock timer 8-bit PWM timer 8-bit pulse width count timer 16-bit timer/ counter 8-bit serial I/O

21 bits 1 (in main clock)/15 bits 1 (at 32.768 kHz) 8-bit reload timer operation (toggled output capable, operating clock cycle: 0.4 s to 3.3 ms) 2 channels 7/8-bit resolution PWM operation (conversion cycle: 51.2 s to 839 ms) 2 channels 8-bit timer operation (overflow output capable, operating clock cycle: 0.4 to 12.8 s) 8-bit reload timer operation (toggled output capable, operating clock cycle: 0.4 to 12.8 s) 8-bit pulse width measurement operation (capable of continuous measurement, and measurement of H pulse width/ L pulse width/ from to /from to ) 16-bit timer operation (operating clock cycle: 0.4 s) 16-bit event counter operation (rising edge/falling edge/both edge selectable) 8 bits LSB first/MSB first selectable One clock selectable from four transfer clocks (one external shift clock, three internal shift clocks: 0.8 s, 3.2 s, 12.8 s) Capable of switching two I/O systems by software Transfer data length (6, 7, and 8 bits) Transfer rate (300 to 62500 bps. at 10 MHz osciliation) 10-bit resolution 8 channels A/D conversion mode (conversion time: 13.2 s) Sense mode (conversion time: 7.2 s) Capable of continuous activation by an external activation or an internal timer

UART

10-bit A/D converter

(Continued)
3

MB89630R Series
(Continued)
Part number Item

MB89635R MB89636R MB89637R MB89T635R MB89T637R MB89P637 MB89W637 MB89PV630

External interrupt input Standby mode Process Operating voltage* EPROM for use

4 independent channels (edge selection, interrupt vector, source flag). Rising edge/falling edge selectable Used also for wake-up from stop/sleep mode. (Edge detection is also permitted in stop mode.) Sleep mode, stop mode, watch mode, and subclock mode CMOS 2.2 V to 6.0 V 2.7 V to 6.0 V
MBM27C256A-20CZ MBM27C256A-20TV

* : Varies with conditions such as the operating frequency. (See section s Electrical Characteristics.) In the case of the MB89PV630, the voltage varies with the restrictions of the EPROM for use.

s PACKAGE AND CORRESPONDING PRODUCTS

Package DIP-64P-M01 FPT-64P-M06 FPT-64P-M09 DIP-64C-A06 MQP-64C-P01 MDP-64C-P02 : Available * MB89635R MB89T635R MB89636R MB89637R MB89T637R MB89P637 MB89W637 * MB89PV630 *

: Not available

* : To convert pin pitches, an adapter socket (manufacturer: Sun Hayato Co., Ltd.) is available. 64SD-64QF2-8L: For conversion from (DIP-64P-M01, DIP-64C-A06, or MDP-64C-P02) to FPT-64P-M09 Inquiry: Sun Hayato Co., Ltd.: TEL (81)-3-3986-0403 FAX (81)-3-5396-9106 Note: For more information about each package, see section s Package Dimensions.

MB89630R Series
s DIFFERENCES AMONG PRODUCTS
1. Memory Size
Before evaluating using the piggyback product, verify its differences from the product that will actually be used. Take particular care on the following points: On the MB89P637/W637, the program area starts from address 8007H but on the MB89PV630 and MB89637R starts from 8000H. On the MB89P637/W637, addresses 8000H to 8006H comprise the option setting area, option settings can be read by reading these addresses. On the MB89PV630/MB89637R, addresses 8000H to 8006H could also be used as a program ROM. However, do not use these addresses in order to maintain compatibility of the MB89P637/W637. The stack area, etc., is set at the upper limit of the RAM. The external area is used.

2. Current Consumption
In the case of the MB89PV630, add the current consumed by the EPROM which connected to the top socket. When operated at low speed, the product with an OTPROM (one-time PROM) or an EPROM will consume more current than the product with a mask ROM. However, the current consumption in sleep/stop modes is the same. (For more information, see sections s Electrical Characteristics and s Example Characteristics.)

3. Mask Options
Functions that can be selected as options and how to designate these options vary by the product. Before using options check section s Mask Options. Take particular care on the following points: A pull-up resistor cannot be set for P50 to P53 on the MB89P637 and MB89W637. Options are fixed on the MB89PV630, MB89T635R, and MB89T637R.

4. Differences between the MB89630 and MB89630R Series

Memory access area There are no difference between the access area of MB89635/MB89635R, and that of MB89637/MB89637R. The access area of MB89636 is different from that of the MB89636R when using in external bus mode. Address 0000H to 007FH 0080H to 037FH 0380H to 047FH 0480H to 7FFFH 8000H to 9FFFH A000H to FFFFH ROM area External area I/O area RAM area Memory area MB89636 I/O area RAM area Access prohibited External area Access prohibited ROM area MB89636R

MB89630R Series
Other specifications Both MB89630 series and MB89630R is the same. Electrical specifications/electrical characteristics Electrical specifications of the MB89630R series are the same as that of the MB89630 series. Electrical characteristics of both the series are much the same.

s CORRESPONDENCE BETWEEN THE MB89630 AND MB89630R SERIES

The MB89630R series is the reduction version of the MB89630 series. The the MB89630 and MB89630R series consist of the following products:
MB89630 series MB89635 MB89T635 MB89636 MB89637 MB89T637 MB89T637R

MB89630R series MB89635R MB89T635R MB89636R MB89637R

MB89P637 MB89W637 MB89PV630

MB89630R Series
s PIN ASSIGNMENT
(Top view) P31/UO1 P30/UCK1 P43/PTO1 P42/UI2 P41/UO2 P40/UCK2 P53/PTO2 P52 P51/BZ P50/ADST P60/AN0 P61/AN1 P62/AN2 P63/AN3 P64/AN4 P65/AN5 P66/AN6 P67/AN7 AVCC AVR AVSS P74/EC P73/INT3 P72/INT2 P71/INT1/X0A* P70/INT0/X1A* RST MOD0 MOD1 X0 X1 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 92 61 91 60 90 59 89 58 88 57 87 56 86 55 85 54 84 53 83 52 82 51 81 50 80 49 79 48 47 46 45 44 Each pin inside 43 the dashed line is 42 for MB89PV630 only. 41 40 39 38 37 36 35 34 33 VCC A14 A13 A8 A9 A11 OE A10 CE O8 O7 O6 O5 O4 VCC P32/UI1 P33/SCK1 P34/SO1 P35/SI1 P36/PWC P37/WTO VSS P00/AD0 P01/AD1 P02/AD2 P03/AD3 P04/AD4 P05/AD5 P06/AD6 P07/AD7 P10/A08 P11/A09 P12/A10 P13/A11 P14/A12 P15/A13 P16/A14 P17/A15 P20/BUFC P21/HAK P22/HRQ P23/RDY P24/CLK P25/WR P26/RD P27/ALE

VPP A12 A7 A6 A5 A4 A3 A2 A1 A0 O1 O2 O3 VSS

65 66 67 68 69 70 71 72 73 74 75 76 77 78

(DIP-64P-M01) (DIP-64C-A06) (MDP-64C-P02)

(Top view)

*: When the dual-clock system is selected.

P51/BZ P50/ADST P60/AN0 P61/AN1 P62/AN2 P63/AN3 P64/AN4 P65/AN5 P66/AN6 P67/AN7 AVCC AVR AVSS P74/EC P73/INT3 P72/INT2

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

P52 P53/PTO2 P40/UCK2 P41/UO2 P42/UI2 P43/PTO1 P30/UCK1 P31/UO1 VCC P32/UI1 P33/SCK1 P34/SO1 P35/SI1 P36/PWC P37/WTO VSS

P00/AD0 P01/AD1 P02/AD2 P03/AD3 P04/AD4 P05/AD5 P06/AD6 P07/AD7 P10/A08 P11/A09 P12/A10 P13/A11 P14/A12 P15/A13 P16/A14 P17/A15

P71/INT1/X0A* P70/INT0/X1A* RST MOD0 MOD1 X0 X1 VSS P27/ALE P26/RD P25/WR P24/CLK P23/RDY P22/HRQ P21/HAK P20/BUFC (FPT-64P-M09) *: When the dual-clock system is selected.

MB89630R Series

(Top view) P53/PTO2 P40/UCK2 P41/UO2 P42/UI2 P43/PTO1 P30/UCK1 P31/UO1 VCC P32/UI1 P33/SCK1 P34/SO1 P35/SI1 P36/PWC P52 P51/BZ P50/ADST P60/AN0 P61/AN1 P62/AN2 P63/AN3 P64/AN4 P65/AN5 P66/AN6 P67/AN7 AVCC AVR AVSS P74/EC P73/INT3 P72/INT2 P71/INT1/X0A* P70/INT0/X1A* 1 2 3 4 5 6 85 77 7 86 76 8 87 75 9 88 74 10 89 73 11 90 72 12 91 71 13 92 70 14 93 69 15 16 17 18 19 Each pin inside the dashed line is for MB89PV630 only. 20 21 22 23 24 25 26 27 28 29 30 31 32 94 95 96 65 66 67 68 84 83 82 81 80 79 78 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

P37/WTO VSS P00/AD0 P01/AD1 P02/AD2 P03/AD3 P04/AD4 P05/AD5 P06/AD6 P07/AD7 P10/A08 P11/A09 P12/A10 P13/A11 P14/A12 P15/A13 P16/A14 P17/A15 P20/BUFC

RST MOD0 MOD1 X0 X1 VSS P27/ALE P26/RD P25/WR P24/CLK P23/RDY P22/HRQ P21/HAK (FPT-64P-M06) (MQP-64C-P01) *: When the dual-clock system is selected.

Pin assignment on package top (MB89PV630 only) Pin no. 65 66 67 68 69 70 71 72 Pin name N.C. VPP A12 A7 A6 A5 A4 A3 Pin no. 73 74 75 76 77 78 79 80 Pin name A2 A1 A0 N.C. O1 O2 O3 VSS Pin no. 81 82 83 84 85 86 87 88 Pin name N.C. O4 O5 O6 O7 O8 CE A10 Pin no. 89 90 91 92 93 94 95 96 Pin name OE N.C. A11 A9 A8 A13 A14 VCC

N.C.: Internally connected. Do not use. 8

MB89630R Series
s PIN DESCRIPTION
Pin no. SH-DIP*1 MDIP*2 30 31 28 29 27 QFP2*3 22 23 20 21 19 QFP1*4 MQFP*5 23 24 21 22 20 X0 X1 MOD0 MOD1 RST C D Operating mode selection pins Connect directly to VCC or VSS. Reset I/O pin This pin is an N-ch open-drain output type with a pull-up resistor, and a hysteresis input type. L is output from this pin by an internal reset source. The internal circuit is initialized by the input of L. General-purpose I/O ports When an external bus is used, these ports function as the multiplex pins of the lower address output and the data I/O. General-purpose I/O ports When an external bus is used, these ports function as an upper address output. General-purpose output port When an external bus is used, this port can also be used as a buffer control output by setting the BCTR. General-purpose output port When an external bus is used, this port can also be used as a hold acknowledge by setting the BCTR. General-purpose output port When an external bus is used, this port can also be used as a hold request input by setting the BCTR. General-purpose output port When an external bus is used, this port functions as a ready input. General-purpose output port When an external bus is used, this port functions as a clock output. General-purpose output port When an external bus is used, this port functions as a write signal output. General-purpose output port When an external bus is used, this port functions as a read signal output. Pin name Circuit type A Function Main clock crystal oscillator pins

56 to 49

48 to 41

49 to 42 P00/AD0 to P07/AD7

48 to 41

40 to 33

41 to 34 P10/A08 to P17/A157 33 P20/BUFC

40

32

39

31

32

P21/HAK

38

30

31

P22/HRQ

37

29

30

P23/RDY

36

28

29

P24/CLK

35

27

28

P25/WR

34

26

27

P26/RD

*1: DIP-64P-M01, DIP-64C-A06 *2: MDP-64C-P02 *3: FPT-64P-M09

*4: FPT-64P-M06 *5: MQP-M64C-P01

(Continued)

MB89630R Series
(Continued)
Pin no. SH-DIP MDIP*2 33
*1

QFP2*3 25

QFP1*4 MQFP*5 26

Pin name P27/ALE

Circuit type H

Function General-purpose output port When an external bus is used, this port functions as an address latch signal output. General-purpose I/O port Also serves as the clock I/O 1 for the UART. This port is a hysteresis input type. General-purpose I/O port Also serves as the data output 1 for the UART. General-purpose I/O port Also serves as the data input 1 for the UART. This port is a hysteresis input type. General-purpose I/O port Also serves as the data input for the 8-bit serial I/O. This port is a hysteresis input type. General-purpose I/O port Also serves as the data output for the 8-bit serial I/O. General-purpose I/O port Also serves as the data input for the 8-bit serial I/O. This port is a hysteresis input type. General-purpose I/O port Also serves as the measured pulse input for the 8-bit pulse width counter. This port is a hysteresis input type. General-purpose I/O port Also serves as the toggle output for the 8-bit pulse width counter. General-purpose I/O port Also serves as the clock I/O 2 for the UART. This port is a hysteresis input type. General-purpose I/O port Also serves as the data output 2 for the UART. General-purpose I/O port Also serves as the data input 2 for the UART. This port is a hysteresis input type. General-purpose I/O port Also serves as the toggle output for the 8-bit PWM timer. General-purpose I/O port Also serves as an A/D converter external activation. This port is a hysteresis input type.

58

59

P30/UCK1

1 63

57 55

58 56

P31/UO1 P32/UI1

F G

62

54

55

P33/SCK1

61

53

54

P34/SO1

60

52

53

P35/SI1

59

51

52

P36/PWC

58

50

51

P37/WTO

62

63

P40/UCK2

5 4

61 60

62 61

P41/UO2 P42/UI2

F G

59

60

P43/PTO1

10

P50/ADST

*1: DIP-64P-M01, DIP-64C-A06 *2: MDP-64C-P02 *3: FPT-64P-M09 10

*4: FPT-64P-M06 *5: MQP-M64C-P01

(Continued)

MB89630R Series
(Continued)
Pin no. SH-DIP*1 MDIP*2 9 8 7 QFP2 1 64 63
*3

QFP1*4 MQFP*5 2 1 64

Pin name P51/BZ P52 P53/PTO2

Circuit type J J J

Function General-purpose I/O port Also serves as a buzzer output. General-purpose I/O port General-purpose I/O port Also serves as the toggle output for the 8-bit PWM timer. N-ch open-drain output ports Also serve as an A/D converter analog input. Input-only ports These ports are a hysteresis input type. Also serve as an external interrupt input (at singleclock operation). Subclock crystal oscillator pins (at dual-clock operation) Input-only ports Also serve as an external interrupt input. These ports are a hysteresis input type. General-purpose input port Also serves as the external clock input for the 16-bit timer/counter. This port is a hysteresis input type. Power supply pin Power supply (GND) pin A/D converter power supply pin A/D converter reference voltage input pin A/D converter power supply pin Use this pin at the same voltage as VSS.

11 to 18 26, 25

3 to 10 18, 17

4 to 11 19, 18

P60/AN0 to P67/AN7 P70/INT0/X1A, P71/INT1/X0A

I B/E

24, 23 22

16, 15 14

17, 16 15

P72/INT2, P73/INT3 P74/EC

64 32, 57 19 20 21

56 24,49 11 12 13

57 25, 50 12 13 14

VCC VSS AVCC AVR AVSS

*1: DIP-64P-M01, DIP-64C-A06 *2: MDP-64C-P02 *3: FPT-64P-M09

*4: FPT-64P-M06 *5: MQP-M64C-P01

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MB89630R Series
External EPROM pins (MB89PV630 only) Pin no. MDIP 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 MQFP 66 67 68 69 70 71 72 73 74 75 77 78 79 80 82 83 84 85 86 87 88 89 91 92 93 94 95 96 65 76 81 90 Pin name VPP A12 A7 A6 A5 A4 A3 A2 A1 A0 O1 O2 O3 VSS O4 O5 O6 O7 O8 CE A10 OE A11 A9 A8 A13 A14 VCC N.C. I/O O O H level output pin Address output pins Function

Data input pins

O I

Power supply (GND) pin Data input pins

O O O O

ROM chip enable pin Outputs H during standby. Address output pin ROM output enable pin Outputs L at all times. Address output pins

O O O EPROM power supply pin Internally connected pins Be sure to leave them open.

12

MB89630R Series
s I/O CIRCUIT TYPE
Type A
X1

Circuit

Remarks Crystal or ceramic oscillation type (main clock) External clock input selection versions of MB89PV630, MB89P637, MB89W637, MB89635R, MB89T635R, MB89636R, MB89637R, and MB89T637R At an oscillation feedback resistor of approximately 1 M@5.0 V

X0

Standby control signal

B
X1A

X0A

Crystal or ceramic oscillation type (subclock) MB89PV630, MB89P637, MB89W637, MB89635R, MB89636R, and MB89637R with dual-clock system At an oscillation feedback resistor of approximately 4.5 M@5.0 V

Standby control signal

C
R P-ch

At an output pull-up resistor (P-ch) of approximately 50 k@5.0 V Hysteresis input

N-ch

D E
R

Hysteresis input

Pull-up resistor optional (except P70 and P71) F

R P-ch P-ch

CMOS output CMOS input

N-ch

Pull-up resistor optional (except P22 and P23)

(Continued)

13

MB89630R Series
(Continued)
Type G
R P-ch P-ch

Circuit CMOS output Hysteresis input

Remarks

N-ch

Pull-up resistor optional H

P-ch

CMOS output

N-ch

I
N-ch Analog input

Analog input

J
R P-ch

CMOS input

N-ch

Pull-up resistor optional K

R P-ch

Hysteresis input

N-ch

Pull-up resistor optional

14

MB89630R Series
s HANDLING DEVICES
1. Preventing Latchup
Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins other than medium- and high-voltage pins or if higher than the voltage which shows on 1. Absolute Maximum Ratings in section s Electrical Characteristics is applied between VCC and VSS. When latchup occurs, power supply current increases rapidly and might thermally damage elements. When using, take great care not to exceed the absolute maximum ratings. Also, take care to prevent the analog power supply (AVCC and AVR) and analog input from exceeding the digital power supply (VCC) when the analog system power supply is turned on and off.

2. Treatment of Unused Input Pins

Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down resistor.

3. Treatment of Power Supply Pins on Microcontrollers with A/D and D/A Converters
Connect to be AVCC = DAVC = VCC and AVSS = AVR = VSS even if the A/D and D/A converters are not in use.

4. Treatment of N.C. Pins

Be sure to leave (internally connected) N.C. pins open.

5. Power Supply Voltage Fluctuations

Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is therefore important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations (P-P value) will be less than 10% of the standard VCC value at the commercial frequency (50 Hz to 60 Hz) and the transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched.

6. Precautions when Using an External Clock

When an external clock is used, oscillation stabilization time is required even for power-on reset (option selection) and wake-up from stop mode.

15

MB89630R Series
s PROGRAMMING TO THE EPROM ON THE MB89P637
The MB89P637 is an OTPROM version of the MB89630 series.

1. Features
32-Kbytes PROM on chip Options can be set using the EPROM programmer. Equivalency to the MBM27C256A in EPROM mode (when programmed with the EPROM programmer)

2. Memory Space
Memory space in each mode is illustrated below.
Normal operating mode
0000H I/O 0080H 0100H Register 0200H RAM

EPROM mode (Corresponding addresses on the EPROM programmer)

0480H External area 8000H Option setting area 8007H 0007H 0000H Option setting area

PROM 32 KB

Program area (EPROM) 32 KB

FFFFH

7FFFH

3. Programming to the EPPROM

In EPROM mode, the MB89P637 functions equivalent to the MBM27C256A. This allows the PROM to be programmed with a general-purpose EPROM programmer by using the dedicated socket adapter. However, the electronic signature mode cannot be used. When the operating ROM area for a single chip is 32 Kbytes (8007H to FFFFH) the EPROM can be programmed as follows:

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MB89630R Series
Programming procedure (1) Set the EPROM programmer to the MBM27C256A-20CZ and MBM27C256A-20TV. (2) Load program data into the EPROM programmer at 0007H to 7FFFH. (Note that addresses 8000H to FFFFH in the operating mode assign to 0000H to 7FFFH in EPROM mode). (3) Load option data into addresses 0000H to 0006H of the EPROM programmer. (For information about each corresponding option, see 8. OTPROM Option Bit Map.) (4) Program with the EPROM programmer.

4. Recommended Screening Conditions

High-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked OTPROM microcomputer program.
Program, verify

Aging +150C, 48 Hrs.

Data verification

Assembly

5. Programming Yield
All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature. For this reason, a programming yield of 100% cannot be assured at all times.

6. Erasure
In order to clear all locations of their programmed contents, it is necessary to expose the internal EPROM to an ultraviolet light source. A dosage of 10 W-seconds/cm2 is required to completely erase an internal EPROM. This dosage can be obtained by exposure to an ultraviolet lamp (wavelength of 2537 Angstroms ()) with intensity of 12000 W/cm2 for 15 to 21 minutes. The internal EPROM should be about one inch from the source and all filters should be removed from the UV light source prior to erasure. It is important to note that the internal EPROM and similar devices, will erase with light sources having wavelengths shorter than 4000 . Although erasure time will be much longer than with UV source at 2537 , nevertheless the exposure to fluorescent light and sunlight will eventually erase the internal EPROM, and exposure to them should be prevented to realize maximum system reliability. If used in such an environment, the package windows should be covered by an opaque label or substance.

17

MB89630R Series
7. EPROM Programmer Socket Adapter
Part No. Package Compatible socket adapter Sun Hayato Co., Ltd. MB89P637-SH SH-DIP-64 ROM-64SD-28DP-8L MB89P637PF QFP-64 ROM-64QF-28DP-8L

Inquiry: Sun Hayato Co., Ltd.: TEL : (81)-3-3986-0403 FAX : (81)-3-5396-9106

8. OTPROM Option Bit Map

Address

0000H

0001H

0002H

0003H

0004H

0005H

Bit 3 Reset pin output 1: Yes 0: No P07 P06 P05 P04 P03 Pull-up Pull-up Pull-up Pull-up Pull-up 1: No 1: No 1: No 1: No 1: No 0: Yes 0: Yes 0: Yes 0: Yes 0: Yes P17 P16 P15 P14 P13 Pull-up Pull-up Pull-up Pull-up Pull-up 1: No 1: No 1: No 1: No 1: No 0: Yes 0: Yes 0: Yes 0: Yes 0: Yes P37 P36 P35 P34 P33 Pull-up Pull-up Pull-up Pull-up Pull-up 1: No 1: No 1: No 1: No 1: No 0: Yes 0: Yes 0: Yes 0: Yes 0: Yes Vacancy Vacancy Vacancy Vacancy P43 Pull-up Readable Readable Readable Readable 1: No and writable and writable and writable and writable 0: Yes Vacancy Vacancy Vacancy P74 P73 Pull-up Pull-up Readable Readable Readable 1: No 1: No and writable and writable and writable 0: Yes 0: Yes
Vacancy Single/dualclock system Readable Readable Readable 1: Dual clock and writable and writable and writable 0: Single clock Vacancy Vacancy Vacancy Vacancy Vacancy Vacancy Vacancy

Bit 7

Bit 6

Bit 5

Bit 4

Bit 2 Power-on reset 1: Yes 0: No P02 Pull-up 1: No 0: Yes P12 Pull-up 1: No 0: Yes P32 Pull-up 1: No 0: Yes P42 Pull-up 1: No 0: Yes P72 Pull-up 1: No 0: Yes
Vacancy

Bit 1

Bit 0

Oscillation stabilization (/FCH)

11:218/FCH 01:217/FCH 10:214/FCH 00:24/FCH P01 P00 Pull-up Pull-up 1: No 1: No 0: Yes 0: Yes P11 P10 Pull-up Pull-up 1: No 1: No 0: Yes 0: Yes P31 P30 Pull-up Pull-up 1: No 1: No 0: Yes 0: Yes P41 P40 Pull-up Pull-up 1: No 1: No 0: Yes 0: Yes
Vacancy Vacancy Readable Readable and writable and writable Vacancy Reserved bit

0006H

Readable Readable Readable Readable Readable Readable Readable Readable and writable and writable and writable and writable and writable and writable and writable and writable

Note: Each bit is set to 1 as the initialized value.

18

MB89630R Series
s PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE
1. EPROM for Use
MBM27C256A-20CZ, MBM27C256A-20TV

2. Programming Socket Adapter

To program to the PROM using an EPROM programmer, use the socket adapter (manufacturer: Sun Hayato Co., Ltd.) listed below. Package LCC-32 (Rectangle) Adapter socket part number ROM-32LC-28DP-YG

Inquiry: Sun Hayato Co., Ltd.: TEL: (81)-3-3986-0403 FAX : (81)-3-5396-9106

3. Memory Space
Memory space in each mode, such as 32-Kbyte PROM, option area is diagrammed below.
Address 0000H I/O 0080H RAM 0480H Not available 8000H Not available 8007H 0007H 0000H Not available Single chip Corresponding addresses on the EPROM programmer

PROM 32 KB

EPROM 32 KB

FFFFH

7FFFH

4. Programming to the EPROM

(1) Set the EPROM programmer to the MBM27C256A. (2) Load program data into the EPROM programmer at 0007H to 7FFFH. (3) Program to 0000H to 7FFFH with the EPROM programmer.

19

MB89630R Series
s BLOCK DIAGRAM

X0 X1

Main clock oscillator

X0A X1A

Subclock oscillator (32.768 kHz)

21-bit timebase timer

Clock controller

CMOS I/O port P 3 7 / WT O P 3 6 / P WC P35/SI1 P34/SO1 P33/SCK1 P32/UI1 P31/UO1 P 3 0 / U C K1 UART P 4 0 / U C K2 P41/UO2 P42/UI2

RST

Reset circuit (Watchdog timer) Internal data bus

8-bit PWC timer

Watch prescaler

P00 /AD0 to P07 /AD7 P10 /A08 to P1 7/A1 5 MOD0 MOD1 P27 /ALE P26 /RD P25 /WR P24 /CLK P23 /RDY P22 /HRQ P21 /HAK P20 /BUFC

Port0 and port1

CMOS I/O port

External bus interface

UART baud rate generator

CMOS I/O port Port 2 N-ch open-drain I/O port CMOS output port

Port 4

Port 3

8-bit serial I/O

P 4 3 / P T O1

Buzzer output RAM 10-bit A/D converter F 2 M C- 8L CPU 8 Port 6 3 8

Port 5

8-bit PWM timer

P 5 3 / P T O2 P52 P51/BZ P50/ADST A V CC, A V SS , AVR P60/AN0 to P67/AN7

N-ch open-drain output port RO M Input port External interrupt Other pins VCC 2, VSS 2 4

16-bit timer/counter

Port 7

P70/INT0 P71/INT1 P72/INT2 P73/INT3

P74/EC

20

MB89630R Series
s CPU CORE
1. Memory Space
The microcontrollers of the MB89630R series offer 64 Kbytes of memory for storing all of I/O, data, and program areas. The I/O area is located at the lowest address. The data area is provided immediately above the I/O area. The data area can be divided into register, stack, and direct areas according to the application. The program area is located at exactly the opposite end of I/O area, that is, near the highest address. Provide the tables of interrupt reset vectors and vector call instructions toward the highest address within the program area. The memory space of the MB89630R series is structured as illustrated below. Memory space
MB89637R MB89T637R MB89P637 MB89W637 I/O 0080H RAM 768 B 0100H Register 0200H 0280H 0480H External area 8000H 8007H A000H External ROM 32 KB ROM*1 32 KB *2 External area 8000H *3 0200H 0380H 0480H Register 0200H 0100H Register RAM 1024 KB

0000H

MB89PV630 I/O

0000H

MB89635R MB89T635R I/O

0000H

MB89636R I/O

0000H

0080H RAM 1 KB 0100H Register 0200H

0080H RAM 512 B 0100H

0080H

*3 External area

0480H External area 8000H 8007H *2

C000H ROM*1 16 KB

ROM* 24 KB

FFFFH

FFFFH

FFFFH

FFFFH

*1: The ROM area is an external area depending on the mode. The internal ROM cannot be used on the MB89T635R and MB89T637R. *2: Addresses 8000H to 8006H for the MB89P637 and MB89W637 comprise an option area, do not use this area for the MB89PV630 and MB89637R. *3: The access is forbidden in the external bus mode.

21

MB89630R Series
2. Registers
The F2MC-8L family has two types of registers; dedicated registers in the CPU and general-purpose registers in the memory. The following dedicated registers are provided:

Program counter (PC): Accumulator (A): Temporary accumulator (T): Index register (IX): Extra pointer (EP): Stack pointer (SP): Program status (PS):

A 16-bit register for indicating the instruction storage positions A 16-bit temporary register for storing arithmetic operations, etc. When the instruction is an 8-bit data processing instruction, the lower byte is used. A16-bit register which performs arithmetic operations with the accumulator When the instruction is an 8-bit data processing instruction, the lower byte is used. A16-bit register for index modification A16-bit pointer for indicating a memory address A16-bit register for indicating a stack area A16-bit register for storing a register pointer, a condition code

16 bits PC A T IX EP SP PS : Program counter : Accumulator : Temporary accumulator : Index register : Extra pointer : Stack pointer : Program status

Initial value FFFDH Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate I-flag = 0, IL1, IL0 = 11 The other bit values are indeterminate.

The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for use as a condition code register (CCR). (See the diagram below.)

Structure of the program status register

15 PS 14 13 RP 12 11 10 9 8 7 H 6 I 5 4 3 N 2 Z 1 V 0 C

Vacancy Vacancy Vacancy

IL1, IL0

RP

CCR

22

MB89630R Series
The RP indicates the address of the register bank currently in use. The relationship between the pointer contents and the actual address is based on the conversion rule illustrated below. Rule for conversion of actual addresses of the general-purpose register area
RP Lower OP codes b1 b0

0 0 0 0 0 0 0 1 R4 R3 R2 R1 R0 b2

Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and bits for control of CPU operations at the time of an interrupt. H-flag: Set to 1 when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared to 0 otherwise. This flag is for decimal adjustment instructions. I-flag: Interrupt is enabled when this flag is set to 1. Interrupt is disabled when the flag is cleared to 0. Cleared to 0 at the reset.

IL1, IL0: Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is higher than the value indicated by this bit.

IL1 0 0 1 1

IL0 0 1 0 1

Interrupt level 1 2 3

High-low High

Low

N-flag: Set to 1 if the MSB becomes to 1 as the result of an arithmetic operation. Cleared to 0 when the bit is cleared to 0. Z-flag: V-flag: Set to 1 when an arithmetic operation results in 0. Cleared to 0 otherwise. Set to 1 if the complement on 2 overflows as a result of an arithmetic operation. Cleared to 0 if the overflow doesnot occur.

C-flag: Set to 1 when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared to 0 otherwise. Set to the shift-out value in the case of a shift instruction.

23

MB89630R Series
The following general-purpose registers are provided: General-purpose registers: An 8-bit register for storing data The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains eight registers and up to a total of 32 banks can be used on the MB89653A (RAM 512 8 bits). The bank currently in use is indicated by the register bank pointer (RP). Register bank configuraiton
This address = 0100H + 8 (RP) R0 R1 R2 R3 R4 R5 R6 R7 32 banks Memory area

24

MB89630R Series
s I/O MAP
Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH (R/W) (R/W) SMR1 SDR1 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (W) (R/W) (W) (R/W) (R/W) (R/W) (R) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) SYCC STBC WDTE TBCR WPCR CHG3 PDR3 DDR3 PDR4 DDR4 BUZR PDR5 PDR6 PDR7 PCR1 PCR2 RLBR TMCR TCHR TCLR Read/write (R/W) (W) (R/W) (W) (R/W) (W) Register name PDR0 DDR0 PDR1 DDR1 PDR2 BCTR Register description Port 0 data register Port 0 data direction register Port 1 data register Port 1 data direction register Port 2 data register External bus pin control register Vacancy System clock control register System clock control register Watchdog timer control register Timebase timer control register Watch prescaler control register Port 3 switching register Port 3 data register Port 3 data direction register Port 4 data register Port 4 data direction register Buzzer register Port 5 data register Port 6 data register Port 7 data register PWC pulse width control register 1 PWC pulse width control register 2 PWC reload buffer register 16-bit timer control register 16-bit timer count register (H) 16-bit timer count register (L) Vacancy Serial mode register Serial data register Vacancy Vacancy

(Continued)

25

MB89630R Series
(Continued)
Address 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H to 7BH 7CH 7DH 7EH 7FH Note: Do not use vacancies. (W) (W) (W) ILR1 ILR2 ILR3 (R/W) (R/W) (R/W) (W) (W) (R/W) (R/W) (R/W) (R) (W) CNTR1 CNTR2 CNTR3 COMR1 COMR2 SMC SRC SSD SIDR SODR Read/write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Register name ADC1 ADC2 ADDH ADDL EIC1 EIC2 Register description A/D converter control register 1 A/D converter control register 2 A/D converter data register (H) A/D converter data register (L) External interrupt control register 1 External interrupt control register 2 Vacancy Vacancy PWM timer control register 1 PWM timer control register 2 PWM timer control register 3 PWM timer compare register 1 PWM timer compare register 2 UART serial mode control register UART serial rate control register UART serial status/data register UART serial input data control register UART serial output data control register Vacancy Interrupt level setting register 1 Interrupt level settingregister 2 Interrupt level setting register 3 Vacancy

26

MB89630R Series
s ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(AVSS = VSS = 0.0 V)

Parameter Power supply voltage A/D converter reference input voltage Input voltage Output voltage L level maximum output current L level average output current L level total maximum output current L level total average output current H level maximum output current H level average output current H level total maximum output current H level total average output current Power consumption Operating temperature Storage temperature

Symbol VCC AVCC AVR VI VI2 VO VO2 IOL IOLAV IOL IOLAV IOH IOHAV IOH IOHAV PD TA Tstg

Value Min. VSS 0.3 VSS 0.3 VSS 0.3 VSS 0.3 VSS 0.3 VSS 0.3 VSS 0.3 40 55 Max. VSS + 7.0 VSS + 7.0 VSS + 7.0 VCC + 0.3 VSS + 7.0 VCC + 0.3 VSS + 7.0 20 4 100 40 20 4 50 20 500 +85 +150

Unit V V V V V V V mA mA mA mA mA mA mA mA mW C C * *

Remarks

AVR must not exceed AVCC + 0.3 V. Except P50 to P53 P50 to P53 Except P50 to P53 P50 to P53 Average value (operating current operating rate) Average value (operating current operating rate) Average value (operating current operating rate) Average value (operating current operating rate)

* : Use AVCC and VCC set at the same voltage. Take care so that AVCC does not exceed VCC, such as when power is turned on. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

27

MB89630R Series
2. Recommended Operating Conditions
(AVSS = VSS = 0.0 V)

Parameter

Symbol

Value Min. 2.2* Max 6.0*

Unit

Remarks Normal operation assurance range* MB89635R/637R Normal operation assurance range* MB89PV630/P637/ W637/T635R/T637R Retains the RAM state in stop mode

VCC Power supply voltage 2.7* 6.0* V

AVCC A/D converter reference input voltage Operating temperature AVR TA

1.5 3.0 40

6.0 AVCC +85

V V C

* : These values vary with the operating frequency, instruction cycle, and analog assurance range. See Figure 1 and 5. A/D Converter Electrical Characteristics. Figure 1 Operating Voltage vs. Main Clock Operating Frequency
6

Operating voltage (V)

Operation assurance range 4

Analog accuracy assured in the AVCC = 3.5 V to 6.0 V range

1.0

2.0 3.0

4.0

5.0

6.0

7.0

8.0

9.0

10.0

Main clock operating frequency (at an instruction cycle of 4/FCH) (MHz)

4.0

2.0

0.8

0.4

Minimum execution time (instruction cycle) (s) Note: The shaded area is assured only for the MB89635R/636R/637R.

Figure 1 indicates the operating frequency of the external oscillator at an instruction cycle of 4/FCH. Since the operating voltage range is dependent on the instruction cycle, see minimum execution time if the operating speed is switched using a gear. 28

MB89630R Series
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the devices electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.

29

MB89630R Series
3. DC Characteristics
(AVCC = VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = 40C to +85C)

Parameter

Symbol

Pin name
P00 to P07, P10 to P17, P22, P23, P31, P34, P37, P41, P43, P51 to P53 P51 to P53 RST, MOD0, MOD1, P30, P32, P33, P35, P36, P40, P42,P50, P72 to P74 P50, P70, P71 P00 to P07, P10 to P17, P22, P23, P31, P34, P37, P41, P43 P30, P32, P33, P35, P36, P40, P42, P50 to P53, P70 to P74, RST, MOD0, MOD1

Condition

Value Min. 0.7 VCC Typ. Max.

VCC + 0.3

Unit

Remarks P51 to P53 with pull-up resistor Without pull-up resistor P50 with pull-up resistor Without pull-up resistor

VIH1

VIH2 H level input voltage VIHS

0.7 VCC

VSS + 6.0

0.8 VCC

VCC + 0.3

VIHS2 VIL L level input voltage VILS

0.8 VCC
VSS 0.3

VSS + 6.0

V V

0.3 VCC

VSS 0.3

0.2 VCC

Open-drain output pin application voltage

VD

P50 to P53

VSS 0.3

VSS + 6.0

H level output VOH voltage L level output voltage

P00 to P07, P10 to P17, P20 to P27, P30 to P37, IOH = 2.0 mA P40 to P43 P00 to P07, P10 to P17, P20 to P27, P30 to P37, IOL = 4.0 mA P40 to P43, P50 to P53, P60 to P67, RST P00 to P07, P10 to P17, P20 to P23, P30 to P37, P40 to P43, P50 to P53, 0.0 V < VI < VCC P70 to P74, MOD0, MOD1

4.0

VOL

0.4

Input leakage current ILI (Hi-z output leakage current)

Without pull-up resistor

(Continued)

30

MB89630R Series
(AVCC = VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = 40C to +85C)

Parameter Pull-up resistance

Symbol

Pin name

Condition

Value Min. 25 Typ. 50 Max. 100

Unit k

Remarks With pull-up resistor

RPULL

P00 to P07, P10 to P17, P30 to P37, P40 to P43, VI = 0.0 V P50 to P53, P72 to P74

ICC1

FCH = 10 MHz VCC = 5.0 V tinst*2 = 0.4 s FCH = 10 MHz VCC = 3.0 V tinst*2 = 6.4 s
FCH = 10 MHz VCC = 5.0 V tinst*2 = 0.4 s FCH = 10 MHz VCC = 3.0 V tinst*2 = 6.4 s

12

20

mA
MB89635R/T635R/ 636R/637R/T637R/ PV630 MB89P637/W637

ICC2

1.0 1.5 3

2 2.5 7

mA mA mA

ICCS2

Sleep mode

ICCS1

0.5

1.5

mA
MB89635R/T635R/ 636R/637R/T637R/ PV630 MB89P637/W637

FCL = 32.768 kHz,

Power supply current*1

ICCL VCC

VCC = 3.0 V Subclock mode

FCL = 32.768 kHz,

50 500 25

100 700 50

A A A

ICCLS

VCC = 3.0 V Subclock sleep mode

FCL = 32.768 kHz,

ICCT

VCC = 3.0 V Watch mode Main clock stop mode at dualclock system TA = +25C Subclock stop mode Main clock stop mode at singleclock system

15

ICCH

(Continued)

31

MB89630R Series
(Continued)
Parameter
Symbol (AVCC = VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = 40C to +85C)

Pin name

Condition FCH = 10 MHz, when A/D conversion operates.

Value Min. Typ. 6 Max.

Unit

Remarks

IA Power supply current*1 IAH AVCC

mA

FCH = 10 MHz, TA = +25C, when A/D conversion in a stop. f = 1 MHz

Input capacitance CIN

Other than AVCC, AVSS, VCC, and VSS

10

pF

*1: The power supply current is measured at the external clock. In the case of the MB89PV630, the current consumed by the connected EPROM and ICE is not counted. *2: For information on tinst, see (4) Instruction Cycle in 4. AC Characteristics.

4. AC Characteristics
(1) Reset Timing
(VCC = 5.0 V10%, AVSS = VSS = 0.0 V, TA = 40C to +85C)

Parameter RST L pulse width

Symbol tZLZH

Condition

Value Min. 48 tHCYL Max.

Unit ns

Remarks

tZLZH RST

0.2 VCC

0.2 VCC

32

MB89630R Series
(2) Specification for Power-on Reset
(AVSS = VSS = 0.0 V, TA = 40C to +85C)

Parameter Power supply rising time Power supply cut-off time

Symbol tR tOFF

Condition

Value Min. Max. 50

Unit ms ms

Remarks Power-on reset function only Min. interval time for the next power-on reset

Note: Make sure that power supply rises within the selected oscillation stabilization time. If power supply voltage needs to be varied in the course of operation, a smooth voltage rise is recommended.

tR 2.0 V 0.2 V

tOFF

VCC

0.2 V

0.2 V

(3) Clock Timing

(AVSS = VSS = 0.0 V, TA = 40C to +85C)

Parameter Clock frequency Clock cycle time

Symbol FCH FCL tHCYL tLCYL PWH PWL PWLH PWLL tCR tCF

Pin name X0, X1 X0A, X1A X0, X1 X0A, X1A X0 X0A X0

Condition

Value Min. 1 100 Typ. 32.768 30.5 15.2 Max. 10 1000 10

Unit MHz kHz ns s ns s ns

Remarks

20

External clock External clock External clock

Input clock pulse width

Input clock rising/falling time

33

MB89630R Series

Main clock timing condition

tHCYL PWH tCR 0.8 VCC X0 0.2 VCC 0.2 VCC 0.2 VCC 0.8 VCC tCF PWL

Main clock configurations

When a crystal or ceramic reasonator is used When an external clock is used

X0

X1

X0

X1 Open

Subclock timing condition

tLCYL PWLH tCR 0.8 VCC X0A 0.2 VCC 0.2 VCC 0.2 VCC 0.8 VCC tCF PWLL

Subclock configurations
When a crystal or ceramic reasonator is used When an external clock is used

X0A

X1A

X0A

X1A Open

34

MB89630R Series
(4) Instruction Cycle Parameter Instruction cycle (minimum execution time) Symbol Value (typical) 4/FCH, 8/FCH, 16/FCH, 64/FCH tinst 2/FCL s Unit s Remarks (4/FCH) tinst = 0.4 s, operating at FCH = 10 MHz tinst = 61.036 s, operating at FCL = 32.768 kHz

Note: Operating at 10 MHz, the cycle varies with the set execution time. (5) Clock Output Timing
(VCC = 5.0 V10%, AVSS = VSS= 0.0 V, TA = 40C to +85C)

Parameter Clock time CLK CLK

Symbol tCYC tCHCL

Pin name CLK CLK

Condition

Value Min. 1/2 tinst* 1/4 tinst* 70 ns Max. 1/4 tinst*

Unit s s

Remarks

* : For information on tinst, see (4) Instruction Cycle.

tCYC tCHCL 2.4 V

CLK

2.4 V 0.8 V

35

MB89630R Series
(6) Bus Read Timing
(VCC = 5.0 V10%, 10 MHz, AVSS = VSS= 0.0 V, TA = 40C to +85C)

Parameter

Symbol

Pin name
RD, A15 to A08, AD7 to AD0 RD AD7 to AD0, A15 to A08 RD, AD7 to AD0 AD7 to AD0, RD RD, ALE RD, A15 to A08 RD, CLK RD, BUFC A15 to A08, AD7 to AD0, BUFC

Condition

Value Min.
1/4 tinst* 64 ns 1/2 tinst* 20 ns

Max. 200 120

Unit s s s s s s s s ns s s

Remarks

Valid address RD time tAVRL RD pulse width tRLRH

Valid address data read tAVDV time RD data read time RD data hold time RD ALE time RD address loss time RD CLK time CLK RD time RD BUFC time BUFC valid address time tRLDV tRHDX tRHLH tRHAX tRLCH tCLRH tRLBL tBHAV

1/2 tinst*
1/2 tinst* 80 ns

No wait No wait

0
1/4 tinst* 40 ns 1/4 tinst* 40 ns 1/4 tinst* 40 ns

0 5 5

* : For information on tinst, see (4) Instruction Cycle.

CLK

2.4 V 0.8 V

tRHLH ALE 0.8 V

2.4 V AD 0.8 V tAVDV A 2.4 V 0.8 V tAVRL tRLDV tRLRH RD 0.8 V tRLBL tRLCH

0.7 VCC 0.3 VCC

0.7 VCC 0.3 VCC tRHDX 2.4V tCLRH 0.8V tRHAX

2.4 V 0.8 V

2.4 V 0.8 V

2.4 V tBHAV 2.4 V

BUFC

0.8 V

36

MB89630R Series
(7) Bus Write Timing
(VCC = 5.0 V10%, FCH = 10 MHz, AVSS = VSS= 0.0 V, TA = 40C to +85C)

Parameter

Symbol

Pin name
AD7 to AD0, ALE A15 to A08

Condition

Value Min.
1/4 tinst*1 64 ns*2

Max.

Unit Remarks s ns s s s s s s s ns s s

Valid address ALE time tAVLL ALE time address loss time Valid address WR time WR pulse width Write data WR time WR address loss time WR data hold time WR ALE time WR CLK time CLK WR time ALE pulse width ALE CLK time tLLAX tAVWL tWLWH tDVWH tWHAX tWHDX tWHLH tWLCH tCLWH tLHLL tLLCH

5
1/4 tinst*1 60 ns*2 1/2 tinst* 20 ns* 1/2 tinst* 60 ns*
1 1 2

WR, ALE WR
AD7 to AD0, WR WR, A15 to A08 AD7 to AD0, WR

1/4 tinst*1 40 ns*2 1/4 tinst*1 40 ns*2 1/4 tinst* 40 ns* 1/4 tinst* 40 ns*
1 1 2 2

WR, ALE WR, CLK ALE ALE,CLK

0
1/4 tinst*1 35 ns*2 1/4 tinst* 30 ns*
1 2

*1: For information on tinst, see (4) Instruction Cycle. *2: This characteristics are also applicable to the bus read timing.

CLK tLHLL 2.4 V 0.8 V tAVLL 2.4 V 2.4 V 0.8 V 0.8 V tLLAX 2.4 V 0.8 V tLLCH

2.4 V 0.8 V

tWHLH 0.8 V

ALE

2.4 V 0.8 V tDVWH tWHDX 2.4 V tCLWH 0.8 V tWHAX tWLWH

AD

2.4 V 0.8 V tAVWL

tWLCH

WR 0.8V

2.4 V

37

MB89630R Series
(8) Ready Input Timing
(VCC = 5.0 V10%, FCH = 10 MHz, AVSS = VSS= 0.0 V, TA = 40C to +85C)

Parameter RDY valid CLK time CLK RDY loss time

Symbol tYVCH tCHYX

Pin name RDY, CLK

Condition

Value Min. 60 0 Max.

Unit ns ns

Remarks * *

* : This characteristics are also applicable to the read cycle.

CLK

2.4 V

2.4 V

ALE

AD

Address

Data

WR tYVCH tCHYX RDY

tYVCH

tCHYX

Note: The bus cycle is also extended in the read cycle in the same manner.

38

MB89630R Series
(9) Serial I/O Timing
(VCC = 5.0 V10%, FCH = 10 MHz, AVSS = VSS= 0.0 V, TA = 40C to +85C)

Parameter Serial clock cycle time SCK1 SO1 time UCK1 UO1 time UCK2 UO2 time Valid SI1 SCK1 Valid UI1 UCK1 Valid UI2 UCK2

Symbol tSCYC tSLOV

Pin name SCK1, UCK1, UCK2 SCK1, SO1 UCK1, UO1 UCK2, UO2 SI1, SCK1 UI1, UCK1 UI2, UCK2 SCK1, SI1 UCK1, UI1 UCK2, UI2 SCK1, UCK1, UCK2 SCK1, UCK1, UCK2 SCK1, SO1 UCK1, UO1 UCK2, UO2 SI1, SCK1 UI1, UCK1 UI2, UCK2 SCK1, SI1 UCK1, UI1 UCK2, UI2

Condition

Value Min. 2 tinst* 200 Max. 200

Unit Remarks s ns

tIVSH

Internal shift clock mode

1/2 tinst*

SCK1 valid SI1 hold time UCK1 valid UI1 hold time tSHIX UCK2 valid UI2 hold time Serial clock H pulse width Serial clock L pulse width SCK1 SO1 time UCK1 UO1 time UCK2 UO2 time Valid SI1 SCK1 Valid UI1 UCK1 Valid UI2 UCK2 tSHSL tSLSH tSLOV

1/2 tinst* 1 tinst* 1 tinst* External shift clock mode 0

200

s s s ns

tIVSH

1/2 tinst*

SCK1 valid SI1 hold time UCK1 valid UI1 hold time tSHIX UCK2 valid UI2 hold time

1/2 tinst*

* : For information on tinst, see (4) Instruction Cycle.

39

MB89630R Series

Internal shift clock mode

tSCYC

SCK1 UCK1 UCK2

2.4 V 0.8 V 0.8 V

tSLOV SO1 UO1 UO2 2.4 V 0.8 V tIVSH SI1 UI1 UI 0.8 VCC 0.2 VCC

tSHIX 0.8 VCC 0.2 VCC

External shift clock mode

tSLSH

tSHSL

SCK1 UCK1 UCK2

0.8 VCC 0.2 VCC 0.2 VCC

0.8 VCC

tSLOV SO1 UO1 UO2 2.4 V 0.8 V tIVSH SI1 UI1 UI 0.8 VCC 0.2 VCC tSHIX 0.8 VCC 0.2 VCC

40

MB89630R Series
(10) Peripheral Input Timing
(VCC = 5.0 V10%, AVSS = VSS = 0.0 V, TA = 40C to +85C)

Parameter Peripheral input H pulse width 1 Peripheral input L pulse width 1 Peripheral input H pulse width 2 Peripheral input L pulse width 2 Peripheral input H pulse width 3 Peripheral input L pulse width 3

Symbol tILIH1 tIHIL1 tILIH2 tIHIL2 tILIH3 tIHIL3

Pin name PWC, INT0 to INT3,EC

Value Min. 2 tinst* 2 tinst* 2 t * 28 tinst* 28 tinst* 2 t *

8 inst 8 inst

Max.

Unit s s s s s s

Remarks

ADST

A/D mode A/D mode Sense mode Sense mode

ADST

* : For information on tinst, see (4) Instruction Cycle.

tIHIL1 PWC, EC, INT0 to INT3 0.2 VCC 0.8 VCC 0.2 VCC

tILIH1 0.8 VCC

tIHIL2 (tIHIL3) ADST 0.8 VCC 0.2 VCC 0.2 VCC

tILIH2 (tILIH3) 0.8 VCC

41

MB89630R Series
5. A/D Converter Electrical Characteristics
(AVCC = VCC = 3.5 V to 6.0 V, FCH = 10 MHz, AVSS = VSS = 0.0 V, TA = 40C to +85C)

Parameter Resolution Linearity error Differential linearity error Total error Zero transition voltage Full-scale transition voltage Interchannel disparity A/D mode conversion time Analog port input current Analog input voltage Reference voltage Reference voltage supply current

Symbol

Pin name

Value Min. Typ. Max. 10 2.0 1.5 3.0

Unit bit LSB LSB LSB

Remarks

At AVCC = VCC

VOT VFST

AN0 to AN7 AVR 3.5 LSB AVR 1.5 LSB AVR + 0.5 LSB mV 13.2 200 4 10 AVR AVCC LSB s A V V A AVR = 5.0 V At 10 MHz oscillation

AVSS 1.5 LSB AVSS + 0.5 LSB AVSS + 2.5 LSB mV

IAIN IR

AN0 to AN7

0.0 0.0

42

MB89630R Series
6. A/D Converter Glossary
Resolution Analog changes that are identifiable with the A/D converter Linearity error The deviation of the straight line connecting the zero transition point (00 0000 0000 00 0000 0001) with the full-scale transition point (11 1111 1110 11 1111 1111) from actual conversion characteristics Differential linearity error The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value Total error (unit: LSB) The difference between theoretical and actual conversion values caused by the zero transition error, full-scale transition error, linearity error, quantization error, and noise

Theoretical I/O characteristics 3FF 3FE 3FD Digital output 1.5 LSB Digital output VFST 3FF 3FE 3FD

Total error

Actual conversion value

{1 LSB N + 0.5 LSB}

004 003 002 001 0.5 LSB AVSS Analog input AVR

004 003

VNT Actual conversion value Theoretical value

VOT 1 LSB

002 001 AVSS

AVR Analog input

1 LSB =

VFST VOT 1022

(V)

Digital output N total error = VNT {1 LSB N + 0.5 LSB} 1 LSB

(Continued)

43

MB89630R Series
(Continued)

Zero transition error 004 Actual conversion value 003 Digital output Digital output 3FE 3FF

Full-scale transition error

Theoretical value

Actual conversion value

002 Actual conversion value 001

3FD

VFST (Actual measurement) Actual conversion value

VOT (Actual measurement) AVSS Analog input

3FC AVR Analog input

Linearity error 3FF 3FE 3FD Digital output VFST (Actual measurement) Digital output N Actual conversion value {1 LSB N + VOT} N+1

Differential linearity error

Theoretical value

Actual conversion value

V(N + 1)T

VNT
004 003 002 001 AVSS Analog input Theoretical value

N1 Actual conversion value

VNT Actual conversion value

N2 AVR Analog input

VOT (Actual measurement) AVR AVSS

Digital output N linearity error =

VNT {1 LSB N + VOT} 1 LSB

Digital output N differential linearity error =

V(N + 1)T VNT 1 LSB

44

MB89630R Series
7. Notes on Using A/D Converter
Input impedance of the analog input pins The output impedance of the external circuit for the analog input must satisfy the followingconditions. If the output impedance of the external circuit is too high, an analog voltage sampling time might beinsufficient (sampling time = 6 s at 10MHz oscillation.) Therefore, it is recommended to keep the output impedance of the external circuit below 10 k . Analog input circuit model

Analog input

C0 Converter RON1 RON2 C1

RON1: RON2: C0: C1:

Approx. 1.5 k Approx. 1.5 k Approx. 60 pF Approx. 4 pF

Note: The values mentioned here should be used as a guideline.

Error The smaller the | AVRAVss |, the greater the error would become relatively.

45

MB89630R Series
s CHARACTERISTICS EXAMPLE
(1) L Level Output Voltage (2) H Level Output Voltage

VOL vs. IOL

VOL (V) 0.5 VCC = 5.0 V 0.4 0.3 0.2 0.1 VCC = 6.0 V VCC = 3.0 V TA = +25C VCC = 4.0 V

VCC - VOH (V) 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0.0

VCC - VOH vs. IOH

TA = +25C VCC = 2.5 V

VCC = 3.0 V VCC = 4.0 V VCC = 5.0 V VCC = 6.0 V

10 IOL (mA)

0.5

1.0

1.5

2.0

2.5

3.0 IOH (mA)

(3) H Level Input Voltage/L Level Input Voltage (CMOS Input)

(4) H Level Input Voltage/L Level Input Voltage (Hysteresis Input)

VIN (V) 5.0

VIN vs. VCC

TA = +25C VIHS

VIN (V) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0 1 2

VIN vs. VCC

TA = +25C

4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0 1 2 3 4 5

VILS

7 VCC (V)

7 VCC (V)

VIHS: Threshold as the input voltage in hysteresis characteristics is set to H level VILS: Threshold as the input voltage in hysteresis characteristics is set to L level

46

MB89630R Series
(5) Power Supply Current (External Clock)

ICC (mA) 16 14 12 10 8 6

ICC1 vs. VCC, ICC2 vs. VCC

FCH = 10MHz TA = +25C Divide by 4 (ICC1)

ICCS (mA) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 Divide by 8 1.5 1.0 0.5 0 2.0 2.5

ICCS1 vs. VCC, ICCS2 vs. VCC

FCH = 10MHz TA = +25C

Divide by 4 (ICCS1) Divide by 8 Divide by 16 Divide by 64 (ICCS2) 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 VCC (V)

4 Divide by 16 2 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Divide by 64 (ICC2) 6.0 6.5 VCC (V)

ICCL (A) 200 180 160 140 120 100 80 60 40 20 0 2.0 2.5 3.0 3.5

ICCL vs. VCC

TA = +25C

ICCLS (A) 50 45 40 35 30 25 20 15 10 5

ICCLS vs. VCC

TA = +25C

4.0

4.5

5.0

5.5

6.0

6.5 VCC (V)

0 2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

6.5 VCC (V)

(Continued)

47

MB89630R Series
(Continued)

I CCT (A) 20 18 16 14 12 10 8 6 4 2 0 2.0 2.5 3.0

I CCT vs. V CC
TA = +25C

I CCH (A) 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2

I CCH vs. V CC
TA = +25C

3.5

4.0

4.5

5.0

5.5

6.0

6.5 V CC (V)

0 2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

6.5 V CC (V)

(6) Pull-up Resistance

R PULL (k) 1000

R PULL vs. V CC
TA = +25C

100

10 1 2 3 4 5 6 V CC (V)

48

MB89630R Series
s INSTRUCTIONS (136 INSTRUCTIONS)
Execution instructions can be divided into the following four groups: Transfer Arithmetic operation Branch Others Table 1 lists symbols used for notation of instructions. Table 1 Symbol dir off ext #vct #d8 #d16 dir: b rel @ A AH AL T TH TL IX EP PC SP PS dr CCR RP Ri () (( )) Instruction Symbols Meaning Direct address (8 bits) Offset (8 bits) Extended address (16 bits) Vector table number (3 bits) Immediate data (8 bits) Immediate data (16 bits) Bit direct address (8:3 bits) Branch relative address (8 bits) Register indirect (Example: @A, @IX, @EP) Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.) Upper 8 bits of accumulator A (8 bits) Lower 8 bits of accumulator A (8 bits) Temporary accumulator T (Whether its length is 8 or 16 bits is determined by the instruction in use.) Upper 8 bits of temporary accumulator T (8 bits) Lower 8 bits of temporary accumulator T (8 bits) Index register IX (16 bits) Extra pointer EP (16 bits) Program counter PC (16 bits) Stack pointer SP (16 bits) Program status PS (16 bits) Accumulator A or index register IX (16 bits) Condition code register CCR (8 bits) Register bank pointer RP (5 bits) General-purpose register Ri (8 bits, i = 0 to 7) Indicates that the very is the immediate data. (Whether its length is 8 or 16 bits is determined by the instruction in use.) Indicates that the contents of is the target of accessing. (Whether its length is 8 or 16 bits is determined by the instruction in use.) The address indicated by the contents of is the target of accessing. (Whether its length is 8 or 16 bits is determined by the instruction in use.)

Columns indicate the following: Mnemonic: Assembler notation of an instruction ~: The number of instructions #: The number of bytes Operation: Operation of an instruction TL, TH, AH: A content change when each of the TL, TH, and AH instructions is executed. Symbols in the column indicate the following: indicates no change. dH is the 8 upper bits of operation description data. AL and AH must become the contents of AL and AH prior to the instruction executed. 00 becomes 00. N, Z, V, C: An instruction of which the corresponding flag will change. If + is written in this column, the relevant instruction will change its corresponding flag. OP code: Code of an instruction. If an instruction is more than one code, it is written according to the following rule: Example: 48 to 4F This indicates 48, 49, ... 4F. 49

MB89630R Series
Table 2 Mnemonic MOV dir,A MOV @IX +off,A MOV ext,A MOV @EP ,A MOV Ri,A MOV A,#d8 MOV A,dir MOV A,@IX +off MOV A,ext MOV A,@A MOV A,@EP MOV A,Ri MOV dir,#d8 MOV @IX +off,#d8 MOV @EP ,#d8 MOV Ri,#d8 MOVW dir,A MOVW @IX +off,A MOVW ext,A MOVW @EP ,A MOVW EP ,A MOVW A,#d16 MOVW A,dir MOVW A,@IX +off MOVW A,ext MOVW A,@A MOVW A,@EP MOVW A,EP MOVW EP ,#d16 MOVW IX,A MOVW A,IX MOVW SP ,A MOVW A,SP MOV @A,T MOVW @A,T MOVW IX,#d16 MOVW A,PS MOVW PS,A MOVW SP ,#d16 SWAP SETB dir: b CLRB dir: b XCH A,T XCHW A,T XCHW A,EP XCHW A,IX XCHW A,SP MOVW A,PC ~ 3 4 4 3 3 2 3 4 4 3 3 3 4 5 4 4 4 5 5 4 2 3 4 5 5 4 4 2 3 2 2 2 2 3 4 3 2 2 3 2 4 4 2 3 3 3 3 2 # 2 2 3 1 1 2 2 2 3 1 1 1 3 3 2 2 2 2 3 1 1 3 2 2 3 1 1 1 3 1 1 1 1 1 1 3 1 1 3 1 2 2 1 1 1 1 1 1 Transfer Instructions (48 instructions) Operation (dir) (A) ( (IX) +off ) (A) (ext) (A) ( (EP) ) (A) (Ri) (A) (A) d8 (A) (dir) (A) ( (IX) +off) (A) (ext) (A) ( (A) ) (A) ( (EP) ) (A) (Ri) (dir) d8 ( (IX) +off ) d8 ( (EP) ) d8 (Ri) d8 (dir) (AH),(dir + 1) (AL) ( (IX) +off) (AH), ( (IX) +off + 1) (AL) (ext) (AH), (ext + 1) (AL) ( (EP) ) (AH),( (EP) + 1) (AL) (EP) (A) (A) d16 (AH) (dir), (AL) (dir + 1) (AH) ( (IX) +off), (AL) ( (IX) +off + 1) (AH) (ext), (AL) (ext + 1) (AH) ( (A) ), (AL) ( (A) ) + 1) (AH) ( (EP) ), (AL) ( (EP) + 1) (A) (EP) (EP) d16 (IX) (A) (A) (IX) (SP) (A) (A) (SP) ( (A) ) (T) ( (A) ) (TH),( (A) + 1) (TL) (IX) d16 (A) (PS) (PS) (A) (SP) d16 (AH) (AL) (dir): b 1 (dir): b 0 (AL) (TL) (A) (T) (A) (EP) (A) (IX) (A) (SP) (A) (PC) TL AL AL AL AL AL AL AL AL AL AL AL AL AL AL AL TH AH AH AH AH AH AH AH AH dH dH dH dH dH dH dH dH dH dH AL dH dH dH dH dH NZVC ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++++ OP code 45 46 61 47 48 to 4F 04 05 06 60 92 07 08 to 0F 85 86 87 88 to 8F D5 D6 D4 D7 E3 E4 C5 C6 C4 93 C7 F3 E7 E2 F2 E1 F1 82 83 E6 70 71 E5 10 A8 to AF A0 to A7 42 43 F7 F6 F5 F0

Note: During byte transfer to A, T A is restricted to low bytes. Operands in more than one operand instruction must be stored in the order in which their mnemonics are written. (Reverse arrangement of F2MC-8 family)

50

MB89630R Series
Table 3 Mnemonic ADDC A,Ri ADDC A,#d8 ADDC A,dir ADDC A,@IX +off ADDC A,@EP ADDCW A ADDC A SUBC A,Ri SUBC A,#d8 SUBC A,dir SUBC A,@IX +off SUBC A,@EP SUBCW A SUBC A INC Ri INCW EP INCW IX INCW A DEC Ri DECW EP DECW IX DECW A MULU A DIVU A ANDW A ORW A XORW A CMP A CMPW A RORC A ROLC A CMP A,#d8 CMP A,dir CMP A,@EP CMP A,@IX +off CMP A,Ri DAA DAS XOR A XOR A,#d8 XOR A,dir XOR A,@EP XOR A,@IX +off XOR A,Ri AND A AND A,#d8 AND A,dir ~ 3 2 3 4 3 3 2 3 2 3 4 3 3 2 4 3 3 3 4 3 3 3 19 21 3 3 3 2 3 2 2 2 3 3 4 3 2 2 2 2 3 3 4 3 2 2 3 # 1 2 2 2 1 1 1 1 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 2 1 1 1 1 2 2 1 2 1 1 2 2 Arithmetic Operation Instructions (62 instructions) Operation (A) (A) + (Ri) + C (A) (A) + d8 + C (A) (A) + (dir) + C (A) (A) + ( (IX) +off) + C (A) (A) + ( (EP) ) + C (A) (A) + (T) + C (AL) (AL) + (TL) + C (A) (A) (Ri) C (A) (A) d8 C (A) (A) (dir) C (A) (A) ( (IX) +off) C (A) (A) ( (EP) ) C (A) (T) (A) C (AL) (TL) (AL) C (Ri) (Ri) + 1 (EP) (EP) + 1 (IX) (IX) + 1 (A) (A) + 1 (Ri) (Ri) 1 (EP) (EP) 1 (IX) (IX) 1 (A) (A) 1 (A) (AL) (TL) (A) (T) / (AL),MOD (T) (A) (A) (T) (A) (A) (T) (A) (A) (T) (TL) (AL) (T) (A) CA C A (A) d8 (A) (dir) (A) ( (EP) ) (A) ( (IX) +off) (A) (Ri) Decimal adjust for addition Decimal adjust for subtraction (A) (AL) (TL) (A) (AL) d8 (A) (AL) (dir) (A) (AL) ( (EP) ) (A) (AL) ( (IX) +off) (A) (AL) (Ri) (A) (AL) (TL) (A) (AL) d8 (A) (AL) (dir) TL dL TH 00 AH dH dH dH dH dH 00 dH dH dH NZVC ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ +++ ++ +++ ++ ++R ++R ++R ++++ ++++ +++ +++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++R ++R ++R ++R ++R ++R ++R ++R ++R OP code 28 to 2F 24 25 26 27 23 22 38 to 3F 34 35 36 37 33 32 C8 to CF C3 C2 C0 D8 to DF D3 D2 D0 01 11 63 73 53 12 13 03 02 14 15 17 16 18 to 1F 84 94 52 54 55 57 56 58 to 5F 62 64 65

(Continued)

51

MB89630R Series
(Continued) Mnemonic
AND A,@EP AND A,@IX +off AND A,Ri OR A OR A,#d8 OR A,dir OR A,@EP OR A,@IX +off OR A,Ri CMP dir,#d8 CMP @EP ,#d8 CMP @IX +off,#d8 CMP Ri,#d8 INCW SP DECW SP

~ 3 4 3 2 2 3 3 4 3 5 4 5 4 3 3

# 1 2 1 1 2 2 1 2 1 3 2 3 2 1 1

Operation (A) (AL) ( (EP) ) (A) (AL) ( (IX) +off) (A) (AL) (Ri) (A) (AL) (TL) (A) (AL) d8 (A) (AL) (dir) (A) (AL) ( (EP) ) (A) (AL) ( (IX) +off) (A) (AL) (Ri) (dir) d8 ( (EP) ) d8 ( (IX) + off) d8 (Ri) d8 (SP) (SP) + 1 (SP) (SP) 1 Table 4

TL

TH

AH

NZVC ++R ++R ++R ++R ++R ++R ++R ++R ++R ++++ ++++ ++++ ++++

OP code 67 66 68 to 6F 72 74 75 77 76 78 to 7F 95 97 96 98 to 9F C1 D1

Branch Instructions (17 instructions) Operation TL TH AH dH NZVC + + Restore OP code FD FC F9 F8 FB FA FF FE B0 to B7 B8 to BF E0 21 E8 to EF 31 F4 20 30

Mnemonic BZ/BEQ rel BNZ/BNE rel BC/BLO rel BNC/BHS rel BN rel BP rel BLT rel BGE rel BBC dir: b,rel BBS dir: b,rel JMP @A JMP ext CALLV #vct CALL ext XCHW A,PC RET RETI

~ 3 3 3 3 3 3 3 3 5 5 2 3 6 6 3 4 6

# 2 2 2 2 2 2 2 2 3 3 1 3 1 3 1 1 1

If Z = 1 then PC PC + rel If Z = 0 then PC PC + rel If C = 1 then PC PC + rel If C = 0 then PC PC + rel If N = 1 then PC PC + rel If N = 0 then PC PC + rel If V N = 1 then PC PC + rel If V N = 0 then PC PC + reI If (dir: b) = 0 then PC PC + rel If (dir: b) = 1 then PC PC + rel (PC) (A) (PC) ext Vector call Subroutine call (PC) (A),(A) (PC) + 1 Return from subrountine Return form interrupt Table 5

Other Instructions (9 instructions) Operation TL TH AH dH NZVC R S OP code 40 50 41 51 00 81 91 80 90

Mnemonic PUSHW A POPW A PUSHW IX POPW IX NOP CLRC SETC CLRI SETI

~ 4 4 4 4 1 1 1 1 1

# 1 1 1 1 1 1 1 1 1

52

H
3 RETI PUSHW POPW MOV MOVW CLRI A A A,ext A,PS SETC SETI CLRB BBC INCW DECW JMP MOVW dir: 0 dir: 0,rel A A @A A,PC 4 5 6 7 8 9 A B C D E F

NOP

SWAP

RET

MULU

DIVU

A SUBC A A A, T A A A XCH XOR AND OR

JMP CALL PUSHW POPW MOV MOVW CLRC addr16 addr16 IX IX ext,A PS,A

CLRB BBC INCW DECW MOVW MOVW dir: 1 dir: 1,rel SP SP SP ,A A,SP

ROLC

CMP

ADDC

s INSTRUCTION MAP

MOV MOV CLRB BBC INCW DECW MOVW MOVW @A,T A,@A dir: 2 dir: 2,rel IX IX IX,A A,IX

RORC

CMPW

A XOR AND OR DAA A,#d8 A,#d8 A,#d8 DAS

ADDCW SUBCW XCHW XORW ANDW ORW MOVW MOVW CLRB BBC INCW DECW MOVW MOVW A A A, T A A A @A,T A,@A dir: 3 dir: 3,rel EP EP EP ,A A,EP CLRB BBC MOVW MOVW MOVW XCHW dir: 4 dir: 4,rel A,ext ext,A A,#d16 A,PC

MOV CMP ADDC SUBC A,#d8 A,#d8 A,#d8 A,#d8

MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP CLRB BBC MOVW MOVW MOVW XCHW A,dir A,dir A,dir A,dir dir,A A,dir A,dir A,dir dir,#d8 dir,#d8 dir: 5 dir: 5,rel A,dir dir,A SP ,#d16 A,SP

MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP CLRB BBC MOVW MOVW MOVW XCHW A,@IX +d A,@IX +d A,@IX +d A,@IX +d @IX +d,A A,@IX +d A,@IX +d A,@IX +d @IX +d,#d8 @IX +d,#d8 dir: 6 dir: 6,rel A,@IX +d @IX +d,A IX,#d16 A,IX

MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP CLRB BBC MOVW MOVW MOVW XCHW A,@EP A,@EP A,@EP A,@EP @EP ,A A,@EP A,@EP A,@EP @EP ,#d8 @EP ,#d8 dir: 7 dir: 7,rel A,@EP @EP ,A EP ,#d16 A,EP DEC R0 DEC R1 DEC R2 DEC R3 DEC R4 DEC R5 DEC R6 DEC R7 R7 R6 R5 R4 R3 R2 R1 R0 CALLV BNC #0 rel CALLV BC #1 CALLV BP #2 CALLV BN #3

MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R0 A,R0 A,R0 A,R0 R0,A A,R0 A,R0 A,R0 R0,#d8 R0,#d8 dir: 0 dir: 0,rel

MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R1 A,R1 A,R1 A,R1 R1,A A,R1 A,R1 A,R1 R1,#d8 R1,#d8 dir: 1 dir: 1,rel

rel

MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R2 A,R2 A,R2 A,R2 R2,A A,R2 A,R2 A,R2 R2,#d8 R2,#d8 dir: 2 dir: 2,rel

rel

MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R3 A,R3 A,R3 A,R3 R3,A A,R3 A,R3 A,R3 R3,#d8 R3,#d8 dir: 3 dir: 3,rel

rel CALLV BNZ #4 rel CALLV BZ #5

MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R4 A,R4 A,R4 A,R4 R4,A A,R4 A,R4 A,R4 R4,#d8 R4,#d8 dir: 4 dir: 4,rel

MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R5 A,R5 A,R5 A,R5 R5,A A,R5 A,R5 A,R5 R5,#d8 R5,#d8 dir: 5 dir: 5,rel

rel CALLV BGE #6 rel CALLV BLT #7

MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R6 A,R6 A,R6 A,R6 R6,A A,R6 A,R6 A,R6 R6,#d8 R6,#d8 dir: 6 dir: 6,rel

MB89630R Series

MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R7 A,R7 A,R7 A,R7 R7,A A,R7 A,R7 A,R7 R7,#d8 R7,#d8 dir: 7 dir: 7,rel

rel

53

MB89630R Series
s MASK OPTIONS
Part number No. Specifying procedure Pull-up resistors P00 to P07, P10 to P17, P30 to P37, P40 to P43, P50 to P53, P72 to P74 Power-on reset selection With power-on reset Without power-on reset Selection of the main clock oscillation stabilization time (at 10 MHz) Approx. 218/FCH (Approx. 26.2 ms) Approx. 217/FCH (Approx. 13.1 ms) Approx. 214/FCH (Approx. 1.6 ms) Approx. 24/FCH (Approx. 0 ms) FCH : Main clock frequency Reset pin output Reset output provided No reset output Single/dual-clock system option Single clock Dual clock MB89635R MB89636R MB89637R Specify when ordering masking MB89P637 MB89W637 Set with EPROM programmer MB89PV630 MB89T635R MB89T637R Setting not possible

Selectable by Can be set per pin* pin

Fixed to without pull-up resistor

Selectable

Setting possible

Fixed to with power-on reset

Selectable

Setting possible

Fixed to 218/FCH (Approx. 26.2 ms)

Selectable

Setting possible

Fixed to with reset output

MB89PV630-101 Single-clock system MB89T635R-101 Single-clock system MB89T637R-101 Single-clock system MB89PV630-102 Dual-clock systems MB89T635R-102 Dual-clock systems MB89T637R-102 Dual-clock systems

Selectable

Setting possible

* : Pull-up resistors cannot be set for P50 to P53.

54

MB89630R Series
s ORDERING INFORMATION
Part number MB89635RP-SH MB89T635RP-SH MB89636RP-SH MB89637RP-SH MB89P637P-SH MB89T637RP-SH MB89635RPF MB89T635RPF MB89636RPF MB89637RPF MB89P637PF MB89T637RPF MB89635RPFM MB89636RPFM MB89637RPFM MB89T635PFM MB89W637C-SH MB89PV630CF MB89PV630C-SH Package Remarks

64-pin Plastic SH-DIP (DIP-64P-M01)

64-pin Plastic QFP (FPT-64P-M06)

64-pin Plastic QFP (FPT-64P-M09) 64-pin Ceramic SH-DIP (DIP-64C-A06) 64-pin Ceramic MQFP (MQP-64C-P01) 64-pin Ceramic MDIP (MDP-64C-P02)

55

MB89630R Series
s PACKAGE DIMENSIONS
64-pin Plastic SH-DIP (DIP-64P-M01)
58.00 0.55 +.008 2.283 .022
+0.22

INDEX-1 INDEX-2

17.000.25 (.669.010)

5.65(.222)MAX 3.00(.118)MIN 1.00 0 +.020 .039 0 1.7780.18 (.070.007) 1.778(.070) MAX 55.118(2.170)REF
+0.50

0.250.05 (.010.002) 0.450.10 (.018.004) 0.51(.020)MIN 15MAX 19.05(.750) TYP

1994 FUJITSU LIMITED D64001S-3C-4

Dimensions in mm (inches)

64-pin Plastic QFP (FPT-64P-M06)

51

24.700.40(.972.016) 20.000.20(.787.008)
33

3.35(.132)MAX
(Mounting height)

0.05(.002)MIN (STAND OFF)

52

32

14.000.20 (.551.008) INDEX

64 20

18.700.40 (.736.016)

12.00(.472) REF

16.300.40 (.642.016)

"A" LEAD No.

1 19

1.00(.0394) TYP

0.400.10 (.016.004)

0.150.05(.006.002) 0.20(.008)
M

Details of "A" part 0.25(.010) "B" 0.10(.004) 18.00(.709)REF 22.300.40(.878.016) 0.30(.012) 0.18(.007)MAX 0.63(.025)MAX

Details of "B" part

0 10 1.200.20 (.047.008)

1994 FUJITSU LIMITED F64013S-3C-2

Dimensions in mm (inches)

56

MB89630R Series

64-pin Plastic QFP (FPT-64P-M09)

48

14.000.20(.551.008)SQ 12.000.10(.472.004)SQ
33

1.50 0.10 +.008 .059 .004

+0.20

(Mounting height)

49

32

9.75 (.384) REF 1 PIN INDEX

13.00 (.512) NOM

64

17

LEAD No.

16

Details of "A" part "A"

M

0.65(.0256)TYP

0.300.10 (.012.004)

0.13(.005)

0.127 0.02 +.002 .005 .001

+0.05

0.100.10 (STAND OFF) (.004.004)

0.10(.004) 0 10

0.500.20 (.020.008)

1994 FUJITSU LIMITED F64018S-1C-2

Dimensions in mm (inches)

64-pin Ceramic SH-DIP (DIP-64C-A06)

56.900.56 (2.240.022)

R1.27(.050) REF

8.89(.350) DIA TYP 18.750.25 (.738.010)

INDEX AREA

1.270.25 (.050.010) 5.84(.230)MAX 0.250.05 (.010.004) 3.400.36 (.134.014) 1.7780.180 (.070.007) 0.900.10 (.0355.0040) 55.118(2.170)REF 0.46 0.08 +.005 .018 .003
+0.13

19.050.25 (.750.010)

0~9

1.45(.057) MAX

1994 FUJITSU LIMITED D64006SC-1-2

Dimensions in mm (inches) 57

MB89630R Series

64-pin Ceramic MQFP (MQP-64C-P01)

INDEX AREA

18.70(.736)TYP 16.300.33 (.642.013) 15.580.20 (.613.008) 12.00(.472)TYP 1.20 0.20 +.016 .047 .008
+0.40

1.000.25 (.039.010)

1.000.25 (.039.010)

1.270.13 (.050.005) 22.300.33 (.878.013) 24.70(.972) TYP 0.30(.012) TYP 18.120.20 12.02(.473) (.713.008) TYP 10.16(.400) 14.22(.560) TYP TYP

18.00(.709) TYP

1.270.13 (.050.005)

0.30(.012)TYP 7.62(.300)TYP 9.48(.373)TYP 11.68(.460)TYP

0.400.10 (.016.004)

0.400.10 (.016.004)

1.20 0.20 +.016 .047 .008

+0.40

0.50(.020)TYP

10.82(.426) 0.150.05 MAX (.006.002)

1994 FUJITSU LIMITED M64004SC-1-3

Dimensions in mm (inches)

64-pin Ceramic MDIP (MDP-64C-P02)

56.900.64 (2.240.025)

0~9

15.24(.600) TYP

18.750.30 (.738.012)

19.050.30 (.750.012)

INDEX AREA

2.540.25 (.100.010) 33.02(1.300)REF

0.250.05 (.010.002)

10.16(.400)MAX

1.270.25 (.050.010)

1.7780.25 (.070.010)

0.46 0.08 +.005 .018 .003 55.12(2.170)REF

+0.13

0.900.13 (.035.005)

3.430.38 (.135.015)

1994 FUJITSU LIMITED M64002SC-1-4

Dimensions in mm (inches)

58

MB89630R Series

FUJITSU LIMITED
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.

F9609 FUJITSU LIMITED Printed in Japan