1

Unit- 5

Sequential Logic
Circuits

Unit- 5

Sequential

Combinationa l circuits z The outputs are entirely dependent on the current inputs Sequential circuits
z z

Contains no storage elements, no feedback

Storage/memory elements
z z z

Consists of a combinational circuit to which storage elements are connected to form a feedback path z Outputs are a function of both the current inputs and the present state of the storage elements capable of storing binary information defining the state of the sequential circuit Next state is a function of external inputs and current state

(inputs, current state) (outputs, next state)

Types of Sequential Circuits

Two major types: depending on timing of their signals Asynchronous sequential circuits (see Chapter 9)
The transition happens at any instant of time z Do not use clock pulses. Change of internal state occurs when there is a change in input variables
z

Instability problem: may become unstable at times May be regarded as a combinational circuit with feedback

Storage elements work as time-delay device

Synchronous sequential circuits

The transition happens at discrete instants of time z The circuit responds only to pulses on particular inputs z Storage elements are affected only with the arrival of each pulse
z

Synchronous Clocked Sequential Circuits

Clocked sequential circuits (CSC) z Synchronous sequential circuits that use clock pulses
in the inputs of storage elements z Synchronization is achieved by a master-clock generator to generate a periodic train of clock pulses z most commonly used, no instability problems

Flip-flops: the storage elements used in CSC

binary cells capable of storing one bit of information z Maintains a binary state indefinitely until directed by an input signal to switch states
z

The states change only during a clock pulse transition

major differences in the number of inputs they possess and in the manner in which the inputs affect the binary

state

The outputs can come either from the combinational circuit or from the flip-flops or both The flip-flops receive their inputs from the combinational circuit and also from a clock signal with pulse that occurs at fixed intervals of time
z

The flip-flop cannot change and the feedback loop is broken when a clockoutputs pulse is not active

5-2 Latches

Latches: basic circuits to construct flip-flops

z

capable of storing binary information, impractical for use in synchronous sequential circuits

more complicated types can be built upon it

SR Latch
z

Two states: Set and Reset states z an asynchronous sequential circuit with two cross-coupled NOR gates
z

S-R Latch

SR latch with two cross-coupled NAND gates

0 signal to change its state

SR latch with control input

z

Determines when the state of the latch can be changed eliminate undesirable condition of indeterminate state in

D Latch
z

SR latch

10

SR Latch
Two inputs labeled S for set and R for reset
(S,R)=(1,0): set (Q=1, the set state) (S,R)=(0,1): reset (Q=0, the reset/clear state) (S,R)=(0,0): normal condition
z z

no operation, in either the set or the reset state depending on which input was most recently at 1 consider (S,R) = (1,1) (0,0)

(S,R)=(1,1): indeterminate state (Q=Q'=0)

z

unpredictable next state when both inputs return to 0 (depend on which input returns to 0 first) Q = [R+(S+Q)] = R(S+Q) Q = [S+(R+Q)] = S(R+Q)

11

(S+Q) (R+Q)

12

S-R Latch SR Latch with NAND Gates

0 signal to change its state (S,R)=(0,1): set
(Q=1, the set state) (S,R)=(1,0): reset (Q=0, the reset/clear state) (S,R)=(1,1): normal condition (S,R)=(0,0): indeterminate state (Q=Q=1)
unpredictable next state

13

14

SR Latch with Control Input

An additional input as an enable signal
C=0 quiescent condition, no change C=1 S or R is allowed to affect the SR latch (1 signal to change its state)
15

S_ 1/S'

0/1

R_ 1/R'

16

D Latch
S=D and R=D
Ensure S and R are never equal to 1 at the same time z Eliminate the undesirable conditions of the indeterminate state in the RS latch
z

One output Q and two inputs: D (data) and C (control)

Q=D Q = no change

when C=1 when C=0

11

S_ 1/D' 0/1 1/D R_

Graphic Symbols for Latches

12

5-3 Flip-Flops

A trigger: the momentary change to switch the state of a latch or flip-flop

z

Types of triggers
z

The transition it causes is said to trigger the flip-flop Level triggered latches

Edge triggered flip-flops

D latch is triggered every time the pulse stays at logic 1 level. Be used as a temporary storage between a unit and its environment If level-triggered flip-flops are used, the feedback path may cause instability problem as long as the clock pulse stays in the active level triggered only during a signal transition (01 or 10)

13

Edge-triggered D flip-flop
Store binary info during transition Method 1: Master-slave D flip-flop
z

two separate flip-flops a master flip-flop (positive-level triggered)

a slave flip-flop (negative-level triggered) change only during negative edge of clock
z

longer

propagation delay

14

Edge-triggered D flip-flop (cont.)

Method 2: D-type positive-edge-triggered flip-flop
zCLK=0

CLK=positive transition Q=D (state changes once) D=0 when CLK becomes 1 R=1 to 0 D changes further, no effect D=1 when CLK becomes 1 R=stay 1 D changes further, no effect CLK=negative transition or 1 quiescent condition (state holds)
(RD) S [S(RD)] S (RD) R R=CLK+S+RD (RD) [S(RD)]=S+RD S=CLK+S(RD)

S=R=1, no change The most efficient flip-flop constructed with 3 SR latches

Q=R Q=D

15

(RD) S

[S(RD)]=S+RD S=CLK+S(RD)

D=0
S=CLK+S R=CLK+S

D=1
S=CLK+SR CLK=0 S=R=1 D= 0 Q=Q S=R=1 D= 1 Q=Q R=CLK+(SR) [S(RD)] S (RD ) R R=C LK+ S+ RD =C LK + [S( R D) ]

CLK=1 S=S R=S S=SR

R=(SR)

(R

D)

S=0, R=1, Q=1

0 1 2 3 4

t
12 20 28 30

5 6 7 8 9 10 14 22 16 24 18 26

CLK __-- -- -- --- -- -- -D ------------_ Q -

Setup Time and Hold Time

Setup time a minimum time for which the D input must be

maintained at a constant value (or be ready) prior to the occurrence of the clock transition data to the internal latch

Hold time

a minimum time for which the D input must not changes after the application of the positive transition of the clock clock to the internal latch

These parameters are usually specified in manufacturers data books.

17

Graphic Symbols

> dynamic indicator

18

JK Flip-Flop

Edge-triggered D flip-flop
z z z

Store binary information during edge trigger Require the smallest number of gates Other types of flip-flops can be constructed using it Q no change Q =0 reset to 0 J=1, K=0: D=1 Q =1 set to 1 J=1, K=1: D=Q Q =Q complement output

JK Flip-Flop: D=JQ'+K'Q
J=0, K=0: D=Q J=0, K=1: D=0

19

T Flip-Flop
T (toggle) flip-flop: D = TQ = TQ'+T'Q
T=0: D=Q, no change T=1: D=Q' Q=Q'

20

Characteristic Tables and Equations

Characteristic Tables

Characteristic equations D flip-flop Q(t+1) = D

JK flip-flop Q(t+1) = JQ+KQ

T flop-flop

Q(t+1) = TQ = TQ + TQ

21

Direct Inputs
preset/direct set: the inputs that sets the flip-flop to 1 clear/direct reset: the inputs that clears the flip-flop to 0

to a known starting state

asynchronous reset

reset=0 force Q=0, resetting

22

5-4 Analysis of Clocked Sequential Circuits

State equation (transition equation)

A(t+1) = A(t)x(t) + B(t)x(t) B(t+1) = A(t)x(t) y(t)=[A(t) +B(t)]x(t) or A(t+1)=Ax+Bx B(t+1)=Ax y=(A+B)x

CSC diagram state equation

35

state table state equation CSC diagram Four sections: present state, input, next state and output List all possible binary combinations of present state and inputs

State Table or Transition Table

Determine next states and outputs from the logic diagram or from the state equations

A(t+1)=Ax+
36

Bx B(t+1)=Ax y=(A+B)x m flip-flops and n inputs

m+n

2 rows m column of next-state

37

Second Form of State Table

Only 3 sections: present state, next state, and output

z

Given one input, there are two possible next states and outputs for each present state

38

What form to be used depends on applications

State Diagram - pictorial view of state transitions

input/output x/y

A(t+1)=Ax+Bx

B(t+1)= Ax y=(A+B

)x

state diagram state table state equation logic diagram 26

Input/Output Equations

logic diagram of a sequential circuit consists of flip-flops + gates

z

output equations: the circuit that generates external outputs z input equations: the circuit that generates inputs to flip-flops

output equations input state equations characteristic equations (or excitation equations) equations

Symbol
41

convention: DQ = x + y an OR y gate with inputs x and y connected to the D input of a flip-flop whose output is labeled with the symbol Q

42

Flip-Flop Input Equations

FF Input Equations State Equations DA=Ax+Bx A(t+1)=Ax+Bx B(t+1)=Ax D =Ax B Output Equation y=(A+B)x y=(A+B)x D/JK/T FF input equation state equation CSC logic diagram state diagram state table

Analysis with D Flip-Flops

Given: input function: D =Axy state equation: A(t+1)=Axy one flip-flop and 2 inputs
A

Find: logic diagram state table state diagram

Given logic circuit, find the others

Analysis with JK Flip-Flops

(1) Flipequation

(2) State

(3)

(4)

30

equation: Q(t+1)=TQ=TQ+TQ Input equations and output equation: T =Bx; A TB=x; y=AB State equations A(t+1)=(Bx)A+(Bx)A=AB+Ax+ABx B(t+1)=xB

Analysis with T FlipFlops Characteristic

31

Given logic circuit, find the others

Mealy and Moore Models

Mealy model

The output is a function of both the present state and input

The outputs may change if the inputs change during the clock cycle The outputs may have momentary false values due to delay To synchronize, the outputs must be sampled only during the clock edge

Mealy finite state machine (FSM, machine): the Mealy model of a sequential circuit example: Fig. 5-15 (D)

Moore model

The output is a function of the present state only

The outputs are synchronized with the clock

Moore finite state machine (FSM, machine): the Moore model of a sequential circuit example: Figure 5-19 (JK), 5-20 (T)

50

5-6 State Reduction and Assignment

Sequential circuit analysis:

z z

starts from a circuit diagram and culminates in a state table or state diagram starts from a set of specifications and culminates in a logic diagram

Sequential circuit design:

z z

State reduction problem: reduction of the number of flip-flops in a sequential circuit, while keeping the external input-output requirements unchanged
m
z z

m flip-flops produce 2 states fewer State reduction flip-flops

but may require more combinational gates

51

State Reduction

Example: Figure 5-22 (7 states)

z z

Given a state table or state diagram Find ways of reducing the number of states without altering the input-output relationships

52

Test sequence
Initial state: a Input sequence: 01010110100

53

State Equivalence
State equivalence: Two states are equivalent if, for each member of the set of inputs, they

give exactly the same output and send the circuit either to the same state or to an equivalent state

Algorithm: 1.Look for two present states that

go to the same next state and have the same output for both input combinations

2.Remove one of the equivalent state and replace by the other state each time it occurs in the table
Another approach: systematic reduction with an implication table
54

(see Section 9-5)

55

State Reduction Example

36

State Assignment

State assignment: assign coded binary values to the state

z z

In order to design a sequential circuit with physical components A circuit with m states need n bits where 2n >= m To distinguish it from a stable table with symbolic names for states

Transition table: a state table with a binary assignment

z

37

5-7 Design Procedure

Design of a clocked sequential circuit

z z z

Tasks
z z

starts from a set of specifications obtains a state table/diagram (or equivalences) first culminates in a logic diagram (or a list of Boolean functions) Choosing the flip-flops

Finding a combinational gate structure

Determined from the number of states needed Derived from the state table by evaluating the flip-flop input equations and output equations

Synthesis

Summarized procedure
most challenging

38

Example: Sequence Detector

Specification: Design a circuit that detects three or more consecutive 1s in a string of bits combining through an input line 1st Step deriving state diagram or state table

62

Moore model circuit output is 1 when circuit is in state S3 and 0 otherwise

63

Synthesis Using D Flip-Flops

Step 2-4: Assign binary codes and list state table (Table 5-11) Step 5:Choose type of flip-flops Step 6:Derive simplified input and output equations

0 1 2 3

4 5 6 7

64

65

Synthesis Using D Flip-Flops (cont.)

Step 7 Draw the logic diagram (using simplified functions)

Excitation table: a table that lists required inputs

66

Analysis and Design

present states input equations
characteristic equations

output equations state equations

(1) Input/output equations (2) state equations (3) State table (4) State diagram

?
present states input equations

output equations next states

Table Excitation

(1) State diagram/table (2) Input/output equations (3) Circuit diagram

42

Excitation Tables
The input equations for the circuit using flip-flops other than the D type, i.e. JK and T types, must be derived indirectly from the state table Excitation table: list the required inputs for a given

change of state

43

Synthesis Using JK Flip-Flops

The input equations must be evaluated from the present-state to next-state transition derived from the excitation table

(1) (2)

44

Logic Diagram for Sequential Circuit with JK Flip-Flops

(3)

JA=Bx

A=Bx

JB=x

KB=(A x)

45

Synthesis Using T Flip-Flops

Example: 3-bit counter
(0) (1)

(2)

46

Logic Diagram of 3-Bit Binary Counter

(3)

TA2=A1A0
75

TA1=A0

TA0=1

Summary
Chapter 5 Synchronous Sequential Logic 5-1 Sequential Circuits 5-2 Latches

SR latch, SR latch, D latch edge-triggered D, JK, T flip-flops

5-3 Flip-Flops

5-4 Analysis of Clocked Sequential Circuits 5-5 HDL for Sequential Circuits 5-6 State Reduction and Assignment 5-7 Design Procedure
circuit diagraminput equationstate equationstate tablestate diagram