PLL PDF

Phase-Locked Loops
Jieh-Tsorng Wu
May 12, 2003
A
1896
E S
National Chiao-Tung University
Department of Electronics Engineering
Phase-Locked Loops (PLLs)
A
V
i
c
o
A
Filter
Phase
Detector
Loop
VFO
A
i
= g
1
(
i
t +
i
) A
o
= g
2
(
o
t +
o
)
o
=
oo
+ K
c
V
c
g
1
and g
2
are periodic functions with 2 period.
When the loop is locked, the frequency of the VCO is exactly equal to the average
frequency of the input.
The loop lter is a low-pass lter that suppresses high-frequency signal components
in the phase dierence.
PLLs 29-2 Analog ICs; Jieh-Tsorng Wu
Phase-Locked Loops (PLLs)
Applications:
Automatic frequency control.
Frequency and phase demodulation.
Data and clock recovery.
Frequency synthesis.
References:
Roland E. Best, Phase-Locked Loops,, 2nd Edition, McGraw-Hill, Inc., 1993.
Dan H. Wolaver, Phase-Locked Loop Circuit Design, Prentice-Hall, Inc., 1991.
Floyd M. Gardner, Phaselock Techniques, 2nd Edition, John Wiley & Sons, 1979.
Basic Model
V
d
V
c
PD
Detector
Phase
VFO
F(s)
Filter
o
V
d
= K
d
(
i

o
)
o
=
oo
+ K
o
V
c
K
o
/s
When the PLL is locked,
V
d
(s) = K
d
[
i
(s)
o
(s)] = K
d
e
(s)
e
=
i

o
V
c
(s) = F (s) V
d
(s)
_

o
dt =
oo
t +
_
K
o
V
c
dt =
oo
t +
o

o
(s) = V
c
(s)
K
o
s

e
is the phase error, K
d
is the phase-detector gain factor, and K
o
is the VCO gain
factor.
Basic Model
System equations are
V
d
= K
d
(
i

o
) = K
d

e
V
c
= F (s) V
d

o
= V
c
K
o
s
The transfer functions are
i
=
K
o
K
d
F (s)
s + K
o
K
d
F (s)
= H(s)
i
=
s
s + K
o
K
d
F (s)
= 1 H(s)
V
c
i
=
sK
d
F (s)
s + K
o
K
d
F (s)
=
s
K
o
H(s)
H(s) =

o
i
= K
o
V
c
i
=
i

oo

o
=
o

oo
H(s) is the closed-loop transfer function.
Second-Order PLL Active Lag-Lead Filter
V
i
V
o
R
2
1
R
C
F (s) =
s
2
+ 1
s
1
1
= R
1
C
2
= R
2
C
H(s) =
2
n
s +
2
n
s
2
+ 2
n
s +
2
n
n
=
_
K
o
K
d
1
=

n
2

2

n
is the pole frequency of the loop.
is the damping factor. Q
p
= 1/(2) is the pole quality factor.
Second-Order PLL Passive Lag-Lead Filter
V
i
V
o
1
R
R
2
C
F (s) =
s
2
+ 1
s
1
+ 1
1
= (R
1
+ R
2
)C
2
= R
2
C
H(s) =
s
_
2
n

2
n
/(K
o
K
d
)
_
+
2
n
s
2
+ 2
n
s +
2
n
n
=
_
K
o
K
d
1
=

n
2
_
2
+
1
K
o
K
d
_
If R
2
= 0, then
1
=
1
R
1
C
=
1
LF
n
=
_
K
o
K
d
LF
=

n
2K
o
K
d
H(s) =

2
n
s
2
+ 2
n
s +
2
n
High-Gain Second-Order PLL Frequency Response
If K
o
K
d
2
>1 in the passive lter, then
H
passive
(s) H
active
(s) =
2
n
s +
2
n
s
2
+ 2
n
s +
2
n
And the 3 dB bandwidth of H(s) is
3dB
=
n
_
2
2
+ 1 +
_
(2
2
+ 1)
2
+ 1
_
1/2
Usually choose
n
<
i
/10 to remove the high-frequency components at
i
, 2
i
,
. . . , existing in the phase detectors output.
The PD outputs high-frequency components can show up as spurious tones in the
frequency spectrum of the PLLs output.
High-Gain Second-Order PLL Frequency Response
|

H

(

j

)

|

(
d
B
)
0.1 1 10
10
5
0
-5
-10
-15
-20
Frequency (/
n
)
= 5.0
= 2.0
= 0.707
= 0.5
= 0.3
Step Response of a Two-Pole System
Consider the following two-pole transfer function
H(s) =

2
n
s
2
+ 2
n
s +
2
n
Poles = s
1,2
=
_

_
2
1
_
n
If > 1, the system is overdamped, and both poles are real.
Step Response = 1
1
2
_
2
1
_
1
k
1
e
k
1
n
t
1
k
2
e
k
2
n
t
_
k
1
=
_
2
1 k
2
= +
_
2
1
If = 1, the system is critically damped, and both poles are at
n
.
Step Response = 1 (1 +
n
t)e
n
t
1 e
n
t/(2)
if 4
2
>1
Step Response of a Two-Pole System
If < 1, the system is underdamped.
Step Response = 1
_
d
sin
d
t + cos
d
t
_
e
n
t
d
=
_
1
2

n
% Overshoot = 100e
/
1/
2
1
1
Overshoot
Error Band
t
S
t
e
p

R
e
s
p
o
n
s
e
For PLL, choose > 1/
2 = 0.707 to avoid excessive ringing.

Phase Jitter
Probability
Density
V
s
n
c
n
t
V
N
n

n
pdf =
1
2
n
e
2
n
/(2
2
n
)
v(t) = s(t) + n(t) = V
s
sin(2f
o
t) + n(t)
n(t) = n
c
(t) sin(2f
o
t) + n
t
(t) cos(2f
o
t)
The phase jitter is
n
(t) = tan
_
n
t
(t)
V
s
+ n
c
(t)
_
n
t
(t)
V
s
Phase Jitter
Assume that
n
2
=
1
2
n
2
c
+
1
2
n
2
t
n
2
c
= n
2
t
Then, we have
2
n
=
2
n
=
n
2
t
V
2
s
=
n
2
V
2
s
=
1
2
1
SNR
SNR is the signal-to-noise ratio, and can be expressed as
SNR
V
2
s
/2
n
2
Phase Noise
Power
Spectral
Density
Freq
P
s
P
ssb
L(f
m
)
f
o
f
m
v(t) = V
s
sin[2f
o
t +
n
(t)]
Phase Noise
The phase noise L(f
m
), usually in dBc, is the ratio of the single-sideband (SSB) power
in a 1-Hz bandwidth f
m
Hz away from the carrier to the total signal power, i.e.,
L(f
m
)
P
s
P
ssb
Let S
n
(f ) be the power spectral density of
n
(t) in frequency domain, it can be shown
that
S
n
(f
m
) 2L(f
m
) and
2
n
=
_

0
S
n
(f )df
PLL Noise Response
F(s)
i

o
n,i

n,vf o
n
v
c
K
d
K
o
/s
Let
n,o
be the phase noise in
o
, we have
S
n,o
S
n,i
=
_
_
_
_
K
o
K
d
F (s)
s + K
o
K
d
F (s)
_
_
_
_
2
s=j
= |H(j)|
2
S
n,o
S
n,vf o
=
_
_
_
_
s
s + K
o
K
d
F (s)
_
_
_
_
2
s=j
= |1 H(j)|
2
S
n,o
S
n
v
c
=
_
_
_
_
K
o
s + K
o
K
d
F (s)
_
_
_
_
2
s=j
=
_
_
_
_
[1 H(j)]
K
o
j
_
_
_
_
2
PLL Noise Response
Consider only a white noise S
n,i
(f ) in
i
,
2
n,o
=
_

0
S
n,i
(f )|H(j2f )|
2
df = S
n,i
(f ) B
L
B
L
is the noise bandwidth of H(j2f ), i.e.,
B
L

_

0
|H(j2f )|
2
df
For the 2nd-order PLL with active lag-lead lter
B
L
=
1
2
n
_
+
1
4
_
B
L,mi n
occurs at = 0.5.
B
L
< 1.25B
L,mi n
for 0.25 < < 1.0.
Phase Detection Using Analog Multiplier
V
1
V
2
V
d
V
d
e
1
2
3
2
1
2
3
2
2
V
1
(t) = V
1
sin(t +
1
) V
2
(t) = V
2
cos(t +
2
)
V
d
(t) = kV
1
(t)V
2
(t) =
1
2
kV
1
V
2
[sin(
1

2
) + sin(2+
1
+
2
)]
Phase Detection Using Analog Multiplier
The 2component will be ltered out by the loop lter, hence consider the dc component
only
V
d
=
1
2
kV
1
V
2
sin(
1

2
) = K
d
sin(
e
)
e
=
1

2
K
d
is the phase-detector gain factor, and
e
is the phase error.
If
e
<1, v
d
K
d
e
.
V
1
(t) and V
2
(t) are 90
out of phase when

e
= 0.
PLL Tracking Performance Hold-In Range
From the nal value theorem
lim
t
e
(t) = lim
s0
s
e
(s) = lim
s0
s
2
i
(s)
s + K
o
K
d
F (s)
The hold-in range,
H
, is the frequency range in which a PLL can maintain lock
statically.
i
=
o
+
H

i
(t) =
H
t
i
(s) =
H
/s
2
lim
t
e
(t) =

H
K
o
K
d
F (0)
For a sinusoidal PD, the criterion becomes
lim
t
sin
e
(t) =

H
K
o
K
d
F (0)
< 1
H
= K
o
K
d
F (0)
For a 2nd-order PLL with active lter, F (0) , thus
H
.
PLL Tracking Performance Pull-Out Range
The pull-out range
P O
is the frequency-step limit below which the PLL does not skip
cycles but remains in lock.
For a sinusoidal PD
P O
= 1.8
n
( + 1) for 0.5 < < 1.4
Noisy PLL Tracking Performance
Dene the SNR of a PLL as
SNR
L

1
2
2
n,o
As a rule of thumb, SNR
L
> 6 dB is required for stable operation.
For low SNR
L
, the VFO phase occasionally slips one or more cycles as compared to the
input. Dene T
AV
as the average time between cycle slips.
For a 1st-order loop T
AV

4B
L
e
4SNR
L
, where B
L
is the PLL noise bandwidth.
For a 2nd-order loop with = 0.707 T
AV

1
B
L
e
SNR
L
.
The slips of a 1st-order loop are almost always single, isolated events.
The slips in a 2nd-order loop tend to bunch in bursts.
PLL Acquisition Behavior
i
V
o
V
F(s)
Phase
Detector
VFO
Loop Filter
The process of bringing a PLL into lock is called acquisition.
Acquisition is inherently a nonlinear phenomenon.
An nth-order PLL contains n integrators (VFO, capacitors, . . . ). With each integrator
there is associated a state variable of the loop: phase, frequency, frequency rate,
and so on. To force the loop into lock, it is necessary to bring each of the state
variables close to the corresponding parameters of the input signal. Therefore, we
should speak of phase acquisition, frequency acquisition, and so forth.
Phase Acquisition of a First-Order Loop
V
i
V
d
V
o
Phase
Detector
VCO
e
K
o
K
d
K
o
K
d
sin
e
V
d
= K
d
sin
e

o
=
oo
+ K
o
V
d

e
=
i

o
e
=
i

o
=
i
t
oo
t
_
t
0
K
o
K
d
sin
e
dt
o
(0)
d
e
dt
=

e
= K
o
K
d
sin
e
=
i

oo
The loop is locked when

e
= 0.
There is no cycle skipping in the acquisition process.
Phase Acquisition of a Second-Order Loop
The lock-in range,
L
, is the frequency range over which the PLL can acquire lock
without cycle slipping.
By practical considerations, the lock-
in process of a higher-order loop is
so fast that it can be approximated by
the phase acquisition process of a 1st-
order loop with gain K = K
o
K
d
F ().
logf
log|F (jf )|
F () =

2
1
For a PLL with with sinusoidal PD,
Lock-In Range =
L
K
o
K
d
F () = 2
n
Lock-In Time = T
L

1
n
Frequency Acquisition The Pull-In Process
The pull-in range,
P
, is the
maximum initial frequency
oset for the pull-in process
to occur.
t
o
T
p
For a 2nd-order PLL,
Pull-In Range =
P

8
n
K
o
K
d

2
n

8
n
K
o
K
d
if K
o
K
d
>
n
Pull-In Time = T
p

2
2
3
n
Aided Frequency Acquisition Frequency Sweeping
V
i
Loop
Filter
Phase
Detector
Detector
Lock Sweep
Generator
VFO
Use sweep to bring the VFO close to the frequency of locking.
Aided Frequency Acquisition Loop Filter Switching
V
i
Phase
Detector
Detector
Lock
VFO
Low R if unlocked; High R if locked
Loop Filter
Low R
High R
The frequency pull-in can be painfully slow in a narrowband loop. Sometimes, a wider
loop bandwidth is preferred.
Aided Frequency Acquisition Dual Loops
i
V LP
LP
Detector
Filter 1
Filter 2
Phase
VFO
Detector
Frequency
Contains a phase-locked loop (PLL) and a frequency-locked loop (FLL).
The FLL should dominate during frequency acquisition.
The PLL should dominant when the phase is locked.
Digital Phase-Locked Loops (DPLLs)
o
V
V
i
V
d
V
c
F(s)
1/N
PD
Loop Filter
VFO
Frequency Divider
To calculate loop dynamics, combine the VFO and the frequency divider as a new VFO.
o
=
oo
+ K
o
V
d

t
o
=

N
=

oo
N
+
K
o
N
V
d
=
t
oo
+ K
t
o
V
d
t
oo
=

oo
N
K
t
o
=
K
o
N

t
o
=

o
N

i
and
o
are not available except during the rising and falling transitions.
XOR Phase Detector
u1
u2
Q
u1
u2
Q
0
u1
u2
Q
u1
u2
Q
Averaged Q
The PD characteristic is strongly dependent on the duty-cycle of u

1
and u
2
.
Edge-Triggered Set-Reset Phase Detector
S
R
Q
u1
u2
Q
u1
u2
Q
u2
u1
u1
u2
Q
Frequency Discrimination Capability
0
Averaged Q
u1
u2
Q
u1
u2
Q
2
Edge-Triggered Set-Reset Phase Detector
The PD is edge-sensitive, the duty-cycle of u
1
and u
2
is irrelevant.
If f
1
> f
2
or f
1
< f
2
, the PD has frequency discrimination capability, which can
improve frequency acquisition speed of the PLL.
However, when f
1
f
2
, the frequency-sensitive behavior is lost, and the PLL relys on
the pull-in process for frequency acquisition.
Sequential Phase-Frequency Detector (PFD)
R
Q D
u1
u2
UP
0
u1
u2
UP
Averaged (UP-DW)
R
D Q
1
1
u1
u2
UP
DN
DN
DN
2
Sequential Phase-Frequency Detector (PFD)
The PFD is edge-sensitive, the duty-cycle of u
1
and u
2
is irrelevant.
The PFD can discriminate the frequency dierence for even the smallest f
1
f
2
.
A PLL with the PFD can have innite pull-in range. The frequency acquisition aid
provided by the PFD is akin to frequency sweeping.
When using the PFD, a missing transition or an extra one in either u
1
or u
2
can cause
a large error signal to appear. The eects will propagate for more than one cycle.
Great caution is required to use the PFD in a noisy environment.
Charge-Pump Phase-Locked Loops
V
i
V
o
V
c
I
P
I
P
I
e
UP
PFD
R
C
VFO
DN
u1
u2
The on time of either UP or DN is t
p
= |
e
|/
i
for each period 1/f
i
of the input signal.
The average error current I
e
over a cycle is
I
e
= I
P

t
p
T
i
= I
P

e
2

i
= 2f
i
=
2
T
i
The voltage V
c
can be expressed as
V
c
(s) = I
e
(s)
_
R +
1
sC
_
=
e
(s)
I
P
2
_
R +
1
sC
_
V
c
(s)
e
(s)
= K
d
F (s) =
I
P
2
_
R +
1
sC
_
The VFO has the following characteristic:
o
=
oo
+ K
o
V
c
f
o
= f
oo
+ K
t
o
V
c
K
t
o
=
K
o
2
Using the continuous-time approximation, we have
e
(s)
i
(s)
= H
e
(s) =
s
2
s
2
+ 2
n
s +
2
n
o
(s)
i
(s)
= H(s) = 1 H
e
(s)
n
=
_
K
t
o
I
P
C
_
1/2
=
1
2
_
K
t
o
(I
P
R) (RC)
_
1/2
The PLL behaves as a 2nd-order loop with active lag-lead lter.
Discrete-time model can be used for more accurate analysis. Reference: Hein, z-
Domain Model for Discrete-Time PLLs, Trans. CAS, 11/88, pp. 13931400.
During the pump interval t
p
, a voltage step of I
P
R occurs at the VFO input. This
granularity eect may be intolerable in some systems.
The voltage step I
P
R may overload the VFO, making the previous linear analysis
invalid.
The granularity eect can be mitigated with an additional capacitor C
p
in parallel with
the earlier RC network, thus forming a 3rd-order PLL.
Reference: Floyd Gardner, Charge-Pump Phase-Lock Loops, IEEE Trans. Commun.,
Nov. 1980, pp. 18491858.
PFD and Charge-Pump Filter
I
P2
I
P1
Dead Zone
DN
UP
S1
S2
C
R
Q D
R
D Q
1
1
u2
u1
V
c
V
c
e
The dead zone is caused by the slowness of the S1 and S2 switches.
PFD and Charge-Pump Filter
When
e
falls in the dead zone, the PFDs conversion gain is decreased, causing a
reduction in
n
and , and the degradation of
o
phase noise.
The dead zone can be eliminated by allowing UP and DN to be activated
simultaneously for a short time even if the phase dierence is zero. Then, any
mismatch between I
P 1
and I
P 2
can cause a phase oset and consequently spurs
in the output spectrum.
The nite output impedance of the I
P 1
and I
P 2
current sources can also cause phase
oset.
Charge sharing in the S1 and S2 switches can also cause glitches at V
c
.
PFD with Delayed Reset
DN
UP
u2
u1
Delay
Third-Order Charge-Pump PLLs
I
P
I
P
I
e
V
c
UP
DN
0
R1
C1
C2
t

p
|L(j)| (dB)
The loop lter transfer function is
V
c
(s)
e
(s)
= K
d
F (s) =
I
P
2
__
R
1
+
1
sC
1
_
[
1
sC
2
_
=
I
P
2s(C
1
+ C
2
)

sR
1
C
1
+ 1
sR
1
(C
1
[C
2
) + 1
z
=
1
R
1
C
1
p
=
1
R
1
(C
1
[C
2
)
Third-Order Charge-Pump PLLs
The loop gain of the 3-order PLL is
L(s) =
K
o
s
K
d
F (s) =
K
t
o
I
P
s
2
(C
1
+ C
2
)
s/
z
+ 1
s/
p
+ 1
Let
t
/
z
= > 1 and
p
/
t
= > 1, then
t

K
t
o
I
P
(C
1
+ C
2
)
z
= K
t
o
I
P
R
1
C
1
C
1
+ C
2
R
1
=
1
K
t
o
I
P

t
C
1
= K
t
o
I
P

2
t
C
2
= K
t
o
I
P

1

2
t
= 4 and = 4 gives a phase margin 60
.
Multi-Path Charge-Pump Filter
V
a
V
b
V
c
C
a
R
b
C
b
V
c
V
a
V
b
I
e1
I
e2
z

t

p
I
e1
= I
P 1

e
2
I
e1
= I
P 2

e
2
Multi-Path Charge-Pump Filter
The loop lter transfer function is
V
c
(s)
e
(s)
= K
d
F (s) =
I
P 1
2

1
C
a
+
I
P 2
2
_
R
b
[
1
sC
b
_
=
I
P 1
2sC
a
sR
b
_
C
b
+ C
a
I
P 2
I
P 1
_
+ 1
sR
b
C
b
+ 1
1
z
= R
b
_
C
b
+ C
a
I
P 2
I
P 1
_
R
b
C
a
I
P 2
I
P 1
1
p
= R
b
C
b
The loops unity-gain frequency is
t

K
t
o
I
P 1
C
a
z
= K
t
o
I
P 2
R
b

z
,
p
, and
t
, can be set using smaller capacitors and resistors.
Reference: J. Craninckx and M. Steyaert, A Fully Integrated CMOS DCS-1800
Frequency Synthesizer, JSSC, 12/98, pp. 20542065.

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Phase-Locked Loops

2 = 0.707 to avoid excessive ringing.

out of phase when

The PD characteristic is strongly dependent on the duty-cycle of u

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