List of Topics for Term Paper 1. Recruiting Decay for Dynamic Power Reduction in Set-Associative Caches 2.

VLSI Architecture of Hybrid Image Compression Model based on Reversible Blockade Transform 3. Low-Power Clock Tree Design for Pre-Bond Testing of 3-D Stacked ICs 4. Single Chip Sensor Node Processor with Communication Centric Design 5. Low Power Delay Optimised Buffer Design . 6. LARGE VLSI ARRAYSPOWER AND ARCHITECTURAL PERSPECTIVES 7. Low power input output port design using clock gating technique 8. Tutorial on Battery Simulation-Matching Power Source to Electronic System 9. Minimum energy cmos design with dual subthreshold supply and multiple logic-level gates 10.An Efficient Algorithm to Selectively Gate Scan Cells for Capture Power Reduction 11.Post Sign-off Leakage Power Optimization 12.Robust design of power-efficient VLSI circuits 13.Dynamic Scan Clock Control for Test Time Reduction Maintaining Peak Power Limit 14.A Survey of Power Estimation Techniques in VLSI Circuits 15.A Compact Thermal Modeling Methodology for Early-Stage VLSI Design 16.Efficient Desiging of Phase Lock Loop 17.MIPS examples of a small system and VGA circuits 18.Comparative analysis of master slave latches and flip flops for high performance and low power systems 19.Reducing cross talk in ALU part of a processor 20.Fault diagnosis in mixed signal low testability system 21.Designing and mapping of a turbo decoder for 3G mobile systems using dynamically reconfigurable architecture

22.Hardware implementation of fast convolution for GPS signal acquisition using FPGA 23.Dynamically re-configurable array architecture for future mobile digital baseband processing 24.A pipelined asynchronus cache system 25.Soft error tolerant asynchronus FPGA 26.Improvisation of Gabor filter design using verilog HDL 27.A new reversible design of BCD adder 28.High speed and ares sufficient vedic multiplier 29.A very fast and low power carry select adder 30.State machine design technique for verilog 31. An entropy based learning hardware organisation using FPGA
32. Design Paradigm for Robust Spin-Torque Transfer Magnetic RAM (STT MRAM) 33. Unified Logical EffortA Method for Delay Evaluation and Minimization in Logic Paths with RC Interconnect 34. Design and Management of Voltage-Frequency Networks Onchip 35. A fuzzy optimization approach for variation aware power minimization during gate sizing 36. High-Speed Interpolation Architecture for 37. Soft-Decision Decoding of Reed-Solomon codes 38. A Process-Tolerant Cache Architecture for Improved Yield in Nanoscale Technologies 39. On-Chip Traffic Modeling and Synthesis for MPEG-2 Video Applications. 40. FPGA Implementation of OFDM.

41.Area-Efficient Advanced Multiuser WCDMA Receiver 42.Model-based Software-defined Radio(SDR) Design using FPGA 43.FPGA-based Implementation of Efficient Sample Rate Conversion for Software Defined Radios 44.FPGA Implementation of a Coherent SOQPSK-TG Demodulator 45.Implementation and Design of Carrier Recovery Loop for High Order QAM Signals 46.Optimization of FPGA Design and Implementation of Timing Recovery

47.Design and Implementation of Costas Loop Based on FPGA 48.FPGA Implementation of an All-Digital T/Z-Spaced QPSK Receiver with Farrow Interpolation Timing Synchronizer and Recursive Costas Loop 49.Implementation of cordic algorithim 50.FPGA Implementation of an Efficient clock circuitry.