JOURNAL OF TELECOMMUNICATIONS, VOLUME 22, ISSUE 1, OCTOBER 2013

14
Design and Simulation of Wideband and Low
Phase Noise UHF Synthesizer
M. Majdi, F. Hodjat Kashani

AbstractDesign and simulation of a UHF wideband and low noise frequency synthesizer from 470 MHz to 860 MHz is presented. The proposed
voltage controlled oscillator (VCO) in the phase lock loop (PLL) covers wide frequency bandwidth of 58% while phase noise performance has been
optimized simultaneously, using parallel tuning diodes in the LC tank of modified Colpitts VCO. The result of the harmonic balance simulation shows
an overall SSB phase noise less than -105 dBc/Hz at 10 KHz offset. The output power is more than 0dBm with maximum variation of 0.93 dB while
using a high pass filter in the output.

Index TermsFrequency Synthesizer, SSB phase noise, Voltage Controlled Oscillator (VCO), Resonator Circuit, phase lock loop (PLL).


1 INTRODUCTION
The explosive growth of todays telecommunication
market has brought an increasing demand for high
performance, low cost, low power consumption radio
frequency circuits. Among all the RF blocks, the design of
voltage-controlled oscillators (VCOs), which generate the
LO carrier signal, is a major challenge and thus has
received the most attention in recent years, as evidenced
by the large number of publications [1-9]. The LOs are
usually a frequency-synthesizer based on a phase locked
loop (PLL) as depicted in the Fig. 1, in which the output
oscillation signal is provided by a VCO.
Due to the ever-increasing demand for bandwidth in
communications, very stringent requirements are placed
on the spectral purity of LOs, making the VCO design as a
critical sub-circuit to the overall system performance.
Some of digital video broadcasting (DVB) standards
which are now spread throughout the world are operating
in different parts of the UHF band. Therefore, in order to
improve quality of service, RF unit components such as
synthesizers should obtain appropriate spectral purity in
desired bandwidth. The purpose of this paper is designing
the low phase noise wideband UHF frequency synthesizer
from 470 MHz to 860 MHz. The paper has been organized
as follows: In section 2, UHF frequency synthesizer is
designed. In this section, selecting resonator and oscillator
structure and VCO topology are explained in detail. Then
design and simulation of proposed VCO and proper loop
filter are demonstrated. Finally simulation of UHF
frequency synthesizer is presented . in section 3, some
conclusions are offered.

2 DESIGNING THE UHF FREQUENCY SYNTHESIZER

In this paper, we are going to design the low phase
noise UHF frequency synthesizer with the frequency
range of 470MHz to 860MHz. So as to design the low
noise wideband UHF frequency synthesizer, the
! " #

based fractional-N frequency synthesizer has been used
which contains a low noise digital phase frequency
detector (PFD),a precision charge pump ,a programmable
reference divider and also the programmable N-fractional
loop divider with the third-order
! " #
modulator.
Designing VCO with the wideband structure considering
the minimum output power variations along the band and
also a minimum phase noise, designing an appropriate
loop filter, choosing a suitable reference crystal with the
minimum phase noise with the highest stability have been
considered as important parts in designing of the
proposed synthesizer [1].
2.1 DESIGNING THE VOLTAGE CONTROLLED
OSCILLATOR
Each VCO contains three main parts. One of them is
the active circuit which its main element is the transistor
and it converts the dc power to the ac power by creating
the negative resistance. The second part is a load network
which receives the generated ac power and the third part
is a resonator network which allows transmitting the
generated power to the load only in its resonant
frequency. In accordance with the vital VCO features such
as the output power, phase noise characteristic and the
required frequency bandwidth, the structure of the
oscillator and its resonator circuit have been determined.
The optimum design of the VCO and decreasing its phase
noise level as one of the main sources of the PLL output
phase noise plays a significant role in declining the phase
noise level of synthesizer.
2.1.1 ACTIVE DEVICE AND VARACTOR DIODE
SELECTION

Fig. 1. Block diagram of PLL-based frequency synthesizers.

M. Majdi is with the Electrical Engineering Department of Islamic Azad
University Tehran south branch.
F. Hodjat Kashani is with Iran University of Science and Technology,
Narmak, Tehran, Iran.


JOURNAL OF TELECOMMUNICATIONS, VOLUME 22, ISSUE 1, OCTOBER 2013

15
BJT and HBT Transistors with lower Flickr noise are
used in applications such as oscillators, VCO and
multipliers in order to obtain the output spectrum with
the high purity. So, the chosen transistor in this part is a
low-noise BJT, NPN type which its f
T
is equal 45GHz and
hFE is approximately 140. If Ic is 20 mA, the 1-dB
compression point will be 12dBm. Furthermore, for
Ic=7mA, the mentioned amount is 5dBm. Varactor diode
is another semiconductor device of the circuit which
should be chosen based on the requirements. Abrupt
varactors possess the higher Q, so those VCOs, which use
this kind of diode, have better characteristic of the phase
noise and the lower bandwidth. But, in return, the
hyperabrupt varactor has the greater capacitance change
for a given voltage change as well as a linear frequency
versus voltage characteristic over a limited voltage range.
So it can cover a greater frequency bandwidth. Our
proposed UHF VCO covers wide frequency bandwidth
more than 10%, so varactor has been selected which
includes a high capacitance ratio and low series resistance.
Therefore, the SMV1800-079LF silicon hyperabrupt
varactor diode has been used. The control voltage of the
mentioned varactor diode has the potential to sweep
along 0 to 30 volt. If the voltage is 0 and 30, its capacitance
will be 15.78 pF and 0.84 pF respectively. In order to
covering the frequency band in the range of 470 to 860
MHZ, the control voltage has been declined to the range
of 1.35 to 4.68 voltage based on the arrangements of
varactor diodes in the resonator circuit. The curves
relevant to characteristic of the capacitor in terms of the
voltage for the mentioned varactor diode has been shown
in fig. 2.
2.1.2 BIAS POINT SELECTION
The DC bias point of oscillators is selected in the class A
like the power amplifiers. Voltage and current of the bias
should be enough to allow the necessary voltage and
current changes of the output RF to generate the vital
output power. It is usually attempted to consider collector
voltage and current small in the low noise oscillators
however by this way, output power would be reduced. In
the specific situations that output power is not a
significant and impressive parameter in designing, bias
point could be selected in the saturation zone of the
transistor which the transistor indicates the linear
behavior itself and the harmonics have a negligible effect
on the output power of the major harmonic. The bias point
and DC parameters of oscillator circuit are represented in
table 1.

2.1.3 STRUCTURE OF THE OSCILLATOR
The prerequisite to have a fluctuation in the output of
an oscillator is that the stability factor (K) of the network
which is used as an active device and the supplier of the
negative resistance related to the oscillator, should be less
than 1. So, if the stability factor of the applied transistor in
the oscillator is more than 1, it should be made unstable in
a possible manner. In this design due to cover a variety of
the frequency range at the UHF band nearly 58%,
modified colpitts structure is used. The colpitts is
modified by inductive resistance of limited Q of the
inductor, with the aim of its parallel negative resistance
observed on the transistor base. Fig. 3 presents the
modified colpitts oscillator with its bias circuit that its
active segment is a BJT transistor. The inductors and
capacitors values have been considered as follows: C
1
=3.3
pF, C2=3.9 pF, Lt=10 nH, [10].


In order to analysis of possibility and stability of the
oscillation related to the oscillator by using S parameters
of BFP520 transistor, stability factor (k) in the various
frequencies from 470MHz to 860MHz, is less than 1.
Achieved results of surveying the transistor stability in the
common emitter at the mentioned frequency limit, present
that K values are less than one in the whole frequency
ranges, so the transistor is unstable in the range. So, to
expand the unstable region, the capacitive feedback has
been used in the transistor emitter.





TABLE 1
BIAS CIRCUIT PARAMETERS OF THE
TRANSISTOR






Fig. 2. C-V characteristic of the SMV1800-079LF varactor
diode.
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16
2.1.4 STRUCTURE OF THE FREQUENCY RESONATOR
In designing the wide band, the most common
resonators are adjustable ones with hyperabrupt varactor
diode. C-V characteristic of this kind of diodes is
approximately non linear. So, by connecting the frequency
resonator to the transistors base, it could be made to
increase the bandwidth of VCO. Moreover, the small
current of the transistors base-when the resonator is
connected to it- will be more effective than other transistor
pins to decrease the phase noise of the VCO output. To
prevent the effect of bias voltage of the varactors on the
oscillator circuit, varactor diode and transistor should be
isolated on dc side respect to each other, for this purpose,
resonator and oscillator have to be coupled together with
a large dc coupled capacitor. If the varactor diode is
located on the resonator circuit serially, a further
bandwidth would be attained. Different states of the
varactor diode (Ctot) which could be existed with the
inductor (Lt) on the transistors base in fig. 3, are
presented in fig. 4.
Cp capacitor could be resulted to the non ideal inductor in
fig. 4,Series capacitor Cs has been used to complete the
circuit for alternating current but isolates the cathode of
the tuner diode from the coil and thus from the negative
terminal of the tuning voltage. For high-frequency
purposes the biasing resistor is connected in parallel with
the series capacitor. The parallel loss resistance
transformed into the circuit Rc, is calculated as in (1).
( )
2
2
2
1
!
!
"
#
$
$
%
&
' +
=
P S
S
B C
C C L
LC
R R
(
(

(1)

If two varactors are used in the resonator as shown in
fig. 4, Rc resistance will be independent of frequency
across the entire tuning range, as in (2).
B C
R R 4 = (2)
So, bias resistor does not have any influence on
bandwidth of the circuit. This arrangement has the
advantage that the capacitance shift caused by the ac
modulation acts in opposite directions in these diodes and
therefore, cancels itself.
So as to close the circuit for alternating current, series
capacitor Cs is used. Although the existence of Cs makes
increase the quality factor, it decreases the capacitance
ratio and range of varactor adjustment voltage, as in (3).

Thus, in designing the circuit, it is notable that the
amount of the series capacitor Cs should be chosen large
enough in order not to restrict the effective capacitance
variation. The parallel capacitance Cp is always present,
since wiring capacitances are inevitable and every coil has
its self-capacitances.as in (4),
!
!
!
!
"
!
!
!
!
#
$
+
+
=
%
%
&
'
(
(
)
*
%
%
&
'
(
(
)
*
+ =
+
%
%
&
'
(
(
)
*
+ =
min
max
min
max
min
max
1
1
1
1
C
C
C
C
C
C
C
C
C
C
Q Q
C
C
C C
P
P
eff
tot
P
eff
tot
P
tot eff

(4)

Fig. 3. The modified colpitts oscillator and biasing circuit.
!
!
!
!
!
!
"
!
!
!
!
!
!
#
$
+
=
+
+
=
%
%
&
'
(
(
)
*
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%
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(
)
*
+ =
+
+
=
S
tot
eff
S
S
eff
S
tot
eff
S
tot
tot eff
C
C
V V
C
C
C
C
C
C
C
C
C
C
Q Q
C
C
C C
1
1

1
1
1
1
1
max
min
min
max
min
max

(3)


Fig. 4. (a) parallel-resonant circuit with two varactor diode,
(b) parallel-resonant circuit with varactor diode, and bias resistor in
parallel to the diode.

Fig. 5. The final scheme of the UHF VCO.
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17
The Q of the effective tuning capacitance rises with the
magnitude of the parallel capacitance. In view of the fact
that even a comparatively small shunt capacitance reduces
the capacitance ratio considerably, it is necessary to ensure
low wiring and coil capacitance in the layout stage of the
circuit design. So high quality inductors ought to be used.
The frequency range can be tuned by means of the tuning
diode depends on the useful capacitance ratio of the diode
and on the parallel and series capacitances present in the
circuit, as in (5).
!
!
"
#
$
$
%
&
+
+
!
!
"
#
$
$
%
&
+
+
=
S
P
S
P
C
C
C
C
C
C
C
C
C
C
f
f
max
min
max
max
max
max
min
max
1
1
1


(5)

Now, if Cs is large enough, (5) could be written as (6).
P
P
C
C
C
C
f
f
min
max
min
max
1
1
+
+
=

(6)
As presented in the (6), while Cs value is large enough,
frequency range will be dependent on Cp. Thus, the larger
series capacitor Cs and smaller parallel parasitic capacitor
Cp would make less restriction on bandwidth. According
to different techniques and their features as mentioned
above, the proposed resonator circuit has been designed
by using several tuning diodes in parallel arrangement.
Improved phase-noise and bandwidth performance can be
obtained by using this structure.
2.1.5 DESIGN AND SIMULATION OF VCO
The design of proposed VCO has been represented in
fig. 5. In this design, the mentioned frequency resonator is
used. After simulating by ADS software it implies that
arrangements of the varactor diodes, improve capacitance
ratio which is required to cover the desired bandwidth. In
addition, it causes to decline the total resistance of diodes
and decrease diodes noise contribution. Indeed, by
keeping the capacitance ratio, we can decrease the
required control voltage. In addition, by connecting the
resonator circuit to the base of the transistor, we achieved
an appropriate structure for VCO to reach a better output
phase noise characteristic [11],[12].

As illustrated in fig. 5, by using parallel inductor as a high
pass filter in the VCO output the variation of the output
power decrease from 1.78dB to 0.93dB at the frequency
range of 470 to 860 MHz as shown in fig. 6.
The Results of the output parallel inductor value
optimization is introduced in table 2. P
1
, p
2
and p
3
are the
output power at the first, middle and the end of UHF
band, respectively.
Other designed VCO parameters have been shown in

Fig. 6. (a) VCO output power before variation optimization. (b) VCO output power
after variation optimization.
TABLE 2
RESULTS OF THE OUTPUT PARALLEL INDUCTOR VALUE
OPTIMIZATION



Fig. 9. SSB phase noise power spectrum of VCO output.
TABLE 3
CHARACTERISTICS AND PERFORMANCE SUMMARY
OF PROPOSED VCO


JOURNAL OF TELECOMMUNICATIONS, VOLUME 22, ISSUE 1, OCTOBER 2013

18
table 3.

Also, VCO output frequency variations in terms of
varactor diode control voltage variations, VCO output
voltage waveforms in terms of the time and its spectrum
and SSB phase noise power spectrum of VCO output in
frequency terms are shown in fig. 7, fig. 8, and fig. 9.


2.2 LOOP FILTER DESIGN
In this design, to prevent increasing phase noise, the
second order passive filter as shown in fig. 10, is proposed
[1].



The bandwidth of 38 KHz and 45 phase margin is
resulted in simulation of optimized loop filter. The
amplitude and phase of the open and closed loop gain for
this filter have been shown in fig. 11, and fig. 12.



2.3 DESIGN AND SIMULATION OF SYNTHESIZER
The N-fractional frequency synthesizer chip that is used in
this design consists of a digital phase-frequency detector,
charging pump, programmable reference frequency
divider and the N-fractional main divider of the loop with
third order !-! modulator which is programmable. Fig. 13
shows lock time of the loop in 636MHz and fig. 14 shows
output phase error of the loop.

Fig. 10. Second Order Passive Low-Pass Filter.

Fig. 8. VCO output voltage waveforms in terms of the time
and its spectrum.

Fig. 7. VCO output frequency variations in terms of varactor
diode control voltage variations.

Fig. 11. Amplitude and phase of open loop system gain.

Fig. 12. Amplitude and phase of closed loop system gain.

Fig. 15. Phase Noise Of The Synthesizer.
TABLE 4
CHARACTERISTICS AND PERFORMANCE SUMMARY OF
FREQUENCY SYNTHESIZER

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19

Fig. 15 shows the phase noise of the designed synthesizer
and table 4 illustrated characteristics and performance
summary of this synthesizer.

3 CONCLUSION
In this paper, design and simulation of the wideband and
low phase noise UHF frequency synthesizer have been
presented. A wideband VCO, as a key circuit in the PLL,
with respect to the low phase noise is designed by using
modified colpitts structure and a number of tuning diodes
in different arrangement as the parallel resonator. The
simulation results show -119.833 dBc/Hz phase noise at
100 KHz offset frequency and the tuning range is as wide
as 58% from 470MHz to 860MHz. The output power
variation of the VCO is optimized to 0.93dB. Finally, a PLL
is designed using a proper crystal and loop filter with the
bandwidth of 38 KHz. The desirable bandwidth (470MHz
to 860MHz) is achieved for the synthesizer while the SSB
phase noise is less than -105dBc/Hz at 10 KHz offset
frequency in the output of the PLL.


REFERENCES
[1] ulrlch L. 8ohde, Mlcrowave and Wlreless SynLheslzers: 1heory and
ueslgn, by !ohn Wlley & Sons, new ?ork, n?,lS8n: 0471-32019-3 ,
AugusL, 1997 .
[2] !. Po[ung, k. !ongsun, A Low-ower Wldeband mulLl-frequency
synLheslzer for moblle 1v Luner lCs," lLlCL LlecLronlcs Lxpress, vol. 7,
no. 2, 92-97, !anuary, 2010.
[3] !. Puang, Z. Wang, k. Ll, Z. Ll, ?. Wang, A Wlde-band low phase nolse
LC-Luned vCC wlLh consLanL kvCC/uosc for L1L LL," !ournal of
SemlconducLors, vol. 33, no. 2, lebruary, 2012.
[4] x. Shual, P. Wel, S. Chunql, Z. 8unxl, M. Cong, L. Zongsheng, ueslgn
of a wldeband and low phase nolse LC vCC", Solld-SLaLe and
lnLegraLed ClrculL 1echnology (lCSlC1), 10Lh lLLL lnLernaLlonal
Conference, publlshed 2010.
[3] !. . MaLhurln, !. Mercler, Wlde 8and frequency synLhesls", 8adar
Conference-Survelllance for a Safer World, 2009. (lLLL Conferences)
[6] ?. eng, C. Zheng, C. Mlng, S. ?ln, l.l. ual, A 430MPz-2.13CPz
fracLlonal-n frequency synLheslzer for uv8 and A8S-S appllcaLlons,"
CusLom lnLegraLed ClrculLs Conference, 2009. ClCC '09. lLLL. (lLLL
Conferences)
[7] S. Saeedl, M. ALarodl, Slngle-vCC mulLl-band u1v frequency
SynLheslzer wlLh a dlvlde-by-3 frequency dlvlder for quadraLure slgnal
generaLlon," LlecLrlcal Lnglneerlng ueparLmenL, Sharlf unlverslLy,
2009.
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lracLlonal-n lrequency SynLheslzer wlLh Llnearlzed Coarse-1uned
vCC for uPl/vPl Moblle 8roadcasLlng 1uners," korea lLLL Aslan
Solld-SLaLe ClrculLs Conference, 2007.
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SynLheslzer," lLLL 1ransacLlons on 8roadcasLlng, vol. 34, no. 1, March
2008.
[10] u. L. 8ohde, A. k. oddar, An AnalyLlcal Approach of Mlnlmlzlng vCC
hase nolse," Synergy Mlcrowave CorporaLlon, lLLL, AMC2003.

[11] ulrlch L. 8ohde, kA2WLu, All AbouL hase nolse ln CsclllaLors, arL
lll - Lxample osclllaLor clrculLs and Lhelr nolse performance," CLx,
lebruary 1994.
[12] ulrlch L. 8ohde, kA2WLu, ueslgnlng Low-hase-nolse CsclllaLors,"
CLx, CcLober 1994.


M. Majdi received her B.S. and M.S. degrees both in electrical
engineering from Islamic Azad University Tehran south branch, in
2005 and 2010, respectively. She is with the Civil Aviation
Technology College since 2007. Her research interests include
frequency synthesizers and active microwave circuit design.

F. Hodjat Kashani received his B.S. degree in Electrical Engineering
from University of Tehran, M.S. degree in Electrical Engineering from
UCLA and Ph.D. degree in Electrical Engineering from University of
California Los Angeles, in 1962, 1968 and 1970, respectively. he is
Full Prof. of Electrical Engineering of Iran University of Science and
Technology. His Expertise is about Antenna Design, Microwave and
Millimeter Wave Community, Meta-materials and EBG structures. He
has more than twenty Research and Industrial Projects as Design
and Implementation of a Conical Wraparound Antenna.

Fig.13. Lock Time of Output Frequency (at 636MHz).
0 100 200 300 400 500 600 700 800 900 1000
Time (us)
-50
-40
-30
-20
-10
0
10
20
30
40
50
P
h
a
s
e

E
r
r
o
r

(
d
e
g
)
Output Phase Error

Fig.14. Loop Output Phase Error.