Peripheral Features:
PIC12C508 PIC12C508A
PIC12C509 PIC12C509A
PIC12CR509A
PIC12CE518
PIC12CE519
PIC12C508
512 x 12
25
PIC12C508A
512 x 12
25
CMOS Technology:
PIC12C509
1024 x 12
41
PIC12C509A
1024 x 12
41
PIC12CE518
512 x 12
25
16
PIC12CE519
1024 x 12
41
16
PIC12CR509A
EPROM
Program
ROM
Program
1024 x 12
RAM
Data
EEPROM
Data
41
DS40139E-page 1
PIC12C5XX
Pin Diagram - PIC12C508/509
PDIP, 208 mil SOIC, Windowed Ceramic Side Brazed
1
2
GP4/OSC2
GP3/MCLR/VPP
PIC12C508
PIC12C509
VDD
GP5/OSC1/CLKIN
VSS
GP0
GP1
GP2/T0CKI
GP4/OSC2
GP3/MCLR/VPP
3
4
PIC12C508A
PIC12C509A
PIC12CE518
PIC12CE519
VDD
GP5/OSC1/CLKIN
VSS
GP0
GP1
GP2/T0CKI
VSS
GP0
GP1
GP2/T0CKI
GP4/OSC2
GP3/MCLR/VPP
3
4
PIC12CR509A
VDD
GP5/OSC1/CLKIN
Device Differences
Device
Voltage
Range
Oscillator
Oscillator
Calibration2
(Bits)
Process
Technology
(Microns)
PIC12C508A
3.0-5.5
See Note 1
0.7
PIC12LC508A
2.5-5.5
See Note 1
0.7
PIC12C508
2.5-5.5
See Note 1
0.9
PIC12C509A
3.0-5.5
See Note 1
0.7
PIC12LC509A
2.5-5.5
See Note 1
0.7
PIC12C509
2.5-5.5
See Note 1
0.9
PIC12CR509A
2.5-5.5
See Note 1
0.7
PIC12CE518
3.0-5.5
0.7
PIC12LCE518
2.5-5.5
0.7
PIC12CE519
3.0-5.5
0.7
PIC12LCE519
2.5-5.5
0.7
Note 1: If you change from the PIC12C50X to the PIC12C50XA or to the PIC12CR50XA, please verify
oscillator characteristics in your application.
Note 2: See Section 7.2.5 for OSCCAL implementation differences.
DS40139E-page 2
PIC12C5XX
TABLE OF CONTENTS
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
11.0
12.0
13.0
General Description............................................................................................................................................... 4
PIC12C5XX Device Varieties ................................................................................................................................ 7
Architectural Overview........................................................................................................................................... 9
Memory Organization .......................................................................................................................................... 13
I/O Port ................................................................................................................................................................ 21
Timer0 Module and TMR0 Register .................................................................................................................... 25
EEPROM Peripheral Operation........................................................................................................................... 29
Special Features of the CPU ............................................................................................................................... 35
Instruction Set Summary ..................................................................................................................................... 47
Development Support.......................................................................................................................................... 59
Electrical Characteristics - PIC12C508/PIC12C509............................................................................................ 65
DC and AC Characteristics - PIC12C508/PIC12C509 ........................................................................................ 75
Electrical Characteristics PIC12C508A/PIC12C509A/PIC12LC508A/PIC12LC509A/PIC12CR509A/
PIC12CE518/PIC12CE519/
PIC12LCE518/PIC12LCE519/PIC12LCR509A ................................................................................................... 79
14.0 DC and AC Characteristics
PIC12C508A/PIC12C509A/PIC12LC508A/PIC12LC509A/PIC12CE518/PIC12CE519/PIC12CR509A/
PIC12LCE518/PIC12LCE519/ PIC12LCR509A .................................................................................................. 93
15.0 Packaging Information......................................................................................................................................... 99
Index ........................................................................................................................................................................... 105
PIC12C5XX Product Identification System ................................................................................................................ 109
Sales and Support: ..................................................................................................................................................... 109
DS40139E-page 3
PIC12C5XX
1.0
GENERAL DESCRIPTION
The PIC12C5XX from Microchip Technology is a family of low-cost, high performance, 8-bit, fully static,
EEPROM/EPROM/ROM-based CMOS microcontrollers. It employs a RISC architecture with only 33 single word/single cycle instructions. All instructions are
single cycle (1 s) except for program branches
which take two cycles. The PIC12C5XX delivers performance an order of magnitude higher than its competitors in the same price category. The 12-bit wide
instructions are highly symmetrical resulting in 2:1
code compression over other 8-bit microcontrollers in
its class. The easy to use and easy to remember
instruction set reduces development time significantly.
The PIC12C5XX products are equipped with special
features that reduce system cost and power requirements. The Power-On Reset (POR) and Device Reset
Timer (DRT) eliminate the need for external reset circuitry. There are four oscillator configurations to choose
from, including INTRC internal oscillator mode and the
power-saving LP (Low Power) oscillator mode. Power
saving SLEEP mode, Watchdog Timer and code
protection features also improve system cost, power
and reliability.
1.1
Applications
DS40139E-page 4
PIC12C5XX
TABLE 1-1:
10
10
10
10
EPROM
Program
Memory
512 x 12
1024 x 12
1024 x 12
(ROM)
512 x 12
1024 x 12
1024 x 14
2048 x 14
1024 x 14
2048 x 14
RAM Data
Memory
(bytes)
25
41
41
25
41
128
128
128
128
16
16
16
16
Timer
Module(s)
TMR0
TMR0
TMR0
TMR0
TMR0
TMR0
TMR0
TMR0
TMR0
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Interrupt
Sources
I/O Pins
Input Pins
Internal
Pull-ups
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
In-Circuit
Serial
Programming
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Number of
Instructions
33
33
33
33
33
35
35
35
35
Packages
Features
Wake-up
from SLEEP
on pin
change
Peripherals
Memory
EEPROM
Data Memory
(bytes)
Clock
Maximum
Frequency
of Operation
(MHz)
8-pin DIP,
JW, SOIC
8-pin DIP,
JW, SOIC
8-pin DIP,
SOIC
8-pin DIP,
JW, SOIC
8-pin DIP,
JW, SOIC
8-pin DIP,
JW, SOIC
8-pin DIP,
JW, SOIC
8-pin DIP,
JW
8-pin DIP,
JW
All PIC12CXXX & PIC12CEXXX devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O
current capability.
All PIC12CXXX & PIC12CEXXX devices use serial programming with data pin GP0 and clock pin GP1.
DS40139E-page 5
PIC12C5XX
NOTES:
DS40139E-page 6
PIC12C5XX
2.0
2.1
UV Erasable Devices
Microchips PICSTART PLUS and PRO MATE programmers all support programming of the PIC12C5XX.
Third party programmers also are available; refer to the
Microchip Third Party Guide for a list of sources.
2.2
One-Time-Programmable (OTP)
Devices
2.3
Quick-Turnaround-Production (QTP)
Devices
2.4
Serialized Quick-Turnaround
Production (SQTPSM) Devices
2.5
DS40139E-page 7
PIC12C5XX
NOTES:
DS40139E-page 8
PIC12C5XX
3.0
ARCHITECTURAL OVERVIEW
EPROM
Program
ROM
Program
Memory
Device
RAM
Data
PIC12C508
512 x 12
25
PIC12C509
1024 x 12
EEPROM
Data
41
PIC12C508A
512 x 12
25
PIC12C509A
1024 x 12
41
PIC12CR509A
1024 x 12
41
PIC12CE518
512 x 12
25 x 8
16 x 8
PIC12CE519
1024 x 12
41 x 8
16 x 8
DS40139E-page 9
PIC12C5XX
PIC12C5XX BLOCK DIAGRAM
12
GP0
GP1
GP2/T0CKI
GP3/MCLR/VPP
GP4/OSC2
GP5/OSC1/CLKIN
RAM
25 x 8 or
41 x 8
File
Registers
STACK1
STACK2
12
RAM Addr
Addr MUX
Instruction reg
Direct Addr
5-7
Indirect
Addr
FSR reg
STATUS reg
8
3
OSC1/CLKIN
OSC2
Timing
Generation
Internal RC
OSC
Power-on
Reset
Watchdog
Timer
16 X 8
EEPROM
Data
Memory
PIC12CE5XX
Only
MUX
Device Reset
Timer
Instruction
Decode &
Control
GPIO
SDA
Program
Bus
Data Bus
Program Counter
ROM/EPROM
512 x 12 or
1024 x 12
Program
Memory
SCL
FIGURE 3-1:
ALU
8
W reg
Timer0
MCLR
VDD, VSS
DS40139E-page 10
PIC12C5XX
TABLE 3-1:
SOIC
Pin #
I/O/P
Type
GP0
I/O
GP1
I/O
Name
Buffer
Type
ST
Description
GP2/T0CKI
I/O
GP3/MCLR/VPP
GP4/OSC2
I/O
GP5/OSC1/CLKIN
I/O
VDD
VSS
TTL/ST Input port/master clear (reset) input/programming voltage input. When configured as MCLR, this pin is an
active low reset to the device. Voltage on MCLR/VPP
must not exceed VDD during normal device operation
or the device will enter programming mode. Can be
software programmed for internal weak pull-up and
wake-up from SLEEP on pin change. Weak pull-up
always on if configured as MCLR. ST when in MCLR
mode.
TTL
Bi-directional I/O port/oscillator crystal output. Connections to crystal or resonator in crystal oscillator
mode (XT and LP modes only, GPIO in other modes).
Legend: I = input, O = output, I/O = input/output, P = power, = not used, TTL = TTL input,
ST = Schmitt Trigger input
DS40139E-page 11
PIC12C5XX
3.1
3.2
Instruction Flow/Pipelining
FIGURE 3-2:
CLOCK/INSTRUCTION CYCLE
Q1
Q2
Q3
Q4
Q2
Q1
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
Q1
Q2
Internal
phase
clock
Q3
Q4
PC
PC
PC+1
EXAMPLE 3-1:
PC+2
1. MOVLW 03H
2. MOVWF GPIO
3. CALL
SUB_1
4. BSF
GPIO, BIT1
Fetch 1
Execute 1
Fetch 2
Execute 2
Fetch 3
Execute 3
Fetch 4
Flush
Fetch SUB_1 Execute SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetch
instruction is flushed from the pipeline while the new instruction is being fetched and then executed.
DS40139E-page 12
PIC12C5XX
MEMORY ORGANIZATION
PIC12C5XX memory is organized into program memory and data memory. For devices with more than 512
bytes of program memory, a paging scheme is used.
Program memory pages are accessed using one STATUS register bit. For the PIC12C509, PIC12C509A,
PICCR509A and PIC12CE519 with a data memory
register file of more than 32 registers, a banking
scheme is used. Data memory banks are accessed
using the File Select Register (FSR).
4.1
FIGURE 4-1:
CALL, RETLW
Stack Level 1
Stack Level 2
0000h
On-chip Program
Memory
User Memory
Space
4.0
512 Word
01FFh
0200h
On-chip Program
Memory
1024 Word
03FFh
0400h
7FFh
DS40139E-page 13
PIC12C5XX
4.2
FIGURE 4-2:
File Address
00h
INDF (1)
01h
TMR0
02h
PCL
03h
STATUS
04h
FSR
05h
OSCCAL
06h
GPIO
07h
General
Purpose
Registers
1Fh
Note
1:
FIGURE 4-3:
00
01
File Address
00h
INDF(1)
01h
TMR0
02h
PCL
03h
STATUS
20h
04h
FSR
05h
OSCCAL
06h
Addresses map
back to
addresses
in Bank 0.
GPIO
07h
General
Purpose
Registers
2Fh
0Fh
30h
10h
General
Purpose
Registers
3Fh
1Fh
Bank 0
Note 1:
DS40139E-page 14
General
Purpose
Registers
Bank 1
PIC12C5XX
4.2.2
TABLE 4-1:
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-On
Reset
Value on
All Other
Resets(2)
--11 1111
--11 1111
OPTION
1111 1111
1111 1111
00h
INDF
xxxx xxxx
uuuu uuuu
01h
TMR0
xxxx xxxx
uuuu uuuu
02h(1)
PCL
1111 1111
1111 1111
03h
STATUS
0001 1xxx
q00q quuu(3)
04h
FSR
(PIC12C508/
PIC12C508A/
PIC12C518)
111x xxxx
111u uuuu
04h
FSR
(PIC12C509/
PIC12C509A/
PIC12CR509A/
PIC12CE519) Indirect data memory address pointer
110x xxxx
11uu uuuu
05h
OSCCAL
(PIC12C508/
PIC12C509)
CAL3
CAL2
CAL1
CAL0
0111 ----
uuuu ----
05h
OSCCAL
(PIC12C508A/
PIC12C509A/
PIC12CE518/
PIC12CE519/
PIC12CR509A)
CAL5
CAL4
CAL3
CAL2
CAL1
CAL0
1000 00--
uuuu uu--
06h
GPIO
(PIC12C508/
PIC12C509/
PIC12C508A/
PIC12C509A/
PIC12CR509A)
GP5
GP4
GP3
GP2
GP1
GP0
--xx xxxx
--uu uuuu
06h
GPIO
(PIC12CE518/
PIC12CE519)
SCL
SDA
GP5
GP4
GP3
GP2
GP1
GP0
11xx xxxx
11uu uuuu
N/A
N/A
TRIS
GPWUF
PA0
TO
PD
DC
DS40139E-page 15
PIC12C5XX
4.3
STATUS Register
FIGURE 4-4:
R/W-0
GPWUF
bit7
R/W-0
R/W-0
PA0
R-1
TO
R-1
PD
R/W-x
Z
R/W-x
DC
R/W-x
C
bit0
R = Readable bit
W = Writable bit
- n = Value at POR reset
bit 7:
bit 6:
Unimplemented
bit 5:
bit 4:
bit 3:
bit 2:
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1:
bit 0:
DS40139E-page 16
RRF or RLF
Load bit with LSB or MSB, respectively
PIC12C5XX
4.4
OPTION Register
Note:
Note:
FIGURE 4-5:
OPTION REGISTER
W-1
W-1
W-1
W-1
W-1
W-1
W-1
W-1
GPWU
GPPU
T0CS
T0SE
PSA
PS2
PS1
PS0
bit7
bit 7:
bit 5:
bit 4:
bit 3:
bit 2-0:
W = Writable bit
U = Unimplemented bit
- n = Value at POR reset
Reference Table 4-1 for
other resets.
bit 6:
bit0
Timer0 Rate
WDT Rate
000
001
010
011
100
101
110
111
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1:1
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
DS40139E-page 17
PIC12C5XX
4.5
OSCCAL Register
FIGURE 4-6:
R/W-0
R/W-1
R/W-1
R/W-1
R/W-0
R/W-0
U-0
U-0
CAL3
CAL2
CAL1
CAL0
bit7
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as 0
- n = Value at POR reset
FIGURE 4-7:
R/W-1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
U-0
CAL5
CAL4
CAL3
CAL2
CAL1
CAL0
bit7
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as 0
- n = Value at POR reset
DS40139E-page 18
PIC12C5XX
4.6
Program Counter
4.6.1
EFFECTS OF RESET
FIGURE 4-8:
LOADING OF PC
BRANCH INSTRUCTIONS PIC12C5XX
GOTO Instruction
11 10
PC
Instruction Word
0
STATUS
Stack
PA0
11 10
4.7
PCL
PC
PCL
Instruction Word
Reset to 0
PA0
7
STATUS
DS40139E-page 19
PIC12C5XX
4.8
EXAMPLE 4-2:
EXAMPLE 4-1:
INDIRECT ADDRESSING
0x10
FSR
INDF
FSR,F
FSR,4
NEXT
;initialize pointer
; to RAM
;clear INDF register
;inc pointer
;all done?
;NO, clear next
CONTINUE
;YES, continue
FIGURE 4-9:
NEXT
movlw
movwf
clrf
incf
btfsc
goto
PIC12C508/PIC12C508A/PIC12CE518:
Does not
use banking. FSR<7:5> are unimplemented and read
as '1's.
PIC12C509/PIC12C509A/PIC12CR509A/
PIC12CE519: Uses FSR<5>. Selects between bank 0
and bank 1. FSR<7:6> is unimplemented, read as '1 .
DIRECT/INDIRECT ADDRESSING
Direct Addressing
(FSR)
6 5
bank select
Indirect Addressing
location select
(opcode)
bank
00
(FSR)
location select
01
00h
Addresses
map back to
addresses
in Bank 0.
Data
Memory(1)
0Fh
10h
1Fh
Bank 0
3Fh
Bank 1(2)
DS40139E-page 20
PIC12C5XX
5.0
I/O PORT
5.1
GPIO
5.2
TRIS Register
5.3
I/O Interfacing
FIGURE 5-1:
EQUIVALENT CIRCUIT
FOR A SINGLE I/O PIN
Data
Bus
D
WR
Port
W
Reg
Q
Data
Latch
CK
VDD
Q
N
D
Q
TRIS
Latch
TRIS f
CK
Reset
I/O
pin(1,3)
VSS
Q
(2)
RD Port
DS40139E-page 21
PIC12C5XX
TABLE 5-1:
Address
N/A
N/A
Name
TRIS
OPTION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-On
Reset
Value on
All Other Resets
--11 1111
--11 1111
GPWU
GPPU
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
1111 1111
GPWUF
PAO
TO
PD
DC
0001 1xxx
q00q quuu(1)
03H
STATUS
06h
GPIO
(PIC12C508/
PIC12C509/
PIC12C508A/
PIC12C509A/
PIC12CR509A)
GP5
GP4
GP3
GP2
GP1
GP0
--xx xxxx
--uu uuuu
06h
GPIO
(PIC12CE518/
PIC12CE519)
SCL
SDA
GP5
GP4
GP3
GP2
GP1
GP0
11xx xxxx
11uu uuuu
Legend: Shaded cells not used by Port Registers, read as 0, = unimplemented, read as '0', x = unknown, u = unchanged,
q = see tables in Section 8.7 for possible values.
Note 1: If reset was due to wake-up on change, then bit 7 = 1. All other resets will cause bit 7 = 0.
5.4
5.4.1
DS40139E-page 22
EXAMPLE 5-1:
READ-MODIFY-WRITE
INSTRUCTIONS ON AN
I/O PORT
5.4.2
PIC12C5XX
FIGURE 5-2:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
Instruction
fetched
MOVWF GPIO
PC + 1
MOVF GPIO,W
Q1 Q2 Q3 Q4
PC + 2
PC + 3
NOP
NOP
GP5:GP0
MOVWF GPIO
(Write to
GPIO)
Port pin
sampled here
MOVF GPIO,W
(Read
GPIO)
DS40139E-page 23
PIC12C5XX
NOTES:
DS40139E-page 24
PIC12C5XX
6.0
FIGURE 6-1:
GP2/T0CKI
Pin
FOSC/4
PSout
1
1
Programmable
Prescaler(2)
T0SE
8
Sync with
Internal
Clocks
TMR0 reg
PSout
(2 TCY delay) Sync
3
T0CS(1)
PSA(1)
Note 1: Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in the OPTION register.
2: The prescaler is shared with the Watchdog Timer (Figure 6-5).
DS40139E-page 25
PIC12C5XX
FIGURE 6-2:
PC
(Program
Counter)
PC-1
Instruction
Fetch
PC
PC+1
PC+3
T0+1
T0
Timer0
T0+2
Instruction
Executed
PC+4
PC+5
MOVF TMR0,W
NT0
Write TMR0
executed
FIGURE 6-3:
Read TMR0
reads NT0
NT0+1
Read TMR0
reads NT0
PC+6
MOVF TMR0,W
NT0+2
Read TMR0
reads NT0 + 1
Read TMR0
reads NT0
Read TMR0
reads NT0 + 2
PC
(Program
Counter)
PC-1
PC
PC+1
MOVWF TMR0
Instruction
Fetch
MOVF TMR0,W
PC+3
PC+4
PC+5
MOVF TMR0,W
Write TMR0
executed
Read TMR0
reads NT0
Read TMR0
reads NT0
PC+6
MOVF TMR0,W
NT0+1
NT0
Instruction
Execute
TABLE 6-1:
PC+2
T0+1
T0
Timer0
Address
PC+2
MOVWF TMR0
Read TMR0
reads NT0
Read TMR0
reads NT0
T0
Read TMR0
reads NT0 + 1
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-On
Reset
Value on
All Other
Resets
01h
TMR0
xxxx xxxx
uuuu uuuu
N/A
OPTION
GPWU
GPPU
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
1111 1111
N/A
TRIS
GP5
GP4
GP3
GP2
GP1
GP0
DS40139E-page 26
PIC12C5XX
6.1
6.1.2
FIGURE 6-4:
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
Small pulse
misses sampling
(1)
External Clock/Prescaler
Output After Sampling
(3)
T0
T0 + 1
T0 + 2
Note 1: Delay from clock input change to Timer0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc).
Therefore, the error in measuring the interval between two edges on Timer0 input = 4Tosc max.
2: External clock if no prescaler selected, Prescaler output otherwise.
3: The arrows indicate the points in time where sampling occurs.
DS40139E-page 27
PIC12C5XX
6.2
Prescaler
EXAMPLE 6-1:
1.CLRWDT
2.CLRF
TMR0
3.MOVLW '00xx1111b
4.OPTION
;Clear WDT
;Clear TMR0 & Prescaler
;These 3 lines (5, 6, 7)
; are required only if
; desired
5.CLRWDT
;PS<2:0> are 000 or 001
6.MOVLW '00xx1xxxb ;Set Postscaler to
7.OPTION
; desired WDT rate
EXAMPLE 6-2:
CHANGING PRESCALER
(WDTTIMER0)
CLRWDT
MOVLW
'xxxx0xxx'
OPTION
FIGURE 6-5:
CHANGING PRESCALER
(TIMER0WDT)
TCY ( = Fosc/4)
Data Bus
0
GP2/T0CKI
Pin
M
U
X
1
M
U
X
0
T0SE
T0CS
Watchdog
Timer
M
U
X
Sync
2
Cycles
TMR0 reg
PSA
8-bit Prescaler
8
8 - to - 1MUX
PS2:PS0
PSA
WDT Enable bit
0
MUX
PSA
WDT
Time-Out
Note: T0CS, T0SE, PSA, PS2:PS0 are bits in the OPTION register.
DS40139E-page 28
PIC12C5XX
7.0
EEPROM PERIPHERAL
OPERATION
to
PIC12CE518
and
SERIAL DATA
DS40139E-page 29
PIC12C5XX
Figure 7-1: Block diagram of GPIO6 (SDA line)
VDD
reset
To 24L00 SDA
Pad
D
databus
write
GPIO
ck
EN
Output Latch
Schmitt Trigger
EN
ck
Input Latch
ltchpin
Read
GPIO
VDD
To 24LC00 SCL
Pad
databus
write
GPIO
ck
EN
Schmitt Trigger
EN
ck
Read
GPIO
DS40139E-page 30
ltchpin
PIC12C5XX
7.0.2
SERIAL CLOCK
7.1
BUS CHARACTERISTICS
7.1.4
ACKNOWLEDGE
DS40139E-page 31
PIC12C5XX
FIGURE 7-3:
(A)
(B)
(C)
START
CONDITION
SCL
(D)
ADDRESS OR
ACKNOWLEDGE
VALID
(C)
(A)
SDA
FIGURE 7-4:
STOP
CONDITION
DATA
ALLOWED
TO CHANGE
ACKNOWLEDGE TIMING
Acknowledge
Bit
SCL
SDA
Device Addressing
DS40139E-page 32
7.2
FIGURE 7-5:
Device Select
Bits
X R/W ACK
Slave Address
Start Bit
Acknowledge Bit
PIC12C5XX
7.3
WRITE OPERATIONS
7.4
7.3.1
BYTE WRITE
ACKNOWLEDGE POLLING
FIGURE 7-6:
ACKNOWLEDGE POLLING
FLOW
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Byte write operations must be preceded and immediately followed by a bus not busy bus cycle where both
SDA and SCL are held high.
Did Device
Acknowledge
(ACK = 0)?
NO
YES
Next
Operation
FIGURE 7-7:
BYTE WRITE
BUS ACTIVITY
MASTER
S
T
A
R
T
SDA LINE
CONTROL
BYTE
BUS ACTIVITY
WORD
ADDRESS
0
A
C
K
S
T
O
P
DATA
X
A
C
K
A
C
K
DS40139E-page 33
PIC12C5XX
7.5
READ OPERATIONS
7.5.3
Sequential reads are initiated in the same way as a random read except that after the device transmits the first
data byte, the master issues an acknowledge as
opposed to a stop condition in a random read. This
directs the device to transmit the next sequentially
addressed 8-bit word (Figure 7-10).
RANDOM READ
FIGURE 7-8:
SEQUENTIAL READ
S
T
A
R
T
SDA LINE
S 1 0 1 0 X XX 1
S
T
O
P
CONTROL
BYTE
P
A
C
K
BUS ACTIVITY
N
O
A
C
K
DATA
FIGURE 7-9:
RANDOM READ
BUS ACTIVITY
MASTER
S
T
A
R
T
CONTROL
BYTE
X X X X
S 1 0 1 0 X X X 0
SDA LINE
S
T
O
P
CONTROL
BYTE
S 1 0 1 0 X X X 1
A
C
K
A
C
K
BUS ACTIVITY
S
T
A
R
T
WORD
ADDRESS (n)
A
C
K
DATA (n)
N
O
A
C
K
CONTROL
BYTE
DATA n
DATA n + 1
DATA n + 2
S
T
O
P
DATA n + X
SDA LINE
BUS ACTIVITY
DS40139E-page 34
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
PIC12C5XX
8.0
Oscillator selection
Reset
- Power-On Reset (POR)
- Device Reset Timer (DRT)
- Wake-up from SLEEP on pin change
Watchdog Timer (WDT)
SLEEP
Code protection
ID locations
In-circuit Serial Programming
FIGURE 8-1:
8.1
Configuration Bits
MCLRE
CP
bit11
10
bit0
Register:
Address(1):
CONFIG
FFFh
bit 3:
bit 2:
bit 1-0:
Note 1: Refer to the PIC12C5XX Programming Specifications to determine how to access the
configuration word. This register is not user addressable during device operation.
DS40139E-page 35
PIC12C5XX
8.2
Oscillator Configurations
8.2.1
TABLE 8-1:
OSCILLATOR TYPES
LP:
XT:
INTRC:
EXTRC:
8.2.2
Osc
Type
C1(1)
OSC1
Cap. Range
C1
Cap. Range
C2
XT
4.0 MHz
30 pF
30 pF
These values are for design guidance only. Since
each resonator has its own characteristics, the user
should consult the resonator manufacturer for
appropriate values of external components.
FIGURE 8-2:
Resonator
Freq
TABLE 8-2:
CAPACITOR SELECTION
FOR CERAMIC RESONATORS
- PIC12C5XX
Osc
Type
CAPACITOR SELECTION
FOR CRYSTAL OSCILLATOR PIC12C5XX
Resonator
Freq
Cap.Range
C1
Cap. Range
C2
32 kHz(1)
15 pF
15 pF
200 kHz
47-68 pF
47-68 pF
1 MHz
15 pF
15 pF
4 MHz
15 pF
15 pF
Note 1: For VDD > 4.5V, C1 = C2 30 pF is
recommended.
These values are for design guidance only. Rs may
be required to avoid overdriving crystals with low
drive level specification. Since each crystal has its
own characteristics, the user should consult the crystal manufacturer for appropriate values of external
components.
LP
XT
PIC12C5XX
SLEEP
XTAL
(2)
RF(3)
OSC2
To internal
logic
RS
C2(1)
FIGURE 8-3:
Clock from
ext. system
Open
DS40139E-page 36
OSC2
PIC12C5XX
8.2.3
FIGURE 8-4:
EXTERNAL PARALLEL
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
+5V
To Other
Devices
10k
74AS04
4.7k
74AS04
PIC12C5XX
CLKIN
10k
XTAL
10k
20 pF
20 pF
FIGURE 8-5:
EXTERNAL SERIES
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
330
To Other
Devices
PIC12C5XX
330
74AS04
74AS04
74AS04
8.2.4
EXTERNAL RC OSCILLATOR
FIGURE 8-6:
EXTERNAL RC OSCILLATOR
MODE
VDD
Rext
OSC1
Cext
Internal
clock
N
PIC12C5XX
VSS
CLKIN
0.1 F
XTAL
DS40139E-page 37
PIC12C5XX
8.2.5
The internal RC oscillator provides a fixed 4 MHz (nominal) system clock at VDD = 5V and 25C, see Electrical Specifications section for information on variation
over voltage and temperature.
In addition, a calibration instruction is programmed into
the top of memory which contains the calibration value
for the internal RC oscillator. This location is never code
protected regardless of the code protect settings. This
value is programmed as a MOVLW XX instruction where
XX is the calibration value, and is placed at the reset
vector. This will load the W register with the calibration
value upon reset and the PC will then roll over to the
users program at address 0x000. The user then has the
option of writing the value to the OSCCAL Register
(05h) or ignoring it.
8.3
RESET
DS40139E-page 38
PIC12C5XX
TABLE 8-3:
Power-on Reset
MCLR Reset
WDT time-out
Wake-up on Pin Change
W (PIC12C508/509)
W (PIC12C508A/509A/
PIC12CE518/519/
PIC12CE509A)
INDF
00h
xxxx xxxx
uuuu uuuu
TMR0
01h
xxxx xxxx
uuuu uuuu
PC
02h
1111 1111
STATUS
03h
0001 1xxx
1111 1111
q00q quuu (2,3)
FSR (PIC12C508/
PIC12C508A/
PIC12CE518)
04h
111x xxxx
111u uuuu
FSR (PIC12C509/
PIC12C509A/
PIC12CE519/
PIC12CR509A)
04h
110x xxxx
11uu uuuu
OSCCAL
(PIC12C508/509)
05h
0111 ----
uuuu ----
OSCCAL
(PIC12C508A/509A/
PIC12CE518/512/
PIC12CR509A)
05h
1000 00--
uuuu uu--
GPIO
(PIC12C508/PIC12C509/
PIC12C508A/
PIC12C509A/
PIC12CR509A)
06h
--xx xxxx
--uu uuuu
GPIO
(PIC12CE518/
PIC12CE519)
06h
Register
11xx xxxx
Legend:
Note 1:
Note 2:
Note 3:
1111 1111
1111 1111
TRIS
11uu uuuu
OPTION
--11 1111
--11 1111
TABLE 8-4:
Power on reset
0001 1xxx
1111 1111
000u uuuu
1111 1111
0001 0uuu
1111 1111
0000 0uuu
1111 1111
0000 uuuu
1111 1111
1001 0uuu
1111 1111
DS40139E-page 39
PIC12C5XX
8.3.1
MCLR ENABLE
FIGURE 8-7:
MCLR SELECT
MCLRE
WEAK
PULL-UP
GP3/MCLR/V PP
8.4
INTERNAL MCLR
The PIC12C5XX family incorporates on-chip PowerOn Reset (POR) circuitry which provides an internal
chip reset for most power-up situations.
The on-chip POR circuit holds the chip in reset until
VDD has reached a high enough level for proper operation. To take advantage of the internal POR, program
the GP3/MCLR/VPP pin as MCLR and tie through a
resistor to VDD or program the pin as GP3. An internal
weak pull-up resistor is implemented using a transistor.
Refer to Table 11-1 for the pull-up resistor ranges. This
will eliminate external RC components usually needed
to create a Power-on Reset. A maximum rise time for
VDD is specified. See Electrical Specifications for
details.
DS40139E-page 40
PIC12C5XX
FIGURE 8-8:
VDD
Pin Change
Wake-up on
pin change
SLEEP
GP3/MCLR/VPP
WDT Time-out
MCLRE
RESET
On-Chip
DRT OSC
8-bit Asynch
Ripple Counter
(Start-Up Timer)
CHIP RESET
FIGURE 8-9:
VDD
MCLR
INTERNAL POR
TDRT
DRT TIME-OUT
INTERNAL RESET
FIGURE 8-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISE TIME
VDD
MCLR
INTERNAL POR
TDRT
DRT TIME-OUT
INTERNAL RESET
DS40139E-page 41
PIC12C5XX
FIGURE 8-11: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE TIME
V1
VDD
MCLR
INTERNAL POR
TDRT
DRT TIME-OUT
INTERNAL RESET
When VDD rises slowly, the TDRT time-out expires long before VDD has reached its final value. In
this example, the chip will reset properly if, and only if, V1 VDD min.
8.5
DS40139E-page 42
8.6
TABLE 8-5:
Oscillator
Configuration
Subsequent
Resets
IntRC &
ExtRC
18 ms (typical)
300 s (typical)
XT & LP
18 ms (typical)
18 ms (typical)
PIC12C5XX
8.6.1
WDT PERIOD
8.6.2
0
1
Watchdog
Timer
Postscaler
Postscaler
U
X
8 - to - 1 MUX
PS2:PS0
PSA
WDT Enable
Configuration Bit
PSA
MUX
Note: T0CS, T0SE, PSA, PS2:PS0
are bits in the OPTION register.
WDT
Time-out
TABLE 8-6:
Address
N/A
Name
OPTION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-On
Reset
GPWU
GPPU
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
Value on
All Other
Resets
1111 1111
Legend: Shaded boxes = Not used by Watchdog Timer, = unimplemented, read as 0, u = unchanged
DS40139E-page 43
PIC12C5XX
8.7
R1
TABLE 8-7:
R2
VDD
Q1
MCLR
TO/PD/GPWUF STATUS
AFTER RESET
GPWUF
TO
PD
VDD
40k* PIC12C5XX
RESET caused by
8.8
Reset on Brown-Out
= 0.7V
R1
R1 + R2
Vss
bypass
capacitor
VDD
VDD
RST
MCLR
PIC12C5XX
VDD
VDD
33k
10k
Q1
MCLR
40k* PIC12C5XX
DS40139E-page 44
PIC12C5XX
8.9
SLEEP
8.10
8.11
ID Locations
DS40139E-page 45
PIC12C5XX
8.12
The PIC12C5XX microcontrollers with EPROM program memory can be serially programmed while in the
end application circuit. This is simply done with two
lines for clock and data, and three other lines for power,
ground, and the programming voltage. This allows customers to manufacture boards with unprogrammed
devices, and then program the microcontroller just
before shipping the product. This also allows the most
recent firmware or a custom firmware to be programmed.
The device is placed into a program/verify mode by
holding the GP1 and GP0 pins low while raising the
MCLR (VPP) pin from VIL to VIHH (see programming
specification). GP1 becomes the programming clock
and GP0 becomes the programming data. Both GP1
and GP0 are Schmitt Trigger inputs in this mode.
After reset, a 6-bit command is then supplied to the
device. Depending on the command, 14-bits of program data are then supplied to or from the device,
depending if the command was a load or a read. For
complete details of serial programming, please refer to
the PIC12C5XX Programming Specifications.
External
Connector
Signals
To Normal
Connections
PIC12C5XX
+5V
VDD
0V
VSS
VPP
MCLR/VPP
CLK
GP1
Data I/O
GP0
VDD
To Normal
Connections
DS40139E-page 46
PIC12C5XX
9.0
TABLE 9-1:
OPCODE FIELD
DESCRIPTIONS
Field
FIGURE 9-1:
Destination select;
d = 0 (store result in W)
d = 1 (store result in file register f)
Default is d = 1
label
11
OPCODE
11
OPCODE
0
k (literal)
OPCODE
0
k (literal)
Time-Out bit
PD
TO
Program Counter
WDT
8 7
5 4
b (BIT #)
f (FILE #)
Top of Stack
PC
0
f (FILE #)
Label name
TOS
5
d
d = 0 for destination W
d = 1 for destination f
f = 5-bit file register address
6
OPCODE
Description
Power-Down bit
dest
[ ]
Options
( )
Contents
Assigned to
<>
italics
In the set of
User defined term (font is courier)
DS40139E-page 47
PIC12C5XX
TABLE 9-2:
Mnemonic,
Operands
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
DECFSZ
INCF
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
f,d
f,d
f
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
f, d
f, d
f, d
f, d
f, d
12-Bit Opcode
Description
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
Move W to f
No Operation
Rotate left f through Carry
Rotate right f through Carry
Subtract W from f
Swap f
Exclusive OR W with f
LSb
Status
Affected Notes
Cycles
MSb
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
0001
0001
0000
0000
0010
0000
0010
0010
0011
0001
0010
0000
0000
0011
0011
0000
0011
0001
11df
01df
011f
0100
01df
11df
11df
10df
11df
00df
00df
001f
0000
01df
00df
10df
10df
10df
ffff
ffff
ffff
0000
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
0000
ffff
ffff
ffff
ffff
ffff
C,DC,Z
Z
Z
Z
Z
Z
None
Z
None
Z
Z
None
None
C
C
C,DC,Z
None
Z
1,2,4
2,4
4
1
1
1 (2)
1 (2)
0100
0101
0110
0111
bbbf
bbbf
bbbf
bbbf
ffff
ffff
ffff
ffff
None
None
None
None
2,4
2,4
1
2
1
2
1
1
1
2
1
1
1
1110
1001
0000
101k
1101
1100
0000
1000
0000
0000
1111
kkkk
kkkk
0000
kkkk
kkkk
kkkk
0000
kkkk
0000
0000
kkkk
kkkk
kkkk
0100
kkkk
kkkk
kkkk
0010
kkkk
0011
0fff
kkkk
Z
None
TO, PD
None
Z
None
None
None
TO, PD
None
Z
2,4
2,4
2,4
2,4
2,4
2,4
1,4
2,4
2,4
1,2,4
2,4
2,4
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
k
k
k
k
k
k
f
k
Note 1: The 9th bit of the program counter will be forced to a 0 by any instruction that writes to the PC except for GOTO.
(Section 4.6)
2: When an I/O register is modified as a function of itself (e.g. MOVF GPIO, 1), the value used will be that value
present on the pins themselves. For example, if the data latch is 1 for a pin configured as input and is driven
low by an external device, the data will be written back with a 0.
3: The instruction TRIS f, where f = 6 causes the contents of the W register to be written to the tristate latches of
GPIO. A 1 forces the pin to a hi-impedance state and disables the output buffers.
4: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared
(if assigned to TMR0).
DS40139E-page 48
PIC12C5XX
ADDWF
Add W and f
Syntax:
[ label ] ADDWF
Operands:
Operation:
ANDWF
AND W with f
Syntax:
[ label ] ANDWF
0 f 31
d [0,1]
Operands:
0 f 31
d [0,1]
Operation:
f,d
0001
Description:
f,d
Status Affected: Z
11df
ffff
Encoding:
0001
01df
ffff
Description:
Words:
Words:
Cycles:
Cycles:
Example:
ADDWF
Example:
ANDWF
FSR, 0
Before Instruction
W
=
FSR =
FSR,
Before Instruction
0x17
0xC2
W =
FSR =
0x17
0xC2
After Instruction
After Instruction
W
=
FSR =
W
=
FSR =
0xD9
0xC2
ANDLW
Syntax:
[ label ] ANDLW
BCF
Operands:
0 k 255
Operation:
0x17
0x02
Bit Clear f
Syntax:
[ label ] BCF
Operands:
0 f 31
0b7
Status Affected: Z
Operation:
0 (f<b>)
Encoding:
1110
Description:
kkkk
Cycles:
Example:
ANDLW
=
0100
0x5F
0xA3
bbbf
f,b
ffff
Description:
Words:
1
1
Example:
After Instruction
=
Encoding:
Cycles:
Before Instruction
kkkk
Words:
BCF
FLAG_REG,
Before Instruction
FLAG_REG = 0xC7
After Instruction
FLAG_REG = 0x47
0x03
DS40139E-page 49
PIC12C5XX
BSF
Bit Set f
Syntax:
[ label ] BSF
BTFSS
Operands:
Operation:
Syntax:
0 f 31
0b7
Operands:
0 f 31
0b<7
1 (f<b>)
Operation:
skip if (f<b>) = 1
f,b
0101
bbbf
ffff
Description:
Words:
Cycles:
Example:
BSF
Encoding:
FLAG_REG,
Description:
FLAG_REG = 0x0A
Words:
ffff
Cycles:
1(2)
Example:
FLAG_REG = 0x8A
bbbf
Before Instruction
After Instruction
0111
HERE
FALSE
TRUE
BTFSC
Syntax:
Operands:
0 f 31
0b7
FLAG,1
PROCESS_CODE
Before Instruction
skip if (f<b>) = 0
BTFSS
GOTO
After Instruction
Operation:
PC
bbbf
0110
ffff
If FLAG<1>
PC
if FLAG<1>
PC
address (HERE)
=
=
=
=
0,
address (FALSE);
1,
address (TRUE)
Words:
Cycles:
1(2)
Example:
HERE
FALSE
TRUE
BTFSC
GOTO
FLAG,1
PROCESS_CODE
Before Instruction
PC
address (HERE)
=
=
=
=
0,
address (TRUE);
1,
address(FALSE)
After Instruction
if FLAG<1>
PC
if FLAG<1>
PC
DS40139E-page 50
PIC12C5XX
CALL
Subroutine Call
CLRW
Syntax:
[ label ] CALL k
Syntax:
[ label ] CLRW
Operands:
0 k 255
Operands:
None
Operation:
Operation:
00h (W);
1Z
1001
kkkk
kkkk
Status Affected: Z
Encoding:
Cycles:
Example:
HERE
CALL
Cycles:
Example:
CLRW
Before Instruction
W
CLRWDT
address (HERE)
[ label ] CLRF
Operands:
0 f 31
Operation:
00h (f);
1Z
Operation:
00h WDT;
0 WDT prescaler (if assigned);
1 TO;
1 PD
0000
0000
011f
Words:
ffff
Example:
FLAG_REG
Before Instruction
=
0x5A
=
=
0x00
1
After Instruction
Example:
CLRF
0100
Cycles:
Cycles:
0000
Description:
FLAG_REG
Z
0x00
1
None
Status Affected: Z
FLAG_REG
=
=
Operands:
Clear f
Syntax:
Words:
0x5A
Syntax:
address (THERE)
address (HERE + 1)
Encoding:
THERE
After Instruction
Description:
0000
Words:
W
Z
Before Instruction
CLRF
0100
PC =
TOS =
0000
Description:
After Instruction
Words:
PC =
Clear W
CLRWDT
Before Instruction
WDT counter =
After Instruction
WDT counter
WDT prescale
TO
PD
=
=
=
=
0x00
0
1
1
DS40139E-page 51
PIC12C5XX
COMF
Complement f
Syntax:
[ label ] COMF
Operands:
Operation:
DECFSZ
0 f 31
d [0,1]
Operands:
0 f 31
d [0,1]
(f) (dest)
Operation:
(f) 1 d;
Encoding:
0010
01df
ffff
Description:
Words:
Encoding:
Cycles:
COMF
Description:
REG1,0
Words:
Before Instruction
0x13
=
=
HERE
0x13
0xEC
Decrement f
Syntax:
Operation:
PC
(f) 1 (dest)
CNT
if CNT
PC
if CNT
PC
Status Affected: Z
Words:
11df
address (HERE)
=
=
=
CNT - 1;
0,
address (CONTINUE);
0,
address (HERE+1)
GOTO
Unconditional Branch
DECF
Before Instruction
CNT,
[ label ]
0 k 511
Operation:
Example:
Syntax:
Operands:
Cycles:
=
=
ffff
CNT
Z
CNT, 1
LOOP
Before Instruction
0 f 31
d [0,1]
0000
DECFSZ
GOTO
CONTINUE
After Instruction
Operands:
Encoding:
ffff
1(2)
Example:
DECF
Description:
11df
Cycles:
After Instruction
REG1
W
0010
Example:
skip if result = 0
Status Affected: Z
REG1
Decrement f, Skip if 0
Syntax:
f,d
k PC<8:0>;
STATUS<6:5> PC<10:9>
GOTO k
Encoding:
101k
kkkk
kkkk
Description:
Words:
After Instruction
CNT
Z
=
=
0x00
1
Cycles:
Example:
GOTO THERE
After Instruction
PC =
DS40139E-page 52
address (THERE)
PIC12C5XX
INCF
Increment f
IORLW
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 f 31
d [0,1]
Operands:
0 k 255
Operation:
(f) + 1 (dest)
Operation:
INCF f,d
Description:
Words:
Encoding:
0010
10df
ffff
CNT,
=
=
1
IORLW
0x35
Before Instruction
Before Instruction
CNT
Z
kkkk
Words:
Example:
INCF
kkkk
Cycles:
Example:
1101
Description:
Cycles:
IORLW k
Status Affected: Z
Status Affected: Z
Encoding:
0x9A
After Instruction
0xFF
0
W
Z
=
=
0xBF
0
After Instruction
CNT
Z
=
=
0x00
1
IORWF
Inclusive OR W with f
Syntax:
INCFSZ
[ label ]
Operands:
Increment f, Skip if 0
0 f 31
d [0,1]
(W).OR. (f) (dest)
Syntax:
[ label ]
Operands:
0 f 31
d [0,1]
Operation:
Encoding:
Operation:
INCFSZ f,d
Encoding:
0011
f,d
Status Affected: Z
0001
00df
ffff
Description:
IORWF
11df
Inclusive OR the W register with register 'f'. If 'd' is 0 the result is placed in
the W register. If 'd' is 1 the result is
placed back in register 'f'.
Words:
ffff
Cycles:
Example:
IORWF
RESULT, 0
Before Instruction
RESULT =
W
=
0x13
0x91
After Instruction
Words:
Cycles:
1(2)
Example:
HERE
INCFSZ
GOTO
CONTINUE
CNT,
LOOP
RESULT =
W
=
Z
=
0x13
0x93
0
Before Instruction
PC
address (HERE)
After Instruction
CNT
if CNT
PC
if CNT
PC
=
=
=
CNT + 1;
0,
address (CONTINUE);
0,
address (HERE +1)
DS40139E-page 53
PIC12C5XX
MOVF
Move f
Syntax:
[ label ]
MOVWF
Operands:
0 f 31
d [0,1]
Operation:
(f) (dest)
0010
Description:
[ label ]
0 f 31
Operation:
(W) (f)
Encoding:
00df
ffff
Cycles:
0000
001f
ffff
Description:
Words:
Cycles:
Example:
MOVWF
Example:
MOVF
TEMP_REG
W
FSR,
TEMP_REG
=
=
0xFF
0x4F
=
=
0x4F
0x4F
After Instruction
TEMP_REG
W
After Instruction
=
Before Instruction
Words:
MOVWF
Status Affected: Z
Encoding:
Move W to f
Syntax:
Operands:
MOVF f,d
NOP
No Operation
MOVLW
Move Literal to W
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
None
Operands:
0 k 255
Operation:
No operation
Operation:
k (W)
MOVLW k
Encoding:
1100
Description:
kkkk
kkkk
Words:
MOVLW
Words:
0000
No operation.
1
Cycles:
1
NOP
Example:
0000
Description:
Example:
Cycles:
0000
NOP
0x5A
After Instruction
W
DS40139E-page 54
0x5A
PIC12C5XX
OPTION
RLF
Syntax:
[ label ]
Syntax:
[ label ] RLF
Operands:
None
Operands:
Operation:
(W) OPTION
0 f 31
d [0,1]
Operation:
OPTION
0000
Description:
0000
0010
Words:
Cycles:
Status Affected: C
Encoding:
Description:
Example
OPTION
0011
Words:
0x07
Cycles:
Return with Literal in W
Syntax:
[ label ]
Operands:
k (W);
TOS PC
RLF
0 k 255
Operation:
Example:
RETLW
1000
Description:
RETLW k
kkkk
REG1
C
REG1
W
C
Cycles:
Example:
;value.
ADDWF PC
;W = offset
RETLW k1
;Begin table
RETLW k2
;
RETLW kn
; End of table
0x07
After Instruction
W
value of k8
1110 0110
0
=
=
=
1110 0110
1100 1100
1
kkkk
Words:
Before Instruction
=
=
After Instruction
TABLE
REG1,0
Before Instruction
ffff
register f
0x07
OPTION =
01df
Before Instruction
After Instruction
f,d
RRF
Syntax:
[ label ]
Operands:
0 f 31
d [0,1]
Operation:
RRF f,d
Status Affected: C
Encoding:
Description:
0011
C
Words:
00df
ffff
Cycles:
Example:
RRF
REG1,0
Before Instruction
REG1
C
=
=
1110 0110
0
After Instruction
REG1
W
C
=
=
=
1110 0110
0111 0011
0
DS40139E-page 55
PIC12C5XX
SLEEP
SUBWF
Subtract W from f
Syntax:
[label]
Syntax:
[label]
Operands:
None
Operands:
Operation:
00h WDT;
0 WDT prescaler;
1 TO;
0 PD
0 f 31
d [0,1]
Operation:
SLEEP
SUBWF f,d
0000
10df
ffff
Description:
GPWUF is unaffected.
Words:
Cycles:
Example 1:
SUBWF
Encoding:
Description:
0000
0000
0011
Words:
Cycles:
Example:
SLEEP
REG1, 1
Before Instruction
REG1
W
C
=
=
=
3
2
?
After Instruction
REG1
W
C
=
=
=
1
2
1
; result is positive
Example 2:
Before Instruction
REG1
W
C
=
=
=
2
2
?
After Instruction
REG1
W
C
=
=
=
0
2
1
; result is zero
Example 3:
Before Instruction
REG1
W
C
=
=
=
1
2
?
After Instruction
REG1
W
C
DS40139E-page 56
=
=
=
FF
2
0
; result is negative
PIC12C5XX
SWAPF
Swap Nibbles in f
XORLW
Syntax:
Syntax:
[label]
Operands:
0 f 31
d [0,1]
Operands:
0 k 255
(f<3:0>) (dest<7:4>);
(f<7:4>) (dest<3:0>)
Operation:
Operation:
Status Affected: Z
Encoding:
XORLW k
1111
kkkk
kkkk
Description:
Words:
Cycles:
Words:
Example:
XORLW
Cycles:
Example
SWAPF
Encoding:
0011
Description:
10df
ffff
REG1,
0xB5
After Instruction
Before Instruction
REG1
0xAF
Before Instruction
0xA5
0x1A
After Instruction
REG1
W
=
=
0xA5
0X5A
XORWF
Exclusive OR W with f
Syntax:
[ label ] XORWF
Operands:
0 f 31
d [0,1]
Operation:
TRIS
Syntax:
[ label ] TRIS
Operands:
f=6
Status Affected: Z
Operation:
Encoding:
f,d
0000
Description:
0001
10df
ffff
Description:
0000
0fff
Words:
Words:
Cycles:
Cycles:
Example
XORWF
Example
TRIS
GPIO
Before Instruction
W
0XA5
After Instruction
TRIS
Note:
REG,1
Before Instruction
0XA5
REG
W
=
=
0xAF
0xB5
After Instruction
REG
W
=
=
0x1A
0xB5
DS40139E-page 57
PIC12C5XX
NOTES:
DS40139E-page 58
PIC12C5XX
10.0
DEVELOPMENT SUPPORT
10.1
Development Tools
10.2
10.3
10.4
The PRO MATE II Universal Programmer is a full-featured programmer capable of operating in stand-alone
mode as well as PC-hosted mode. PRO MATE II is CE
compliant.
The PRO MATE II has programmable VDD and VPP
supplies which allows it to verify programmed memory
at VDD min and VDD max for maximum reliability. It has
an LCD display for displaying error messages, keys to
enter commands and a modular detachable socket
assembly to support various package types. In standalone mode the PRO MATE II can read, verify or program
PIC12CXXX,
PIC14C000,
PIC16C5X,
PIC16CXXX and PIC17CXX devices. It can also set
configuration and code-protect bits in this mode.
10.5
The PICSTART programmer is an easy-to-use, lowcost prototype programmer. It connects to the PC via
one of the COM (RS-232) ports. MPLAB Integrated
Development Environment software makes using the
programmer simple and efficient. PICSTART Plus is not
recommended for production programming.
PICSTART Plus supports all PIC12CXXX, PIC14C000,
PIC16C5X, PIC16CXXX and PIC17CXX devices with
up to 40 pins. Larger pin count devices such as the
PIC16C923, PIC16C924 and PIC17C756 may be supported with an adapter socket. PICSTART Plus is CE
compliant.
MPLAB-ICE
is
available
in
two
versions.
MPLAB-ICE 1000 is a basic, low-cost emulator system
with simple trace capabilities. It shares processor modules with the MPLAB-ICE 2000. This is a full-featured
emulator system with enhanced trace, trigger, and data
monitoring features. Both systems will operate across
the entire operating speed range of the PICmicro
MCU.
DS40139E-page 59
PIC12C5XX
10.6
10.7
DS40139E-page 60
10.8
10.9
PIC12C5XX
10.10
10.12
10.13
10.11
Assembler (MPASM)
The MPASM Universal Macro Assembler is a PChosted symbolic assembler. It supports all microcontroller series including the PIC12C5XX, PIC14000,
PIC16C5X, PIC16CXXX, and PIC17CXX families.
MPASM offers full featured Macro capabilities, conditional assembly, and several source and listing formats.
It generates various object code formats to support
Microchip's development tools as well as third party
programmers.
MPASM allows full symbolic debugging from MPLABICE, Microchips Universal Emulator System.
MPASM has the following features to assist in developing software for specific use applications.
Provides translation of Assembler source code to
object code for all Microchip microcontrollers.
Macro assembly capability.
Produces all the files (Object, Listing, Symbol, and
special) required for symbolic debug with
Microchips emulator systems.
Supports Hex (default), Decimal and Octal source
and listing formats.
MPLAB-C17 Compiler
For easier source level debugging, the compiler provides symbol information that is compatible with the
MPLAB IDE memory display.
10.14
fuzzyTECH-MP fuzzy logic development tool is available in two versions - a low cost introductory version,
MP Explorer, for designers to gain a comprehensive
working knowledge of fuzzy logic system design; and a
full-featured version, fuzzyTECH-MP, Edition for implementing more complex systems.
Both versions include Microchips fuzzyLAB demonstration board for hands-on experience with fuzzy logic
systems implementation.
10.15
DS40139E-page 61
PIC12C5XX
10.16
DS40139E-page 62
Emulator Products
Software Tools
HCS200
HCS300
HCS301
KEELOQ
Transponder Kit
KEELOQ
Evaluation Kit
PICDEM-3
PICDEM-2
PICDEM-1
PICDEM-14A
SIMICE
SEEVAL
Designers Kit
KEELOQ
Programmer
24CXX
25CXX
93CXX
PRO MATE II
Universal
Programmer
PICSTARTPlus
Low-Cost
Universal Dev. Kit
Total Endurance
Software Model
PIC17C7XX
fuzzyTECH-MP
Explorer/Edition
Fuzzy Logic
Dev. Tool
MPLAB C17*
Compiler
MPLAB
Integrated
Development
Environment
ICEPIC Low-Cost
In-Circuit Emulator
MPLAB-ICE
PIC14000
Programmers
TABLE 10-1:
Demo Boards
PIC12C5XX
PIC12C5XX
DS40139E-page 63
PIC12C5XX
NOTES:
DS40139E-page 64
PIC12C5XX
11.0
NOTICE: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
DS40139E-page 65
PIC12C5XX
11.1
DC CHARACTERISTICS:
DC Characteristics
Power Supply Pins
Parm
No.
Characteristic
Sym
Min
Typ(1)
2.5
Max
Units
5.5
5.5
Conditions
D001
Supply Voltage
VDD
D002
VDR
1.5*
VSS
V/ms
3.0
Voltage(2)
D003
VPOR
D004
SVDD 0.05
*
Supply Current(3)
.78
2.4
mA
D010C
1.1
2.4
mA
D010A
10
27
14
35
14
35
IPD
0.25
0.25
2
4
5
18
A
A
A
IWDT
3.75
3.75
3.75
8
9
14
A
A
A
D010
IDD
DS40139E-page 66
PIC12C5XX
11.2
DC CHARACTERISTICS:
DC CHARACTERISTICS
Param
No.
Characteristic
Input Low Voltage
I/O ports
with TTL buffer
D030
D031
D032
D033
D040
D040A
V
V
V
V
VSS
0.3VDD
Note1
VSS
D033
0.8V
0.15VDD
0.15VDD
0.15VDD
0.15VDD
VSS
VSS
VSS
VIL
2.0V
0.25VDD + 0.8V
0.85VDD
0.85VDD
0.7VDD
0.85VDD
50
250
IPUR
VDD
VDD
V
V
VDD
VDD
VDD
VDD
400
V
V
V
V
A
-1
0.5
+1
VIH
VSS
D041
D042
D042A
D043
D070
D060
D061
MCLR, GP2/T0CKI
20
130
0.5
250
+5
A
A
D063
OSC1
-3
0.5
+3
D080
VOL
0.6
VOH
VDD - 0.7
COSC2
15
pF
D090
D100
IIL
Note1
VDD = 5V, VPIN = VSS
For VDD 5.5V
50
pF
All I/O pins
CIO
Data in Typ column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that
the PIC12C5XX be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as coming out of the pin.
D101
DS40139E-page 67
PIC12C5XX
TABLE 11-1:
VDD (Volts)
Min
Typ
Max
Units
42K
48K
49K
55K
17K
20K
22K
24K
63K
63K
63K
63K
20K
23K
25K
28K
346K
414K
457K
504K
292K
341K
371K
407K
417K
532K
532K
593K
360K
437K
448K
500K
GP0/GP1
2.5
5.5
40
25
85
125
40
25
85
125
38K
42K
42K
50K
15K
18K
19K
22K
40
25
85
125
40
25
85
125
285K
343K
368K
431K
247K
288K
306K
351K
GP3
2.5
5.5
DS40139E-page 68
PIC12C5XX
11.3
The timing parameter symbols have been created following one of the following formats:
1. TppS2ppS
2. TppS
T
F
Frequency
Time
MCLR
to
mc
ck
CLKOUT
osc
oscillator
cy
cycle time
os
OSC1
drt
t0
T0CKI
io
I/O port
wdt
watchdog timer
Period
Fall
High
Rise
Invalid (Hi-impedance)
Valid
Low
Hi-impedance
Pin
15 pF for OSC2 in XT or LP
modes when external clock
is used to drive OSC1
DS40139E-page 69
PIC12C5XX
11.4
Q1
Q3
Q2
Q4
Q1
OSC1
1
TABLE 11-2:
AC Characteristics
Parameter
No.
DC
FOSC
Characteristic
Min
DC
Sym
200
Max
Units
Conditions
Oscillator Frequency
LP osc mode
(2)
0.1
3
4
Tcy
ns
ns
XT osc mode
ms
LP osc mode
250
ns
10,000
ns
XT osc mode
ms
LP osc mode
4/FOSC
50*
ns
ms
LP oscillator
25*
ns
XT oscillator
2*
Oscillator Period(2)
kHz
250
250
(2)
200
TOSC
250
DC
50*
ns
LP oscillator
LP osc mode
EXTRC osc mode
XT oscillator
Note 1: Data in the Typical (Typ) column is at 5V, 25C unless otherwise stated. These parameters are for design
guidance only and are not tested.
2: All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable
oscillator operation and/or higher than expected current consumption.
When an external clock input is used, the max cycle time limit is DC (no clock) for all devices.
3: Instruction cycle period (TCY) equals four times the input oscillator time base period.
DS40139E-page 70
PIC12C5XX
TABLE 11-3:
AC Characteristics
Parameter
No.
Typ(1)
3.58
4.00
4.32
3.50
4.26
Sym
Characteristic
Max* Units
Conditions
Note 1: Data in the Typical (Typ) column is at 5V, 25C unless otherwise stated. These parameters are for design
guidance only and are not tested.
FIGURE 11-3:
Q4
Q2
Q3
OSC1
I/O Pin
(input)
17
I/O Pin
(output)
19
18
New Value
Old Value
20, 21
Note: All tests must be done with specified capacitive loads (see data sheet) 50 pF on I/O pins and CLKOUT.
DS40139E-page 71
PIC12C5XX
TABLE 11-4:
AC Characteristics
Parameter
No.
Sym
Min
Characteristic
(3)
Typ(1)
Max
Units
17
TosH2ioV
100*
ns
18
TosH2ioI
TBD
ns
19
TioV2osH
TBD
ns
20
TioR
10
25**
ns
21
TioF
10
25**
ns
time(2, 3)
FIGURE 11-4: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER TIMING - PIC12C508/C509
VDD
MCLR
30
Internal
POR
32
32
32
DRT
Timeout
(Note 2)
Internal
RESET
Watchdog
Timer
RESET
31
34
34
I/O pin
(Note 1)
Note 1: I/O pins must be taken out of hi-impedance mode by enabling the output drivers in software.
2: Runs in MCLR or WDT reset only in XT and LP modes.
DS40139E-page 72
PIC12C5XX
TABLE 11-5:
Sym
Characteristic
30
TmcL
2000*
ns
VDD = 5 V
31
Twdt
9*
18*
30*
ms
VDD = 5 V (Commercial)
32
TDRT
9*
18*
30*
ms
VDD = 5 V (Commercial)
34
TioZ
2000*
ns
Min
Typ(1)
Max
Units
Conditions
TABLE 11-6:
Oscillator Configuration
POR Reset
Subsequent Resets
18 ms (typical)
300 s (typical)
XT & LP
18 ms (typical)
18 ms (typical)
DS40139E-page 73
PIC12C5XX
FIGURE 11-5: TIMER0 CLOCK TIMINGS - PIC12C508/C509
T0CKI
40
41
42
TABLE 11-7:
AC Characteristics
Parameter
Sym Characteristic
No.
40
Min
41
Tt0L
42
ns
10*
ns
ns
10*
ns
20 or TCY + 40*
N
ns
Whichever is greater.
N = Prescale Value
(1, 2, 4,..., 256)
DS40139E-page 74
PIC12C5XX
12.0
The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables
the data presented are outside specified operating range (e.g., outside specified VDD range). This is for information
only and devices will operate properly only within the specified range.
The data presented in this section is a statistical summary of data collected on units from different lots over a period of
time. Typical represents the mean of the distribution while max or min represents (mean + 3) and (mean 3)
respectively, where is standard deviation.
4.50
4.50
4.40
4.40
4.30
4.30
4.10
Max.
4.00
3.90
4.20
4.10
Max.
4.00
3.90
3.80
3.80
3.70
Min.
3.70
3.60
3.50
-40
Frequency (MHz)
Frequency (MHz)
4.20
Min.
25
85
Temperature (Deg.C)
125
3.60
3.50
-40
25
85
Temperature (Deg.C)
125
DS40139E-page 75
PIC12C5XX
TABLE 12-1:
Oscillator
Frequency
VDD = 2.5V
External RC
4 MHz
250 A*
Internal RC
4 MHz
420 A
XT
4 MHz
251 A
LP
32 KHz
15 A
*Does not include current through external R&C.
VDD = 5.5V
780 A*
1.1 mA
780 A
37 A
50
900
45
800
40
700
WDT period (s)
35
30
Max +125C
25
600
500
Max +125C
Max +85C
Max +85C
400
20
Typ +25C
300
Typ +25C
15
200
10
MIn 40C
MIn 40C
100
2
5
2
VDD (Volts)
VDD (Volts)
DS40139E-page 76
PIC12C5XX
FIGURE 12-5: IOH vs. VOH, VDD = 2.5 V
-1
20
Max 40C
15
-3
IOL (mA)
IOH (mA)
-2
-4
Min +
-5
-6
Typ +25C
10
125 C
Min +85C
85C
Min +
Min +125C
Typ +25C
C
Max 40
-7
500m
1.0
1.5
2.0
2.5
VOH (Volts)
250.0m
500.0m
1.0
VOL (Volts)
50
-5
Max 40C
40
30
+1
25
Min +85C
20
Min +125C
10
ax
-25
4
0
Ty
p
+2
5
C
in
+8
in
M
-20
Typ +25C
IOL (mA)
-15
IOH (mA)
-10
-30
3.5
4.0
4.5
VOH (Volts)
5.0
5.5
0
250.0m
500.0m
750.0m
1.0
VOL (Volts)
DS40139E-page 77
PIC12C5XX
NOTES:
DS40139E-page 78
PIC12C5XX
13.0
NOTICE: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
DS40139E-page 79
PIC12C5XX
13.1
DC CHARACTERISTICS:
DC Characteristics
Power Supply Pins
Parm
No.
Characteristic
Sym
Min
Typ(1)
3.0
Max
Units
Conditions
5.5
D001
Supply Voltage
VDD
D002
VDR
1.5*
D003
VPOR
VSS
D004
SVDD
0.05*
V/ms
D010
Supply Current(3)
IDD
0.8
1.4
mA
D010C
0.8
1.4
mA
D010A
19
27
19
35
30
55
IPD
0.25
0.25
2
4
5
12
A
A
A
IWDT
2.2
2.2
4
5
6
11
A
A
A
IEE
0.1
0.2
mA
D020
Power-Down Current (5)
D021
D021B
D022
Power-Down Current
DS40139E-page 80
PIC12C5XX
13.2
DC CHARACTERISTICS:
DC Characteristics
Power Supply Pins
Parm
No.
Characteristic
Sym
VDD
D002
VDR
D003
VPOR
D004
V/ms
SVDD 0.05*
D010
VSS
Supply Voltage
1.5*
D001
5.5
0.4
0.8
mA
D010C
0.4
0.8
mA
D010A
15
23
15
31
0.2
0.2
3
4
A
A
2.0
2.0
4
5
mA
mA
D020
Power-Down Current (5)
D021
D021B
IDD
Conditions
IPD
IWDT
DS40139E-page 81
PIC12C5XX
13.3
DC CHARACTERISTICS:
DC CHARACTERISTICS
Param
No.
Characteristic
Input Low Voltage
I/O ports
with TTL buffer
D030
D031
D032
D033
D033
D040
D040A
D041
D042
D042A
D043
D070
D060
D061
D063
VIL
VSS
VSS
VSS
VSS
VSS
VSS
VIH
T0CKI
OSC1
D080
IPUR
-
Note 1:
2:
3:
4:
Note 1
Note 1
VDD
VDD
VDD
VDD
VDD
VDD
400
30
V
V
V
V
V
A
A
otherwise
For entire VDD range
+1
+5
+5
A
A
0.6
0.6
VDD - 0.7
VDD - 0.7
Capacitive Loading Specs on
Output Pins
OSC2 pin
COSC2
15
pF
CIO
50
Note 1
VDD = 5V, VPIN = VSS
VDD = 5V, VPIN = VSS
pF
VOL
VOH
D090A
D101
V
V
V
V
D100
0.25VDD +
0.8V
2.0V
0.8VDD
0.8VDD
0.7VDD
0.9VDD
30
250
-
0.8V
0.15VDD
0.2VDD
0.2VDD
0.2VDD
0.3VDD
IIL
D080A
D090
Data in Typ column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not
tested.
In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC12C5XX be driven with external clock in RC mode.
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent
normal operating conditions. Higher leakage current may be measured at different input voltages.
Negative current is defined as coming out of the pin.
This spec. applies when GP3/MCLR is configured as MCLR. The leakage current of the MCLR circuit is higher than the
standard I/O logic.
DS40139E-page 82
PIC12C5XX
13.4
DC CHARACTERISTICS:
DC CHARACTERISTICS
Param
No.
Characteristic
Input Low Voltage
I/O ports
with TTL buffer
D030
D031
D032
D033
D033
D040
D040A
D041
D042
D042A
D043
D070
D060
D061
D063
VIL
VSS
VSS
VSS
VSS
VSS
VSS
VIH
T0CKI
OSC1
D080
IPUR
-
Note 1:
2:
3:
4:
VDD
VDD
VDD
VDD
VDD
VDD
400
30
V
V
V
V
V
A
A
otherwise
For entire VDD range
VOH
COSC
2
CIO
+1
+5
+5
A
A
0.6
0.6
VDD - 0.7
VDD - 0.7
VOL
D090A
D101
V
V
V
V
V
V
D100
0.25VDD + 0.8V
2.0V
0.8VDD
0.8VDD
0.7VDD
0.9VDD
30
250
-
0.8V
0.15VDD
0.2VDD
0.2VDD
0.2VDD
0.3VDD
IIL
D080A
D090
15
pF
50
Note 1
Note 1
Note 1
VDD = 5V, VPIN = VSS
VDD = 5V, VPIN = VSS
pF
Data in Typ column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not
tested.
In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC12C5XX be driven with external clock in RC mode.
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent
normal operating conditions. Higher leakage current may be measured at different input voltages.
Negative current is defined as coming out of the pin.
This spec. applies when GP3/MCLR is configured as MCLR. The leakage current of the MCLR circuit is higher than the
standard I/O logic.
DS40139E-page 83
PIC12C5XX
TABLE 13-1:
VDD (Volts)
Min
Typ
Max
Units
42K
48K
49K
55K
17K
20K
22K
24K
63K
63K
63K
63K
20K
23K
25K
28K
346K
414K
457K
504K
292K
341K
371K
407K
417K
532K
532K
593K
360K
437K
448K
500K
GP0/GP1
2.5
5.5
40
25
85
125
40
25
85
125
38K
42K
42K
50K
15K
18K
19K
22K
40
25
85
125
40
25
85
125
285K
343K
368K
431K
247K
288K
306K
351K
GP3
2.5
5.5
DS40139E-page 84
PIC12C5XX
13.5
The timing parameter symbols have been created following one of the following formats:
1. TppS2ppS
2. TppS
T
F
Frequency
Time
MCLR
to
mc
ck
CLKOUT
osc
oscillator
cy
cycle time
os
OSC1
drt
t0
T0CKI
io
I/O port
wdt
watchdog timer
Period
Fall
High
Rise
Invalid (Hi-impedance)
Valid
Low
Hi-impedance
Pin
DS40139E-page 85
PIC12C5XX
13.6
Q1
Q3
Q2
Q4
Q1
OSC1
1
TABLE 13-2:
AC Characteristics
Parameter
No.
DC
Characteristic
Min
DC
Sym
MHz
XT osc mode
200
kHz
LP osc mode
DC
MHz
MHz
XT osc mode
DC
TOSC
Conditions
200
kHz
LP osc mode
Oscillator Frequency(2)
Units
0.1
FOSC
Max
ns
XT osc mode
ms
LP osc mode
250
ns
250
10,000
ns
XT osc mode
Oscillator Period(2)
ms
LP osc mode
4/FOSC
ns
ms
LP oscillator
25*
ns
XT oscillator
Tcy
50*
2*
2
3
50*
ns
LP oscillator
XT oscillator
Note 1: Data in the Typical (Typ) column is at 5V, 25C unless otherwise stated. These parameters are for design
guidance only and are not tested.
2: All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable
oscillator operation and/or higher than expected current consumption.
When an external clock input is used, the max cycle time limit is DC (no clock) for all devices.
3: Instruction cycle period (TCY) equals four times the input oscillator time base period.
DS40139E-page 86
PIC12C5XX
TABLE 13-3:
AC Characteristics
Parameter
No.
Typ(1)
3.65
4.00
4.28
3.55
4.31
Sym
Characteristic
Max* Units
Conditions
Note 1: Data in the Typical (Typ) column is at 5V, 25C unless otherwise stated. These parameters are for design
guidance only and are not tested.
DS40139E-page 87
PIC12C5XX
FIGURE 13-3:
Q4
Q2
Q3
OSC1
I/O Pin
(input)
17
I/O Pin
(output)
18
19
New Value
Old Value
20, 21
Note: All tests must be done with specified capacitive loads (see data sheet) 50 pF on I/O pins and CLKOUT.
TABLE 13-4:
AC Characteristics
Parameter
No.
Sym
Characteristic
Typ(1)
Max
Units
100*
ns
17
TosH2ioV
18
TosH2ioI
TBD
ns
19
TioV2osH
TBD
ns
20
TioR
10
25**
ns
21
TioF
10
25**
ns
(3)
(2, 3)
DS40139E-page 88
PIC12C5XX
FIGURE 13-4: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER TIMING PIC12C508A, PIC12C509A, PIC12CE518, PIC12CE519, PIC12LC508A,
PIC12LC509A, PIC12LCR509A, PIC12LCE518 and PIC12LCE519
VDD
MCLR
30
Internal
POR
32
32
32
DRT
Timeout
(Note 2)
Internal
RESET
Watchdog
Timer
RESET
31
34
34
I/O pin
(Note 1)
Note 1: I/O pins must be taken out of hi-impedance mode by enabling the output drivers in software.
2: Runs in MCLR or WDT reset only in XT and LP modes.
TABLE 13-5:
Sym
Characteristic
30
TmcL
31
Twdt
32
TDRT
34
TioZ
Min
Typ(1)
Max
Units
Conditions
2000*
ns
VDD = 5 V
9*
18*
30*
ms
VDD = 5 V (Commercial)
9*
18*
30*
ms
VDD = 5 V (Commercial)
2000*
ns
DS40139E-page 89
PIC12C5XX
TABLE 13-6:
Oscillator Configuration
POR Reset
Subsequent Resets
(1)
300 s (typical)(1)
(1)
18 ms (typical)(1)
18 ms (typical)
XT & LP
18 ms (typical)
Note 1: Data in the Typical (Typ) column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only
and are not tested.
T0CKI
40
41
42
TABLE 13-7:
AC Characteristics
Parameter
Sym Characteristic
No.
Min
40
41
Tt0L
- With Prescaler
T0CKI Low Pulse Width - No Prescaler
- With Prescaler
42
ns
ns
10*
ns
10*
ns
20 or TCY + 40*
N
ns
Whichever is greater.
N = Prescale Value
(1, 2, 4,..., 256)
DS40139E-page 90
PIC12C5XX
TABLE 13-8:
AC Characteristics
Parameter
Min
Max
Units
Clock frequency
FCLK
100
100
400
kHz
THIGH
4000
4000
600
ns
TLOW
4700
4700
1300
ns
TR
1000
1000
300
ns
Conditions
TF
300
ns
(Note 1)
THD:STA
4000
4000
600
ns
TSU:STA
4700
4700
600
ns
THD:DAT
ns
(Note 2)
TSU:DAT
250
250
100
ns
TSU:STO
4000
4000
600
ns
TAA
3500
3500
900
ns
TBUF
4700
4700
1300
ns
TOF
20+0.1
CB
250
ns
TSP
50
ns
(Notes 1, 3)
TWC
Endurance
ms
1M
cycles
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined TSP and VHYS specifications are due to new Schmitt trigger inputs which provide improved
noise spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained on Microchips website.
DS40139E-page 91
PIC12C5XX
NOTES:
DS40139E-page 92
PIC12C5XX
14.0
The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables
the data presented are outside specified operating range (e.g., outside specified VDD range). This is for information
only and devices will operate properly only within the specified range.
The data presented in this section is a statistical summary of data collected on units from different lots over a period of
time. Typical represents the mean of the distribution while max or min represents (mean + 3) and (mean 3)
respectively, where is standard deviation.
4.50
4.50
4.40
4.40
4.30
4.30
4.10
4.00
3.90
4.10
4.00
3.90
3.80
3.80
Min.
3.70
3.70
3.60
3.60
3.50
-40
M
ax.
4.20
M
ax.
Frequency (MHz)
Frequency (MHz)
4.20
25
85
Temperature (Deg.C)
125
3.50
-40
M .
in
0
25
85
125
Temperature (Deg.C)
DS40139E-page 93
PIC12C5XX
TABLE 14-1:
Oscillator
Frequency
VDD =3.0V
External RC
4 MHz
240 A*
Internal RC
4 MHz
320 A
XT
4 MHz
300 A
LP
32 KHz
19 A
*Does not include current through external R&C.
VDD = 5.5V
800 A*
800 A
800 A
50 A
550
500
500
450
450
400
400
350
350
IDD (A)
600
550
IDD (A)
600
300
300
250
250
200
200
150
150
100
100
0
2.5
3.0
4.5
VDD (V
olts)
DS40139E-page 94
5.0
5.5
.5
1.0
1.5
2.0
2.5
3.0
3.5 4.0
Frequency (MHz)
PIC12C5XX
FIGURE 14-7: IOH vs. VOH, VDD = 2.5 V
-0
50
-1
-2
45
-3
-4
35
Max +125C
IOH (mA)
40
30
Min +125C
Min +85C
-5
-6
Typ +25C
Max +85C
-7
25
-8
20
Typ +25C
-9
15
Max -40C
-10
MIn 40C
10
0
2.5
3.5
4.5
5.5
VOH (Volts)
6.5
VDD (Volts)
950
850
-5
IOH (mA)
750
650
Min +125C
-10
Min +85C
550
Max +125C
450
-15
Max +85C
Typ +25C
Max -40C
-20
350
Typ +25C
-25
250
1.5
2.0
2.5
3.0
3.5
MIn 40C
VOH (Volts)
150
0
0
2.5
3.5
4.5
5.5
6.5
VDD (Volts)
DS40139E-page 95
PIC12C5XX
FIGURE 14-9: IOL vs. VOL, VDD = 2.5 V
35
0
-5
30
Max -40C
-10
25
20
Typ +25C
IOH (mA)
IOL (mA)
-15
15
Mi
n+
C
5
12
C
85
n+
Mi
C
25
p+
Ty
-20
-25
10
4
0
C
Min +85C
ax
-30
Min +125C
-35
-40
0
0
0.25
0.5
0.75
3.5
1.0
4.0
4.5
5.0
5.5
VOH (Volts)
VOL (Volts)
55
Max -40C
Max -40C
50
40
45
35
40
30
35
25
Typ +25C
IOL (mA)
IOL (mA)
Typ +25C
20
30
25
Min +85C
20
15
Min +85C
15
Min +125C
10
Min +125C
10
0
0
0.25
0.5
VOL (Volts)
DS40139E-page 96
0.75
1.0
0.25
0.5
0.75
1.0
VOL (Volts)
1999 Microchip Technology Inc.
PIC12C5XX
FIGURE 14-13: TYPICAL IPD VS. VDD,
WATCHDOG DISABLED (25C)
250
1.6
VTH (Volts)
260
Ipd (nA)
240
1.4
230
220
1.0
210
Typ (25)
1.2
0.8
200
2.5
0.6
3.0
3.5
4.5
VDD (Volts)
5.0
5.5
0
2.5
3.5
4.5
5.5
VDD (Volts)
DS40139E-page 97
PIC12C5XX
FIGURE 14-15: VIL, VIH OF NMCLR, AND T0CKI VS. VDD
3.5
Vih Max (-40 to 125)
VIH Typ (25)
VIH Min (-40 to 125)
3.0
2.5
2.0
VIL Max (-40 to 125)
1.5
1.0
0.5
2.5
3.5
4.5
5.5
VDD (Volts)
DS40139E-page 98
PIC12C5XX
15.0
PACKAGING INFORMATION
15.1
12C508A
04I/PSAZ
9825
9825
Example
12C508A
04I/SM
9824SAZ
Example
JW
XXX
12C508A
XXXXXX
Legend: MM...M
XX...X
AA
BB
C
D
E
Example
C508A
AABB
Note:
Example
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask
rev#, and assembly code. For OTP marking beyond this, certain price adders apply. Please check with
your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.
DS40139E-page 99
PIC12C5XX
Package Type:
D
2
1
E1
A
A1
A2
B1
p
eB
Units
Dimension Limits
PCB Row Spacing
Number of Pins
Pitch
Lower Lead Width
Upper Lead Width
Shoulder Radius
Lead Thickness
Top to Seating Plane
Top of Lead to Seating Plane
Base to Seating Plane
Tip to Seating Plane
Package Length
Molded Package Width
Radius to Radius Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
B
INCHES*
NOM
0.300
8
0.100
0.018
0.014
0.060
0.055
0.005
0.000
0.012
0.006
0.150
0.140
0.080
0.060
0.020
0.005
0.130
0.120
0.370
0.355
0.250
0.245
0.280
0.267
0.310
0.342
5
10
5
10
MIN
n
p
B
B1
R
c
A
A1
A2
L
D
E
E1
eB
MAX
0.022
0.065
0.010
0.015
0.160
0.100
0.035
0.140
0.385
0.260
0.292
0.380
15
15
MILLIMETERS
NOM
MAX
7.62
8
2.54
0.36
0.56
0.46
1.40
1.65
1.52
0.00
0.25
0.13
0.20
0.29
0.38
3.81
3.56
4.06
2.03
1.52
2.54
0.51
0.13
0.89
3.30
3.05
3.56
9.40
9.02
9.78
6.35
6.22
6.60
7.10
6.78
7.42
7.87
8.67
9.65
5
10
15
5
10
15
MIN
* Controlling Parameter.
Dimension B1 does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003
(0.076 mm) per side or 0.006 (0.152 mm) more than dimension B1.
Dimensions D and E do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed 0.010 (0.254 mm) per side or 0.020 (0.508 mm) more than dimensions D or E.
DS40139E-page 100
PIC12C5XX
Package Type:
p
D
2
B
X
45
L
R2
R1
Units
Dimension Limits
Pitch
Number of Pins
Overall Pack. Height
Shoulder Height
Standoff
Molded Package Length
Molded Package Width
Outside Dimension
Chamfer Distance
Shoulder Radius
Gull Wing Radius
Foot Length
Foot Angle
Radius Centerline
Lead Thickness
Lower Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
L1
A2
INCHES*
NOM
0.050
8
0.054
0.061
0.027
0.035
0.004
0.007
0.189
0.193
0.150
0.154
0.229
0.237
0.010
0.015
0.005
0.005
0.005
0.005
0.011
0.016
0
4
0.000
0.005
0.008
0.009
0.014
0.017
0
12
0
12
MIN
p
n
A
A1
A2
D
E
E1
X
R1
R2
L
L1
c
B
A1
MAX
0.069
0.044
0.010
0.196
0.157
0.244
0.020
0.010
0.010
0.021
8
0.010
0.010
0.020
15
15
MILLIMETERS
NOM
MAX
1.27
8
1.37
1.56
1.75
0.69
0.90
1.11
0.10
0.18
0.25
4.80
4.89
4.98
3.90
3.99
3.81
5.82
6.01
6.20
0.25
0.38
0.51
0.13
0.13
0.25
0.13
0.13
0.25
0.28
0.41
0.53
0
4
8
0.00
0.13
0.25
0.19
0.22
0.25
0.36
0.43
0.51
0
12
15
0
12
15
MIN
Controlling Parameter.
Dimension B does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003
(0.076 mm) per side or 0.006 (0.152 mm) more than dimension B.
Dimensions D and E do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed 0.010 (0.254 mm) per side or 0.020 (0.508 mm) more than dimensions D or E.
DS40139E-page 101
PIC12C5XX
Package Type:
E1
E
p
D
2
n
L
R2
R1
L1
Units
Dimension Limits
Pitch
Number of Pins
Overall Pack. Height
Shoulder Height
Standoff
Molded Package Length
Molded Package Width
Outside Dimension
Shoulder Radius
Gull Wing Radius
Foot Length
Foot Angle
Radius Centerline
Lead Thickness
Lower Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
INCHES*
NOM
0.050
8
0.070
0.074
0.037
0.042
0.005
0.002
0.200
0.205
0.203
0.208
0.300
0.313
0.005
0.005
0.005
0.005
0.011
0.016
0
4
0.010
0.015
0.008
0.009
0.014
0.017
0
12
0
12
MIN
p
n
A
A1
A2
D
E
E1
R1
R2
L
L1
c
B
A1
A2
MAX
0.079
0.048
0.009
0.210
0.213
0.325
0.010
0.010
0.021
8
0.020
0.010
0.020
15
15
MILLIMETERS
NOM
MAX
1.27
8
1.78
1.89
2.00
0.94
1.08
1.21
0.14
0.22
0.05
5.08
5.21
5.33
5.16
5.28
5.41
7.62
7.94
8.26
0.13
0.13
0.25
0.13
0.25
0.13
0.28
0.41
0.53
0
4
8
0.38
0.51
0.25
0.19
0.22
0.25
0.36
0.43
0.51
0
12
15
0
12
15
MIN
Controlling Parameter.
Dimension B does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003
(0.076 mm) per side or 0.006 (0.152 mm) more than dimension B.
Dimensions D and E do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed 0.010 (0.254 mm) per side or 0.020 (0.508 mm) more than dimensions D or E.
DS40139E-page 102
PIC12C5XX
Package Type:
K04-084 8-Lead Ceramic Side Brazed Dual In-line with Window (JW) 300 mil
D
2
n
A1
L
A2
c
B1
p
eB
Units
Dimension Limits
PCB Row Spacing
Number of Pins
Pitch
Lower Lead Width
Upper Lead Width
Lead Thickness
Top to Seating Plane
Top of Body to Seating Plane
Base to Seating Plane
Tip to Seating Plane
Package Length
Package Width
Overall Row Spacing
Window Diameter
Lid Length
Lid Width
MIN
n
p
B
B1
c
A
A1
A2
L
D
E
eB
W
T
U
0.098
0.016
0.050
0.008
0.145
0.103
0.025
0.130
0.510
0.280
0.310
0.161
0.440
0.260
INCHES*
NOM
0.300
8
0.100
0.018
0.055
0.010
0.165
0.123
0.035
0.140
0.520
0.290
0.338
0.166
0.450
0.270
MAX
0.102
0.020
0.060
0.012
0.185
0.143
0.045
0.150
0.530
0.300
0.365
0.171
0.460
0.280
MILLIMETERS
NOM
MAX
7.62
8
2.49
2.54
2.59
0.41
0.46
0.51
1.27
1.40
1.52
0.20
0.25
0.30
3.68
4.19
4.70
2.62
3.12
3.63
0.64
0.89
1.14
3.30
3.56
3.81
12.95
13.21
13.46
7.11
7.37
7.62
7.87
9.27
8.57
4.34
4.09
4.22
11.18
11.43
11.68
6.60
6.86
7.11
MIN
* Controlling Parameter.
DS40139E-page 103
PIC12C5XX
NOTES:
DS40139E-page 104
PIC12C5XX
INDEX
A
ALU ....................................................................................... 9
Applications........................................................................... 4
Architectural Overview .......................................................... 9
Assembler
MPASM Assembler..................................................... 61
B
Block Diagram
On-Chip Reset Circuit ................................................. 41
Timer0......................................................................... 25
TMR0/WDT Prescaler................................................. 28
Watchdog Timer.......................................................... 43
Brown-Out Protection Circuit .............................................. 44
O
OPTION Register................................................................ 17
OSC selection..................................................................... 35
OSCCAL Register............................................................... 18
Oscillator Configurations..................................................... 36
Oscillator Types
HS............................................................................... 36
LP ............................................................................... 36
RC .............................................................................. 36
XT ............................................................................... 36
Q cycles.............................................................................. 12
E
EEPROM Peripheral Operation .......................................... 29
Errata .................................................................................... 3
F
Family of Devices.................................................................. 5
Features ................................................................................ 1
FSR ..................................................................................... 20
Fuzzy Logic Dev. System (fuzzyTECH-MP) .................... 61
I
I/O Interfacing ..................................................................... 21
I/O Ports .............................................................................. 21
I/O Programming Considerations........................................ 22
ICEPIC Low-Cost PIC16CXXX In-Circuit Emulator ............ 59
ID Locations .................................................................. 35, 45
INDF.................................................................................... 20
Indirect Data Addressing..................................................... 20
Instruction Cycle ................................................................. 12
Instruction Flow/Pipelining .................................................. 12
Instruction Set Summary..................................................... 48
K
KeeLoq Evaluation and Programming Tools.................... 62
L
Loading of PC ..................................................................... 19
M
Memory Organization.......................................................... 13
Data Memory .............................................................. 14
Program Memory ........................................................ 13
MPLAB Integrated Development Environment Software .... 61
R
RC Oscillator....................................................................... 37
Read Modify Write .............................................................. 22
Register File Map................................................................ 14
Registers
Special Function ......................................................... 15
Reset .................................................................................. 35
Reset on Brown-Out ........................................................... 44
S
SEEVAL Evaluation and Programming System .............. 61
SLEEP .......................................................................... 35, 45
Software Simulator (MPLAB-SIM) ...................................... 61
Special Features of the CPU .............................................. 35
Special Function Registers................................................. 15
Stack................................................................................... 19
STATUS ............................................................................... 9
STATUS Register ............................................................... 16
T
Timer0
Switching Prescaler Assignment ................................ 28
Timer0 ........................................................................ 25
Timer0 (TMR0) Module .............................................. 25
TMR0 with External Clock .......................................... 27
Timing Diagrams and Specifications ............................ 70, 86
Timing Parameter Symbology and Load Conditions .... 69, 85
TRIS Registers ................................................................... 21
W
Wake-up from SLEEP......................................................... 45
Watchdog Timer (WDT)................................................ 35, 42
Period ......................................................................... 43
Programming Considerations ..................................... 43
WWW, On-Line Support ....................................................... 3
Z
Zero bit ................................................................................. 9
DS40139E-page 105
PIC12C5XX
DS40139E-page 106
PIC12C5XX
ON-LINE SUPPORT
Microchip provides on-line support on the Microchip
World Wide Web (WWW) site.
The web site is used by Microchip as a means to make
files and information easily available to customers. To
view the site, the user must have access to the Internet
and a web browser, such as Netscape or Microsoft
Explorer. Files are also available for FTP download
from our FTP site.
DS40139E-page 107
PIC12C5XX
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (602) 786-7578.
Please list the following information, and use this outline to provide us with your comments about this Data Sheet.
To:
RE:
Reader Response
From: Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________
Application (optional):
Would you like a reply?
Device: PIC12C5XX
N
Literature Number: DS40139E
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this data sheet easy to follow? If not, why?
4. What additions to the data sheet do you think would enhance the structure and subject?
5. What deletions from the data sheet could be made without affecting the overall usefulness?
8. How would you improve our software, systems, and silicon products?
DS40139E-page 108
PIC12C5XX
PIC12C5XX Product Identification System
Examples
Special Requirements
Package:
SN
SM
P
JW
=
=
=
=
Temperature
Range:
I
E
= 0C to +70C
= -40C to +85C
= -40C to +125C
Frequency
Range:
04
= 4 MHz
Device
PIC12C508
PIC12C509
PIC12C508T (Tape & reel for SOIC only)
PIC12C509T (Tape & reel for SOIC only)
PIC12C508A
PIC12C509A
PIC12C508AT (Tape & reel for SOIC only)
PIC12C509AT (Tape & reel for SOIC only)
PIC12LC508A
PIC12LC509A
PIC12LC508AT (Tape & reel for SOIC only)
PIC12LC509AT (Tape & reel for SOIC only)
PIC12CR509A
PIC12CR509AT (Tape & reel for SOIC only)
PIC12LCR509A
PIC12LCR509AT (Tape & reel for SOIC only)
PIC12CE518
PIC12CE518T (Tape & reel for SOIC only)
PIC12CE519
PIC12CE519T (Tape & reel for SOIC only)
PIC12LCE518
PIC12LCE518T (Tape & reel for SOIC only)
PIC12LCE519
PIC12LCE519T (Tape & reel for SOIC only)
a)
c)
PIC12C508A-04/P
Commercial Temp.,
PDIP Package, 4 MHz,
normal VDD limits
PIC12C508A-04I/SM
Industrial Temp., SOIC
package, 4 MHz, normal
VDD limits
PIC12C509-04I/P
Industrial Temp.,
PDIP package, 4 MHz,
normal VDD limits
Please contact your local sales office for exact ordering procedures.
DS40139E-page 109
PIC12C5XX
NOTES:
DS40139E-page 110
PIC12C5XX
NOTES:
DS40139E-page 111
Note the following details of the code protection feature on PICmicro MCUs.
The PICmicro family meets the specifications contained in the Microchip Data Sheet.
Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today,
when used in the intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the PICmicro microcontroller in a manner outside the operating specifications contained in the data sheet.
The person doing so may be engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as unbreakable.
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of
our product.
If you have any further questions about this matter, please contact the local sales office nearest to you.
Trademarks
The Microchip name and logo, the Microchip logo, FilterLab,
KEELOQ, microID, MPLAB, PIC, PICmicro, PICMASTER,
PICSTART, PRO MATE, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, microPort,
Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM,
MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode
and Total Endurance are trademarks of Microchip Technology
Incorporated in the U.S.A.
Serialized Quick Turn Programming (SQTP) is a service mark
of Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
2002, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
M
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01/18/02