FPGA implementation of Binary Coded Decimal Digit Adders and Multipliers AIM: The main aim of the project

is to design FPGA implementation of Binary Coded Decimal Digit Adders and Multipliers. (ABST ACT! Decimal arithmetic has gained high impact on the overall performance of todays financial and commercial applications. Decimal additions and multiplication are the main decimal operations used in any decimal arithmetic algorithm. Decimal digit adders and decimal digit multipliers are usually the building blocks for higher order decimal adders and multipliers. FP !s provide an efficient hard"are platform that can be employed for accelerating decimal algorithms. #n this paper$ different designs for t"o decimal digit adders and one decimal digit multiplier are proposed. The proposed designs "ere described$ functionally tested$ and implemented using %&D' and the (ilin) #*+ ,.- targeting (ilin) %erti)./ (0/%'(12.1 FP !. #mplementation results and comparison "ith e)isting designs are provided. Proposed Met"od: #n this architecture different designs for t"o decimal digit adders and one decimal digit multiplier are proposed. Decimal additions and multiplication are the main decimal operations used in any decimal arithmetic algorithm. Decimal digit adders and decimal digit multipliers are usually the building blocks for higher order decimal adders and multipliers. FP !s provide an efficient hard"are platform that
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can be employed for accelerating decimal algorithms. "e can increase the number of bits.

Ad#antage: Decimal additions and multiplication are the main decimal operations used in any decimal arithmetic algorithm. Decimal digit adders and decimal digit multipliers are usually the building blocks for higher order decimal adders and multipliers. B$%C& DIAG AM:

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Fig. 3 t"o levels implementation of the proposed 40D digit adder

T%%$S5 (#''#6( #*+ ,.-i$ 78D+' *#7 9.:c 'F' '(C': ;3< #47 0orporation$ Decimal F!=$ http5>>"""-.hursley.ibm.com>

decimal>decifa?3.html. ;-< 7. F. 0o"lisha"$ Decimal floating.point5 !lgorism for computers$ in Proceedings of the 39th #+++ *ymposium on 0omputer !rithmetic @!A#T&. 3921B$ Cashington$ D0$ D*!$ -221$ !A#T& 21$ pp. 32:E$ #+++ 0omputer *ociety. ;1< !. Tsang and 7. 8lschano"sky$ ! study of database - customer ?ueries$ Tech. Aep.$ #47 Technical Aeport$ #47 *anta Teresa 'aboratory$ *an Fose$ 0!$ !pril 3,,3. ;:< 7. *. *chmookler and !. Ceinberger$ &igh speed decimal addition$ #+++ Transactions on 0omputers$ vol. -2$ pp. G9-EG99$ 3,H3. ;/< &. Cetter C. 4ultmann$ C. &aller and !. Corner$ 4inary and decimal adder unit$ -223.

V.Mallikarjuna (Project manager)

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Na'()r

Mobile No: +91-8297578555. Branch !: "#$ ra%a$ &