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Fei Yuan, Ph.D, P.Eng. Department of Electrical & Computer Engineering Ryerson University Copyright c 2006
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OUTLINE
Introduction to ESD Principle Sources of ESD in ICs ESD Models ESD Protection Mechanisms ESD Protection Devices ESD Protection Circuits Layout of ESD Protection Circuits
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Introduction to ESD
What is ESD ?
ESD - Electro-Static Discharge. ESD is a transient discharge of static charge that arises from either human handling or a machine contact. Although ESD is the result of a static potential in a charged object, the energy dissipated and damage made are mainly due to the current in ICs during discharge. Most ESD damage is thermally initiated in the form of device / interconnect burn-out or oxide break-down. The basic phenomenon is for sucient heat to be generated in a localized volume signicantly faster than it can be removed, leading to a temperature in excess of the materials safe operating limits. pn-junction may melt. Gate oxide may have void formation. Metal interconnects & Vias may melt or vaporization, leading to shorts or opens. Gate-oxide breakdown is another form of ESD damage.
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Student Version of MATLAB
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Figure 3: Scaling of the breakdown voltage of gate oxide and the avalanche breakdown voltage.
The level of ESD stress, however, does not scale down with the technology.
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ESD Models
Human Body Model (HBM)
HBM models the ESD of a human body. Peak current 1.3A, rise time 10-30ns.
Human body model R=1.5kW
VC (0 - )
C=100pF
DUT
Figure 4: Equivalent circuit for the human body model of ESD. The switch closes upon an ESD event.
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VC (0 - ) C=200pF
DUT
Figure 5: Equivalent circuit for the machine model of ESD. The switch closes upon an ESD event.
ESD stress caused by charged machines is sever because of zero body resistance.
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DUT
Figure 6: Equivalent circuit of charged device model of ESD. The switch closes upon an ESD event.
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vn = n E,
vp = p E,
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where vn and vp are the velocity of free electrons and that of holes, respectively, n and p are the bulk mobility of free electrons and holes, respectively. The total charge crossing a cross-section of area A per second is given by
Q = (vnn + vp p)Aq, where n and p are the concentration of free electrons and holes, respectively, and q is the charge of an electron. The current density is obtained from Q = (nn + pp )qE = E, A
Copyright (c) F. Yuan 2006 (11)
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J=
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where
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Current Density
For n-type, the concentration of free electronics is approximately the doping of the donors, i.e. nnn , where nn is the doping of donors, we have vnn E . Consequently
J Jn = (nnn E )q = nn vn q = E
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4 10 V/cm
n-well resistors exhibit a large resistance in the saturation region show above. n-well resistors in the saturation region can be used as current-limiting devices for ESD protection by limiting the amount of ESD discharging current.
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PAD D
p+
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n+ n+
Isub
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p-substrate
Figure 9: Parasitic lateral BJT in nMOS transistors.
nMOS is used as ESD protection devices. Gate is grounded to ensure nMOS is o under normal operation conditions. Drain-substrate/source-substrate pn-junctions are reverse biased. A parasitic lateral BJT as shown exists in the substrate. Under normal operation conditions, this parasitic BJT is o because both the pn-junctions of the nMOS transistor are reverse biased.
Copyright (c) F. Yuan 2006 (15)
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(Vt2 , I t2 ) Thermal breakdown Snapback region (ESD protection operation region) Avalanche breakdown Vsh (Vt1 , I t1 )
Slope=1/R sh
VD
Figure 10: Avalanche breakdown, snap back, and thermal breakdown of nMOS transistors.
When the BJT is ON, more electrons ows from the source to the drain ID and VD decreases sharply until the snapback holding voltage Vsp is reached. The snapback holding voltage is mainly across the drain-substrate pc-junction. The marginal increase of the drain voltage is due to voltage drop across the drain diusion, source diusion, and contact resistance. During snapback, the resistance has positive temperature coecients. This implies that if the current in any region increases, the temperature of the region will increase, thereby increasing the resistance, which encourages the current to ow elsewhere current is conducted uniformly by all gures of nMOS transistors.
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Vsp
VD
Vsp
VD
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Poly-resistor
N-well resistor
Poly-resistors should not be used as ESD protection devices due to their poor heat dissipation capability (Poly resistors are isolated from the substrate by the SiO2 layer). Note that the heat generated by ICs are taken away via two paths (i) PADs/traces/pins and (ii) substrate/ground plate. n-well resistors have good contact with the substrate. They are used as primary current-limiting devices. When a n-well resistor is used as the current-limiting device, together with a nMOS (primary ESD protection device), it is essential to make sure that the n-well resistor will not enter its thermal breakdown when the nMOS is in its avalanche breakdown.
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Figure 13: Diodes in CMOS. (a) p+ /n-well diodes; (b) n+ /p-well diodes; (c) ESD protection using diodes.
Two main types of diodes : n+ /p-well diodes and p+ /n-well diodes. p+ /n-well diodes have a pn-junction between the n-well and p-substrate whereas there is no isolation between the diode and the p-substrate in n+ /p-well diodes. When forward-biased, diodes can sustain a large current with a small device dimension.
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G SS
p-substrate
Figure 14: Drain contact-gate spacing (DS) and source contact-gate spacing (SS) of ESD protection nMOS transistors.
During a ESD strike, the pn-junction at the drain undergoes an avalanche breakdown. Holes ow to the substrate, resulting in an increase in VB parasitic BJT will be turned on ESD current ows from the collector the (drain of nMOS) to the emitter (the source of nMOS that is connected to the ground) ESD stress at the drain of the nMOS transistor (PAD) is released. The dimensions of ESD nMOS should be large enough to handle large ESD currents multiple ngers structure is used to implement ESD nMOS. The main design parameters of nMOS are (i) channel length, (ii) drain contact-to-gate spacing, and (iii) device width. The source contact-to-gate spacing is not critical and is kept at its minimum design value.
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i) The minimum channel length is good for ecient turn-on but the punch-through limit will be reduced. ii) Drain contact-to-gate spacing aects the resistance of ballast resistors. For silicided processes, the minimum drain contact-to-gate spacing is used. iii) Device width determines the maximum current that the device can conduct.
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G S Metal-2 Metal-1
Figure 15: Lumped ballast resistors are added at the drains to ensure a uniform ESD current distribution among the ngers of ESD protection transistors.
During an avalanche breakdown, the current owing through the drain increases. However, the positive temperature coecient of the resistance of n+ -diusion (called Ballast Resistors) at the drain prevents current from concentrating in a localized region it forces the ESD current to ow into other ngers uniform current distribution is achieved. The eect of n+ -diusion resistance is virtually eliminated in silicided CMOS processes because in these processes n+ is silicided and the resistance of silicided n+ is small (a few ohms). To preserve the current-limiting ability of ballast resistors, explicit n-well ballast resistors at the drain are added. Note that the sheet resistance of n-well is much higher than that of n+ -diusion.
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R
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ID
Thermal breakdown
Vsp
VD
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PAD pn-junction
Under normal operation, the pn-junction between n-well and p-substrate is reverse biased and SCR has no eect on the operation of the protected circuits. During a ESD strike, the pn-junction undergoes an avalanche breakdown currents ow from n+ through Rnwell to the substrate a sucient voltage drop across Rnwell turns on T2 a large current ows from p+-diusion through Rsub to the ground T1 turns on T1 and T2 latch up to release ESD stress. SCR has a high ESD breakdown voltage (40V with the latch-up time 1ns) as compared with that of nMOS because the breakdown voltage of n+/p-sub is lower than that of n-well/p-sub (large pn-junction width) internal circuits might have already been destroyed even before ESD protection circuits are activated. SCR is not aected by silicidation attractive for modern CMOS processes where silicidation is common.
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n+-diffusion is added
Internal circuits
n+ n+ p+
PAD
p+
n+
During an ESD strike, pn-junction in this region undergoes an avalanche breakdown at a LOWER voltage. Breakdown voltage : 25V for 0.35 CMOS (40V for conventional SCR).
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Grouded-gate is added
PAD
p+
n+
n+
n+
p+
The added gate-grounded nMOS enters avalanche breakdown rst. Avalanche voltage is similar to gate-grounded nMOS (10V approximately).
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Primary ESD protection elements shunt most of ESD currents. Primary ESD protection elements have large width and need more time to turn on. Secondary ESD protection elements serve to limit the voltage at the circuit being protected until the primary ESD protection devices are fully operational. Secondary ESD protection devices have smaller width. The eectiveness of the primary ESD protection devices is determined by the secondary protection stage. Note that due to the small dimensions, the secondary protection devices enter avalanche breakdown before the primary protection devices are activated. It is critical to ensure that the avalanche breakdown of the primary protection devices is activated before the secondary protection devices enter their thermal breakdown so that the secondary ESD protection devices will not be destroyed by ESD stress. Current-limiting resistor has two functions (i) limit the current owing into the internal circuits. (ii) withstand some ESD voltage so that the secondary protection circuit will not be damaged in an ESD strike.
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PAD
Current-limiting resistor
Internal circuits
Both nMOS and pMOS are used for positive and negative ESD strikes. Under normal operation conditions, ESD devices are o minimize the leakage current of these devices.
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zo PAD
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Internal circuits
Figure 22: Top - Distributed ESD protection with equal sections; Bottom - small-signal equivalent circuit.
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PAD
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