Chapter 3:Design Style:3.1 Introduction:Design Style is the way of arranging internal description of circuit architecture.

Different design styles of coding are listed as follows, a) Structural b) Behavioral c) Data flow Each of them is explained in detail in below sections. 3.2:Structural:Structural way of coding is more like instantiating existing design unit (may be gate or functionality of a design) and connect the ports to get the expected behavior of a requirement. Say our requirement is to get an output as high when the inputs(say two bits) are similar.We are having a "exclusive or" functional unit (Example:-2.1) using that we can meet our requirement. Note:- Below code is tested in modelsim starter edition for VHDL-93 standard. Example 3.1:LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY logic_high IS PORT( in_a : IN STD_LOGIC; in_b : IN STD_LOGIC; out_d : OUT STD_LOGIC ); END logic_high; ARCHITECTURE struct_rtl OF logic_high IS

-- Signal Declaration SIGNAL out_1 : STD_LOGIC; -- Instantiation the functionality of "xor_gate" -- "xor_gate.vhd" has to be compiled. COMPONENT xor_gate PORT ( a_i : IN STD_LOGIC; b_i : IN STD_LOGIC; c_o : OUT STD_LOGIC ); END COMPONENT; BEGIN u1: xor_gate PORT MAP( a_i => in_a, b_i => in_b, c_o => out_1 ); u2: xor_gate PORT MAP( a_i => '1', b_i => out_1, c_o => out_d

); END struct_rtl; In the above example shows how to instantiate the functionality of other module and how to connect the ports. There are two way of connecting the ports one is "naming" association as shown in Example 3.1 and other is "positional" association shown in Example 3.2. Note:- In positional association the port has to mapped carefully,it is better to use naming association. Example 3.2:u2:xor_gate PORT MAP( in_c, out_1, out_2 ); 3.3:Behavioral:In Behavioral modeling the internal design will be described by the statements like the process(execute statements based on sensitivity list),sequential(execute statements continuously). Inside the architecture if there are two process then both will occur concurrently. Example 3.3:LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY xor_gate IS PORT( a_i : IN STD_LOGIC; b_i : IN STD_LOGIC; c_o : OUT STD_LOGIC

); END xor_gate; ARCHITECTURE beh_arc OF xor_gate IS BEGIN beh_pro:PROCESS(a_i,b_i) BEGIN c_o <= a_i XOR b_i; END PROCESS beh_pro; END beh_arc; 3.4:Data flow:Way of Data flow modeling the design is using the concurrent statements i.e. execution of statements will be at the same time. Example 3.4:LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY xor_gate IS PORT( a_i : IN STD_LOGIC; b_i : IN STD_LOGIC; c_o : OUT STD_LOGIC );

END xor_gate; ARCHITECTURE data_flow_arc OF xor_gate IS BEGIN c_o <= a_i XOR b_i; END data_flow_arc; Based on the requirement we have to choose the design style. Sometimes we may need to mix all or any two of the design style. Example 3.5:LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY logic_high IS PORT( in_a : IN STD_LOGIC; in_b : IN STD_LOGIC; out_d : OUT STD_LOGIC ); END logic_high; ARCHITECTURE mix_rtl OF logic_high IS SIGNAL out_1 : STD_LOGIC; -- Instantiation the functionality of "xor_gate" -- "xor_gate.vhd" has to be compiled. COMPONENT xor_gate PORT ( a_i : IN STD_LOGIC; b_i : IN STD_LOGIC; c_o : OUT STD_LOGIC

); END COMPONENT; BEGIN -- structural Modeling u1: xor_gate PORT MAP ( a_i => in_a, b_i => in_b, c_o => out_1 ); -- Data flow modeling out_d <= out_1 XOR '1'; END mix_rtl;

Chapter 3:Design Style:-

3.1 Introduction:-

Design Style is the way of arranging internal description of circuit architecture. Different design styles of coding are listed as follows, a) Structural b) Behavioral c) Data flow

Each of them is explained in detail in below sections.

3.2:Structural:-

Structural way of coding is more like instantiating existing design unit (may be gate or functionality of a design) and connect the ports to get the expected behavior of a requirement. Say our requirement is to get an output as high when the inputs(say two bits) are similar.We are having a "exclusive or" functional unit (Example:-2.1) using that we can meet our requirement. Note:- Below code is tested in modelsim starter edition for VHDL-93 standard.

Example 3.1:-

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY logic_high IS

PORT(

in_a : IN STD_LOGIC;

in_b : IN STD_LOGIC;

out_d : OUT STD_LOGIC

);

END logic_high;

ARCHITECTURE struct_rtl OF logic_high IS

-- Signal Declaration

SIGNAL out_1 : STD_LOGIC;

-- Instantiation the functionality of "xor_gate" -- "xor_gate.vhd" has to be compiled.

COMPONENT xor_gate

PORT (

a_i : IN STD_LOGIC;

b_i : IN STD_LOGIC;

c_o : OUT STD_LOGIC

);

END COMPONENT;

BEGIN

u1: xor_gate

PORT MAP(

a_i => in_a,

b_i => in_b,

c_o => out_1

);

u2: xor_gate

PORT MAP( a_i => '1',

b_i => out_1,

c_o => out_d

); END struct_rtl;

In the above example shows how to instantiate the functionality of other module and how to connect the ports. There are two way of connecting the ports one is "naming" association as shown in Example 3.1 and other is "positional" association shown in Example 3.2. Note:- In positional association the port has to mapped carefully,it is better to use naming association.

Example 3.2:-

u2:xor_gate

PORT MAP(

in_c,

out_1,

out_2

);

3.3:Behavioral:-

In Behavioral modeling the internal design will be described by the statements like the process(execute statements based on sensitivity list),sequential(execute statements continuously). Inside the architecture if there are two process then both will occur concurrently.

Example 3.3:-

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY xor_gate IS

PORT(

a_i : IN STD_LOGIC;

b_i : IN STD_LOGIC;

c_o : OUT STD_LOGIC

);

END xor_gate;

ARCHITECTURE beh_arc OF xor_gate IS

BEGIN

beh_pro:PROCESS(a_i,b_i)

BEGIN

c_o <= a_i XOR b_i;

END PROCESS beh_pro;

END beh_arc;

3.4:Data flow:-

Way of Data flow modeling the design is using the concurrent statements i.e. execution of statements will be at the same time.

Example 3.4:-

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY xor_gate IS

PORT(

a_i : IN STD_LOGIC;

b_i : IN STD_LOGIC;

c_o : OUT STD_LOGIC

);

END xor_gate;

ARCHITECTURE data_flow_arc OF xor_gate IS

BEGIN

c_o <= a_i XOR b_i;

END data_flow_arc;

Based on the requirement we have to choose the design style. Sometimes we may need to mix all or any two of the design style.

Example 3.5:-

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY logic_high IS

PORT( in_a : IN STD_LOGIC;

in_b : IN STD_LOGIC; out_d : OUT STD_LOGIC

);

END logic_high; ARCHITECTURE mix_rtl OF logic_high IS

SIGNAL out_1 : STD_LOGIC;

-- Instantiation the functionality of "xor_gate" -- "xor_gate.vhd" has to be compiled.

COMPONENT xor_gate

PORT (

a_i : IN STD_LOGIC;

b_i : IN STD_LOGIC;

c_o : OUT STD_LOGIC

);

END COMPONENT;

BEGIN

-- structural Modeling

u1: xor_gate

PORT MAP (

a_i => in_a,

b_i => in_b,

c_o => out_1

);

-- Data flow modeling

out_d <= out_1 XOR '1';

END mix_rtl; 4. Mixed Style of Modeling

1.FULL ADDER It is possible to mix the three modeling styles that we have seen so far in a single architecture body. That is, within an architecture body, we could use component instantiation statements (that represent structure), concurrent signal assignment statements (that represent dataflow), and process statements (that represent behavior). Here is an example of a mixed style model for a one-bit full-adder shown in Fig. 2.7.

entity FULL_ADDER is port (A, B, CIN: in BIT; SUM, COUT: out BIT); end FULL_ADDER;

architecture FA_MIXED of FULL_ADDER is component XOR2 port (A, B: in BIT; Z: out BIT); end component; signal S1: BIT; begin X1: XOR2 port map (A, B, S1 ); - structure. process (A, B, CIN) - behavior. variable T1, T2, T3: BIT; begin T1 :=A and B; T2 := B and CIN; T3:=A and CIN; COUT <= T1 or T2 or T3; end process; SUM <= S1 xor CIN; - dataflow. end FA_M!XED;

Figure 2.7 A 1-bit full-adder The full-adder is represented using one component instantiation statement, one process statement and one concurrent signal assignment statement. All of these statements are concurrent statements, and therefore, their order of appearance within the architecture body is not important. Note that a process statement itself is a concurrent statement; however, statements within a process statement are always executed sequentially. SI is a signal locally declared within the architecture body and is used to pass the value from the output of the component XI to the expression for signal SUM.