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VLSI Design EE 671

Assignment 5

Instructor: Prof. M.P.Desai

Submitted by: Anuj Srivastava 123079034

[Assignment 5]

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1. Consider the system shown in Figure 1. You are allowed to adjust the delays in blocks A and B subject to the following constraints. A + B 15ns A B 3ns You are free to choose the value of as you wish (it can be positive or negative!). Subject to these constraints, find the values of A,B and which will give you the minimum clock period at which the circuit will operate correctly (Assume that the flip-flops are ideal).

Solution:

Now, by solving the above equations, i.e. A + B 15ns A B 3ns

We, get minimum delay for A state as T A = 9 units And minimum delay for A state as T B = 6 units.

[Assignment 5]

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Now, for correct output following conditions has to be satisfied:TA < TClk + Setup TA > Hold + TB < TClk - Setup TB > Hold - Where, TClk = Clock Time Period = Skew Setup = Set up time Hold = Hold time Now, By taking, = 1 unit, Hold =0 & Setup = 0 Solving eq.1 gives TClk > 8 units Similarly, from eq.2 , we get, TA > 1 which is already true. Similarly, from eq. 3 , we get TClk > 7 units And from eq.4 , we get TB > -1 which is again true. So, From above quations we can see that for the satisfactorily working of the system we get TClk > 8 units. So, for any TClk = 8 + system will work satisfactorily, where is any small positive value.
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..eq.1 ..eq.2 ..eq.3 ....eq.4

2. Consider the system shown in Figure 2. Assume that all the logic between latches consists of static complementary gates (the pair of numbers in each logic block is the minimum and maximum delay in 1ns through the block, excluding the latch delay). Further, assume that the setup time of all latches is 1ns, while the hold time is 0ns. The data to output and clock to output delays of the latches is 1ns. The absolute clock skew across the latches is given to be | | (that means the magnitude of the skew will be at most ||, but the sign of the relative skew between latches is unknown). (a) Assuming that the clock skew is 0, what is the smallest clock period at which this system will operate correctly? Solution:

Given that, Setup time (s) = 1ns Delay due to data to output (dx) = 1ns Now considering skew () = 0 units We know that for satisfactorily performance following conditions shoulb be met:For a state x, dx + s + M TClk ..........................................(condition1)

And on an average, dx + M 2TClk - s ................................... (condition2)


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Where, m denotes minimum delay in combinational circuit of state x & M denotes maximum delay in combinational circuit of state x. Now, For state A (m,M) = (3,6) Therefore, From condition1, we get TClk 8 ns. Similarly, For state B (m,M) = (2,7) Therefore, From condition1, we get TClk 9 ns. Similarly, For state C (m,M) = (3,8) Therefore, From condition1, we get TClk 4 ns. Similarly, For state D (m,M) = (4,5) Therefore, From condition1, we get TClk 7 ns. Now, taking two combinational circuts at a time. Taking A &B we get, MA + MB + 2 < 1.5TClk S We get, TClk > 10.67 ns. Similarly, Taking B &C we get, MB + MC + 2 < 1.5TClk S We get, TClk > 12 ns.

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Similarly, Taking C &D we get, MC + MD + 2 < 1.5TClk S We get, TClk > 10.67 ns. Similarly, Taking D &A we get, MD + MA + 2 < 1.5TClk S We get, TClk > 8 ns. Now, Now, taking three combinational circuts at a time. Taking A ,B & C we get, MA + MB + MC + 3 < 2TClk S We get, TClk > 12.5 ns Similarly, Taking B ,C & D we get, MB + MC + MD + 3 < 2TClk S We get, TClk > 12 ns Similarly, Taking C ,D & A we get, MC + MD + MA + 3 < 2TClk S We get, TClk > 11.5 ns Similarly, Taking D, A & B we get, MD + MA + MB + 3 < 2TClk S We get, TClk > 11 ns
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Now, From condition2,i.e., from final average conditions We get, 4+ (7+8+5+6) 2TClk - s we get TClk 15.5 ns So, From above quations we can see that for the satisfactorily working of the system our get T Clk > 15.5 ns. So, for any TClk = 15.5 + (ns) system will work perfectly, where is any small positive value.

(b) On a two-dimensional T clk, || plane, identify the region in which your circuit will operate correctly (that is, for each value of ||, the set of Tclk values for which the circuit operates correctly). Solution: Given that, Setup time (s) = 1ns Delay due to data to output (dx) = 1ns Now considering skew () = ns We know that for satisfactorily performance following conditions should be met:For a single combinational circuit , dx + s + M + TClk ...................................(condition1) And on an average, dx + M + 2TClk - s ................................... (condition2) But in sequential system = + + -3 = 0 So, condition2 reduces to again as, dx + M + 2TClk - s

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Also, here M changes to M+ for A,B & C, For D, M changes to M-3. Now, For state A (m,M) = (3,6) Therefore, From condition1, we get TClk 8 + ns. Similarly, For state B (m,M) = (2,7) Therefore, From condition1, we get TClk 9 + ns. Similarly, For state C (m,M) = (3,8) Therefore, From condition1, we get TClk 4 + ns. Similarly, For state D (m,M) = (4,5) Therefore, From condition1, we get TClk 7 -3 ns.

Finding range of Also we know that, m+d>H Therefore mA + 1 > H So, < 4ns
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(Here m changes to m - )

Similarly, mB + 1 > H So, < 3ns Similarly, mC + 1 > H So, < 4ns Similarly, md + 1 > H So, > -(4/3)ns Therefore, for this positive skew we get the range as (-4/3 , 3) Similarly, for negative skew, For A,B,C m changes to m + and for D it changes to m - 3. Therefore mA + 1 > H So, > -4ns Similarly, mB + 1 > H So, > -3ns Similarly, mC + 1 > H So, > -4ns Similarly, md + 1 > H So, < (4/3)ns (Here m changes to m - 3) (Here m changes to m + ) (Here m changes to m + ) (Here m changes to m + ) (Here m changes to m + 3) (Here m changes to m - ) (Here m changes to m - )

[Assignment 5]

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So, for negative skew range will be (-3, 4/3). So, final range will be -3 to 3 i.e. (-3,3) So, || 3

Now, I have taken different integers values of in ns and t ry to analyse for what minimum value of TClk gives satisfactory performance. (ns) -3 -2 -1 0 1 2 3 TClk (ns) 16 13 10 9 10 11 12

Now, taking two combinational circuts at a time. Taking A &B we get, MA + MB + 2 < 1.5TClk S We get, TClk > 10.67 + (4/3) ns. Similarly, Taking B &C we get, MB + MC + 2 < 1.5TClk S We get, TClk > 12 + (4/3) ns.
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Similarly, Taking C &D we get, MC + MD + 2 < 1.5TClk S We get, TClk > 10.67 - (4/3) ns. Similarly, Taking D &A we get, MD + MA + 2 < 1.5TClk S We get, TClk > 8 - (4/3) ns. Now, I have taken different integers values of in ns and t ry to analyse for what minimum value of TClk gives satisfactory performance

(ns) -3 -2 -1 0 1 2 3

TClk (ns) 14.67 13.3367 12.0033 12 13.33 14.67 16

Now, taking three combinational circuts at a time. Taking A ,B & C we get, MA + MB + MC + 3 < 2TClk S
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We get, TClk > 12.5 + (3/2) ns. Similarly, Taking B ,C & D we get, MB + MC + MD + 3 < 2TClk S We get, TClk > 12 - (1/2) ns. Similarly, Taking C ,D & A we get, MC + MD + MA + 3 < 2TClk S We get, TClk > 11.5 - (3/2) ns. Similarly, Taking D, A & B we get, MD + MA + MB + 3 < 2TClk S We get, TClk > 11 (1/2) ns Now, I have taken different integers values of in ns and try to analyse for what minimum value of TClk gives satisfactory performance (ns) -3 -2 -1 0 1 2 3 TClk (ns) 16 14.5 13 12.5 14 15.5 17

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Now, From condition2, i.e., from final average conditions We get, 4+ (7+8+5+6) + + + - 3 2TClk - s we get TClk 15.5 ns Now, I have taken different integers values of in ns and t ry to analyse for what minimum value of TClk gives satisfactory performance. (ns) -3 -2 -1 0 1 2 3 TClk (ns) 15.5 15.5 15.5 15.5 15.5 15.5 15.5

[Assignment 5]

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Comparison of all 4 tables

(ns) -3 -2 -1 0 1 2 3

Tclk (SCC) 16 13 10 9 10 11 12

Tclk (DCC) 14.67 13.3367 12.0033 12 13.33 14.67 20

Tclk (TCC) 16 14.5 13 12.5 14 15.5 17

Tclk (Avg.) 15.5 15.5 15.5 15.5 15.5 15.5 15.5

Note: SCC denotes Single Combinational circuit, DCC denotes Double Combinational circuit, TCC denotes Triple Combinational circuit, Avg. denotes average of all 4 Combinational circuit taken at a time.

[Assignment 5]

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Now,after compairing of all the four tables, we figure out that for each value of ||, the set of T clk values for which the circuit operates correctly. (ns)

TClk (ns)

-3 -2 -1 0 1 2 3

16 15.5 15.5 15.5 15.5 15.5 17

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Tclk vs

Region of correct operation: Region above the graph.

[Assignment 5]

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