II Ece - Ec1256 - Ec II Manual

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EC 2257 ELECTRONICS CIRCUITS II AND SIMULATION LAB
1. CURRENT SERIES FEEDBACK AMPLIFIER 2. VOLTAGE SHUNT FEEDBACK AMPLIFIER 3. RC PHASE SHIFT OSCILLATOR 4. HARTLEY OSCILLATOR 5. COLPITTS OSCILLATOR 6. COLLECTOR COUPLED ASTABLE MULTIVIBRATOR 7. EMITTER COUPLED ASTABLE MULTIVIBRATOR 8. MONOSTABLE MULTIVIBRATOR 9. CLASS C TUNNED AMPLIFIERS 10. INTEGRATORS, DIFFERNTIATORS, CLIPPERS AND CLAMPERS.
SIMULATION USING PSPICE
1. ACTIVE FILTER : BUTTERWORTH IInd ORDER LPF 2. ACTIVE FILTER : BUTTERWORTH IInd ORDER HPF 3. DIFFERNTIAL AMPLIFIER 4. ASTABLE MULTIVIBRATOR 5. CMOS INVERTER 6. CMOS NOR 7. CMOS NAND
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Page 1
EX.NO: DATE:
AIM:
CURRENT SERIES FEEDBACK AMPLIFIER
To study the frequency response of current series amplifier with and without feedback
APPARATUS REQUIRED:
Sl. No.
Apparatus
Range
Quantity
THEORY:
An amplifier whose fraction of output is fed back to the input is called feedback amplifier. A feedback amplifier consists of two parts namely amplifier circuit and feedback circuit. Depending upon whether the feedback signal increases or decreases the input signal it is classified into two i. Positive Feedback If the feedback signal is in phase with the input signal .ii Negative feedback If the feedback signal is out of phase with the input signal. The positive feedback increases the gain of the amplifier whereas the negative feedback decreases the gain. In the current series feedback connection a fraction of the output current is converted into a proportional voltage by the feedback network and then applied in series with the input.
DESIGN:
Vcc=10V, Ic=2mA, =200, Vce=Vcc/2=10/2=5V. Ve=Vcc/10=10/10=1V. Re=Ve/Ie=1/2m=500560 Vrc = Vcc-Vce-Ve = 10-5-1 = 4V. Rc = Vrc/Ic=4/2m=2K2.2k
To find R1 & R2 VB = VBE + VE 0.7 + 1 VB = 1.7V w.k.t I1 = 10 IB
Page 2
IB = I1 / 10 IC = IB IC = I1 / 10 IE = I1 / 10 (IC = IE ) From the ckt I1 = VE / R2 IE = VE / 10R2 R2 = VE / 10 IE R2 = RE / 10 R2 = 10K VB = R2Vcc / R1 + R2 1.7 = 10 x 103 x 10 / R1 + 10 x 103 1.7 R1 + 17 x 103 = 100 x 103 R1 = 48.82K R1 = 47K
PROCEDURE :
The connections are done as shown in the diagram. The input voltage is set to a fixed value. Vary the frequency and note down the output voltage. Repeat the same with feedback. Calculate the gain and plot the graph.
PIN DIAGRAM:
Collector Base BC107
Emitter
Page 3
CIRCUIT DIAGRAM:
With Feedback:
+10V R1 47K 2.2K
0.1uF
0.1uF Vin CRO R2 10K
BC107 CRO
560
Without Feedback:
+10V R1 47K 2.2K
0.1uF
0.1uF Vin CRO R2 10K 560
BC107 CRO
100uF
MODEL GRAPH
Gain (in dB)
Without feedback
With Feedback
Frequency (in Hz)
Page 4
Tabulation: With feedback Vi =
S.No FREQUENCY in Hz OUTPUT VOLTAGE GAIN = 20 log(Vo/Vi)in db Vo in volts
Tabulation:
Without feedback Vi =
RESULT:
Page 5
EX.NO: DATE:
AIM:
VOLTAGE SHUNT FEEDBACK AMPLIFIER
To study the frequency response of voltage shunt feedback amplifier with and without feedback
APPARATUS REQUIRED:
Sl. No.
Apparatus
Range
Quantity
THEORY:
An amplifier whose fraction of output is fed back to the input is called feedback amplifier. A feedback amplifier consists of two parts namely amplifier circuit and feedback circuit. Depending upon whether the feedback signal increases or decreases the input signal it is classified into two i. Positive Feedback If the feedback signal is in phase with the input signal .ii Negative feedback If the feedback signal is out of phase with the input signal. The positive feedback increases the gain of the amplifier whereas the negative feedback decreases the gain. In the voltage shunt feedback connection a fraction of the output voltage is applied in parallel with the input voltage through the feedback network The voltage shunt feedback connection decreases both input and output resistances of the feedback amplifier by a factor equal to (1+ Av)
DESIGN:
RC = 2.5K, R = 1.8K, RF = 10K RC= RC RF / (RC + RF) = RC RF / ( RF - RC) = 2.5K*10K/(10K-2.5K) RC = 3.3K R = RC RC /( RC + RC) R RS + R RF = RS RF RC = R RF /( RF - R ) = 1.8K*10K/(10K-1.8K) Rs=2.2K
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PIN DIAGRAM:
Emitter
CIRCUIT DIAGRAM:
With Feedback
+10V
Rc Rf 10K Q1 0.01uF Vin CRO 2.2K
3.3K
0.01uF
BC107
CRO
Page 7
WithoutFeedback:
+10V
Rc
3.3K
0.01uF Q1 0.01uF Vin CRO 2.2K
BC107
CRO
MODEL GRAPH
Gain (in dB)
Without feedback
With Feedback
Frequency (in Hz)
Page 8
Tabulation: With feedback Vi =
Tabulation: Without feedback
Vi =
Page 9
PROCEDURE
: The connections are done as shown in the diagram. The input voltage is set to a fixed value. Vary the frequency and note down the output voltage. Repeat the same with feedback. Calculate the gain and plot the graph.
RESULT :
Page 10
Ex.No: Date:
AIM:
RC PHASE SHIFT OSCILLATOR
To design and construct a RC phase shift oscillator to generate a sine wave of a frequency f = 1.98 KHz.
APPARATUS REQUIRED:
Sl. No.
Apparatus
Range
Quantity
THEORY:
Oscillator is a feed back circuit where a fraction of output voltage of an amplifier is fed back to the input in the same phase. RC phase shift oscillators are a sine wave oscillator which is used in the audio frequency range. It has a CE amplifier ,which provides 180.phase shift to the input signal and three frequency selective RC phase shift networks provides a phase shift of 60of each , a total of 180 for a signal with frequency equal to specific value, which corresponds to the output of the oscillator. Thus the total phase shift between the input and output is360. The frequency of oscillation is given by f = 1/( 2 RC (6+4K) )
DESIGN:
VCC = 20 V IE = 2mA, hfe = 100 VCE = VCC /2 = 10 V VE = VCC /10 = 2 V RE = VE / IE = VE / IC 2/2m RE = 1K RC = Vcc Vce Ve / Ic RC = 20 10 2 / 2 x 10-3 RC = 4K
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To find R1 & R2 VB = VBE + VE 0.7 + 2 VB = 2.7V w.k.t I1 = 10 IB IB = I1 / 10 IC = IB IC = I1 / 10 IE = I1 / 10 (IC = IE ) From the ckt I1 = VE / R2 IE = VE / 10R2 R2 = VE / 10 IE R2 = RE / 10 R2 = 10K VB = R2Vcc / R1 + R2 2.7 = 10 x 103 x 20 / R1 + 10 x 103 2.7 R1 + 27 x 103 = 200 x 103 R1 = 64K
Frequency: F = 1/(2RC)*1/((6+4(RC +R)) From circuit, R = 2.2K, C = 0.01F F = 1/(2*2.2K*0.01*(6+4(4K/2.2K)) = 1.98 KHz.
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PIN DIAGRAM:
Emitter
CIRCUIT DIAGRAM:
+20V
R1
69K
4K Vo 0.01uF
0.01uF
BC109
0.01uF 2.2K
0.01uF 2.2K
0.01uF 2.2K
R2
10K 1K 0.4uF
MODEL GRAPH
amplitude in volts
t in ms www.Vidyarthiplus.com Page 13
OBSERVATION
Amplitude in volts Time period (ms) (T) Frequency in Hz ( f= 1/ T)
PROCEDURE:
1. The connection is made as per the circuit diagram. 2. Set the RPS to 20Volts. 3. Observe the output and measure the time period of the output waveform Vo , determine the frequency and trace it 4. Plot the output on a graph sheet. 5. Compare the experimental value with the theoretical value of output frequency.
RESULT:
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Ex.NO: Date: HARTLEY OSCILLATOR
AIM: To design a Hartley oscillator and to generate a sine wave of a frequency of 4.59 KHz. APPARATUS REQUIRED:
Sl. No.
Apparatus
Range
Quantity
THEORY:
It is a sinusoidal oscillator which uses a single tapped coil having two parts named L1 and L2.The tank circuit also includes a capacitor. The centre point of L1 and L2 is grounded. They are inductively coupled and form an auto transformer or a split tank inductor. Feedback between the input and output circuit is accomplished through the autotransformer action which gives 180 phase shift .The transistor introduces 180 phase shift, therefore the total phase shift is 360 and hence the feedback is positive or regenerative. In The circuit R1 and R2 form a voltage divider for providing base bias and RE is an emitter swamping resistor to add stability to the circuit. When Vcc is applied, an initial bias is established by R1 and R2 and oscillations are produced because of positive feedback from the LC tank circuit.
DESIGN:
Vcc = 10 V :Ie = 1mA., hfe = 200, Vce = Vcc/2 = 5 V Ve = Vcc/10 = 1 V :Re = Ve/Ie = 2/2m :Re = 1K Rc = Vcc Vce Ve / Ic = 10 5 1 / 1 x 10-3 Rc = 4K
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Frequency: L1 = L2 = 60mH, C = 0.01F F = 1/(2(LC)) L = L1+L2 = 0.12H F = 1/(2(0.12*0.01)) = 4.59 KHz
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PIN DIAGRAM:
BC148
CBE
CIRCUIT DIAGRAM:
+10V 10K R1 83K Vo
0.03uF 60mH 0.01uF BC148
0.01uF R2 22K 1K 22uF 60mH
MODEL GRAPH
amplitude in volts
Page 17
T in ms
OBSERVATION
PROCEDURE:
1. The connection is made as per the circuit diagram. 2. Set the RPS to 10Volts. 3. Observe the output and measure the time period of the output waveform Vo , determine the frequency and trace it 4. Plot the output on a graph sheet. 5. Compare the experimental value with the theoretical value of output frequency.
RESULT:
Page 18
Ex.No: Date: COLPITTS OSCILLATOR
AIM: To design an Colpitts oscillator to generate a sine wave of a frequency 9.188 KHz. APPARATUS REQUIRED:
THEORY:
A colpitts oscillator is to generate sine wave in the frequency range 1500Mhz.It uses a LC tuned circuit with a CE amplifier to obtain oscillations. The feedback consists of two capacitors C1 and C2 and an inductor L.The Resistors R1 , R2 and RE provide dc bias to the transistor. The feedback between the output and input circuit is accomplished by the voltage developed across the capacitor C2 Feedback between the input and output circuit is 180 phase shift .The transistor introduces 180 phase shift, therefore the total phase shift is 360 and hence the feedback is positive or regenerative. When Vcc is applied, an initial bias is established by R1 and R2 , the capacitors C1 and C2 are charged . The capacitors discharge through the coil(L) which sets up the frequency of oscillations f = 1/( 2 (L Ceq))where Ceq= C1 C2 / C1+ C2.The oscillations across the capacitor C2 is fed back to the base-emitter junction and appear in an amplified form at the collector.
DESIGN:
Vcc = 10 V :Ie = 1mA., hfe = 200, Vce = Vcc/2 = 5 V Ve = Vcc/10 = 1 V :Re = Ve/Ie = 2/2m :Re = 1K Rc = Vcc Vce Ve / Ic = 10 5 1 / 1 x 10-3 Rc = 4K
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Frequency: L = 60mH, C1 = C2 = 0.01F F = 1/(2(LC)) C = C1C2/(C1+C2) = (0.01)2 /(0.01+0.01) = 5nF F = 1/(2(60m*5n)) = 9.188 KHz
PIN DIAGRAM
BC148
CBE
PROCEDURE:
1. The connection is made as per the circuit diagram. 2. Set the RPS to 10Volts. 3.Observe the output and measure the time period of the output waveform Vo , determine the frequency and trace it 4. Plot the output on a graph sheet. 5. Compare the experimental value with the theoretical value of output frequency.
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CIRCUIT DIAGRAM:
+10V R1 100K Rc 4K C2 0.01uF BC148 0.01uF 0.01uF C1 R2 22K Re 1K Ce 22uF L 60mH
0.1uF Vo
MODEL GRAPH
amplitude in volts
T in ms
OBSERVATION
RESULT:
Page 21
Ex.No: Date:
AIM
COLLECTOR COUPLED ASTABLE MULTIVIBRATOR
: To design an astable multivibrator and to obtain the output waveform for a frequency of 7.24KHz.
APPARATUS REQUIRED:
Sl. No.
Apparatus
Range
Quantity
THEORY:
The Astable multivibrator has 2 Quasi-states. And theyre unstable. Without any external trigger, the multivibrator keeps on alternating in states. The frequency of the oscillations are determined by the values of R and C used in the circuit.Astable multivibrator is also called as free running oscillator.as soon as we switch on the power supply any one of the transistor is turned on, since both the transistors are not identical.there will be voltage drop on the collector of that transistor, which is taken as an input to the second transistor.the second transistor is connected to the collector of the first transistor .Hence the second transistor turns on now.this process repeats, finally we get a square wave as an output.
DESIGN:
Vcc = 10 V Ic = 12 mA = 20 Re = 250 Ic = Ie = 12mA Ve = IeRe = 12m * 250 = 3 V Ib = Ic/ = 0.6 mA Rb = (Vcc Vbe Ve)/Ib = (10 - 0.7 3)/0.6m = 10.5 K Frequency: F = 1/(1.38RC) From Circuit, R = 10 K C = 0.01F www.Vidyarthiplus.com Page 22
F = 1/(1.38*10K*0.01) = 7.24 KHz MODEL GRAPH:
Amplitude (in volts)
Period (in us)
PIN DIAGRAM:
Emitter
CIRCUIT DIAGRAM:
+10V 1k 10K 10K Vo 0. 01uF 0. 01uF 1K
BC 109
BC 109
Page 23
TABULATION: Amplitude (in volts) Time Period (in msec)
PROCEDURE: 1. Connections are given as per the circuit diagram. 2. Supply voltage is kept at 10V. 3. CRO connected at the output is adjusted and the square wave output is obtained. 4. The amplitude and time period (Ton and Toff) of the signal is noted. 5. The output waveform is plotted in a graph, taking Amplitude in Y-axis and Time period in X-axis. 6. Then the practical value of the frequency is calculated.
RESULT:
Page 24
Ex. No : Date:
AIM:
EMITTER COUPLED ASTABLE MULTIVIBRATOR
To design an emitter coupled astable multivibrator for a pulsewidth of 6.9S.
APPARATUS REQUIRED:
Sl. No.
Apparatus
Range
Quantity
THEORY:
Square wave outputs are generated when the OPAMP is forced to operate in the saturated region. That is, the out put of the OPAMP is forced to swing repetitively between positive saturation V sat and negative saturation Vsat, resulting in the square wave output. Astable multivibrator circuit is shown in figure. The output of the OPAMP in this circuit will be in positive or negative saturation, depending whether the differential voltage is positive or negative, respectively. The time period T of the out wave form is T = 2 RC ln ( (1+)/(1-)) =R2/(R1+R2) If R1 = 1.16 R2 T = 2RC Frequency = 1/(2RC)
DESIGN SPECIFICATION:
PW = 6.9s, , Vcc = 5 V, hfe = 50 Rc = Vcc/Ic = 2.2K Re = Vcc/2Ic = 1.2K Ib = Ic/ hfe = 40A Rb = (Vcc Vbe )/Ib = 100K PW = 0.69RbC 6.21= 0.69*150*C C = 6.9/(0.69*100K) = 100pF
Page 25
PIN DIAGRAM:
Emitter
CIRCUIT DIAGRAM:
+5V
2.2K 100K 100K
2.2K
Vo 100pF 100pF
BC107
BC107
Re 1.2K
Page 26
MODEL GRAPH
Period (in us)
TABULATION: Amplitude (in volts) Time Period (in msec) TON (ms) TOFF (ms)
PROCEDURE: i. Connect the circuit shown in figure using component values as obtained in design. ii. Observe and sketch the capacitor voltage wave form and output wave form. iii. Determine the frequency.
RESULT :
Page 27
Ex.No: Date:
AIM:
MONOSTABLE MULTIVIBRATOR
To design, construct and test a monostable multivibrator.
APPARATUS REQUIRED:
Sl. No.
Apparatus
Range
Quantity
THEORY:
Monostable Multivibrator is also called as one shot Multivibrator and can be used to generate a gating pulse, whose width can be controlled. The Monostable Multivibrator provides a single pulse of desired duration in response to an external trigger. The external trigger cases the circuit to go to a Quasi-stable state. After a certain interval, the circuit comes to stable state. The width or duration of the pulse is obtained at the collector or ouput of either transistor of the Monostable Multivibrator, is given by the expression, tp = 0.69 R3 C1 seconds.
DESIGN SPECIFICATIONS :
PW = 6.21s, R = 150, Vcc = 5 V, hfe = 10 Ic = 3 mA, Vcesat = 0.2 V PW = 0.69RC 6.21= 0.69*150*C C = 0.06F Rc2 = (Vcc Vd - Vcesat)/Ic = (5 0.7 0.2)/3m = 1.366K 1K Rc1 = Rc2 = 1K Ib2 = Ic/ hfe = 300A Rb2 = (Vcc Vbe - Vdt)/Ib2 = 12K Frequency: F = 1/(2*pulse width) = 1/(2*6.21) = 80 KHz www.Vidyarthiplus.com Page 28
CIRCUIT DIAGRAM
+5V
1K 1N4007 FG 1K 150 0.06uF BC107
22K
1K Vo
12K
BC107
MODEL GRAPH
Period (in us)
Page 29
TABULATION
Pulse width (in msec)
PROCEDURE : 1. The connection is made as per the circuit diagram. 2. Apply a negative going pulse as the input signal. 3. Observe the output voltage across the capacitor Vc and the output waveform Vo and trace it.
RESULT :
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Ex.No: Date:
AIM:
CLASS C TUNED AMPLIFIER
To design construct and test a Class C tuned amplifier for a tuning frequency of 7KHz.
APPARATUS REQUIRED
Sl. No.
Apparatus
Range
Quantity
THEORY:
Tuned amplifier is used to amplify the input signal at the tuned frequency only. The input signal other than tuning frequency are attenuated . The class C amplifier is developed to make the circuit operate only for portion of input signal , I,e less than 90 degrees. The Class C amplifier works on the principle of tuning the parallel RLC resonant circuit to tuning frequency. The value of Lc decide the tuning frequency and is related as f= (1/ (2 (Lc))). The values of LC are chosen for the required tuning frequency interval. During the remaining period the Q is in cut-off region and no current flows through its collector. The energy in the tank circuit supplies the load current through capacitor. Once the input signal frequency is out of the tuning frequency, the oscillation in the tank circuit cannot be sustained. Thus the circuit attenuates input signals other than tuning frequency.
DESIGN:
Fr = 1/ 2LC , fr = 7KHz Let C= .001F, then L = 1/((2 ftune)^2*C) L = 1/((2*3.14*7*10^3)^2*0.001*10^-6) ; L = 516mH

PROCEDURE:
1. Connections are made as shown in the circuit diagram. 2. Input signal is set at 6MHz , 1V peak is given and the corresponding output is noted from the CRO 3. Observe the output and measure the time period and amplitude of the output waveform Vo , determine the frequency and trace it www.Vidyarthiplus.com Page 31
4. Obtain the tuning frequency from the plot of the frequency response..
CIRCUIT DIAGRAM:
+10V
0.001f
516mH
0.01uF
0.01uF Vin CRO R2 4.7K
BC107 CRO
OBSERVATION:
Vi =
MODEL GRAPH:
RESULT:
Page 32
Ex.No: Date:
AIM:
INTEGRATOR ,DIFFERENTIATOR , CLIPPERS AND CLAMPERS
To construct and test integrator ,differentiator, clippers and clampers circuit and to obtain the output waveform.
APPARATUS REQUUIRED:
Sl. No.
Apparatus
Range
Quantity
THEORY:
INTEGRATOR :
The circuit performs the mathematical operation of integration, that is , the o/p waveform is the integral of the i/p waveform. The output voltage Vo (t) = - ( 1 / R C )vi(t) dt
DIFFERENTIATOR :
The circuit performs the mathematical operation of differentiation , that is , the o/p waveform is the derivative of the i/p waveform. The output voltage Vo(t) = - R C (dvi / dt)
CLIPPERS:
Clippers have the ability to clip off a portion of the input signal without distorting the remaining part of the alternating waveform.. The half wave recitifier is an example of the simplest form of diode clipper one resistor and diode. Depending upon the orientation of the diode , the positive or negative region of the input signal is clipped off. Clippers are of two : I . Series ii. Parallel Series configuration is defined as one where diode is in series with the load, while the parallel the diode is connected in parallel to the load.
CLAMPERS:
The clamping network is one that will clamp a signal to different dc level. The circuit has a diode, resistor and a capacitive element, but it can also employ an independent dc supply to introduce an additional shift. The magnitude of R and C must be chosen that the www.Vidyarthiplus.com Page 33
time constant = RC is large enough that the voltage across the capacitor does not discharge significantly during the interval diode is nonconducting.
PROCEDURE:
(i)Connect the differentiator circuit. Adjust the signal generator to produce a 1V peak a. sine wave at 100Hz. b. square wave at 100 Hz (ii) Observe i/p and o/p waveform on the oscilloscope .Measure and record the peak value of Vo and the phase angle of Vo w.r.t Vi. (iii) Connect the integrator circuit Adjust the signal generator to produce a 1V peak a. sine wave at 5kHz. b. square wave at 5kHz iv.Observe and record the input and the output waveforms.
CIRCUIT DIAGRAM
Page 34
Tabulation Differentiator Amplitude Time period in V (ms) Input Output
Integrator Amplitude Time period in V (ms) Input Output
CLIPPERS Positive Clipper:
560 FG 1N4007 Vo
Negative Clipper:
Page 35
560 FG 1N4007 Vo
Tabulation Positive Clipper: Amplitude Time Period (in volts) (in msec) Input Output
Negative Clipper: Amplitude (in volts) Input Output Time Period (in msec)
CLAMPERS Positive Clamper:

1uF FG 1N4007 Vo
Negative Clamper:
1uF FG 1N4007 Vo
Clampers:
Input Signal:
Clippers:
Input Signal:
Page 36
Positive Clamped Output:
Negative Clipped Output:
Negative Clamped Output:
Positive Clipped Output:
Tabulation Positive Clamper: Amplitude (in volts) Input Output Period (in sec)
Negative Clamper: Amplitude (in volts) Input Output Period (in sec)
Page 37
RESULT:
SIMULATION USING PSPICE
Ex.No:
SECOND ORDER LOW PASS FILTER
AIM:
To plot the frequency response of active second order low pass filter using OP-AMP in Pspice.
SIMULATOR:
Pspice simulator.
THEORY:
An improved filter response can be obtained by using a second order active filter consist of two RC pairs. It has a rool-off rate of -40dB/decade. The transfer function of a low pass filter is H(s) = AoH2
S2 + HS + H2 www.Vidyarthiplus.com Page 38
For n=2, the clamping factor =1.414,the pass band gain ,Ao=3-=1.586. Cut-off frequency of the filter =1/2RC.
DESIGN:
f=1KHz Assume C=0.1 F, R=1.6K. Ao=1+Rf /Ri => Rf /Ri=0.586. Let Rf = 5.86 K., Ri =10 K.
NETLIST:
LOW PASS FILTER
V1 V2 V3 1 6 7 2 1 3 4 3 0 0 0 3 4 7 6 4 AC DC DC 5.8K 10K 1.6K 1.6K 6 7 5 UA741 1V +15V -15V
Rf Ri
R3 R4 X LIB AC
DEC
10
100
3K
PROBE END
CIRCUIT DIAGRAM:
Page 39
RESULT:
Thus, the frequency response of active second order low pass filter was plotted.
ACTIVE HIGH PASS FILTER. Date:

AIM :
To design and simulate a second order Low pass filter using Op-amp and to obtain the frequency response and roll off rate. Mark the each node with a number. Enter each component between nodes. Call the UA 741 Op-amp from the .NOM library. Use the .AC statement to vary the frequency. Observe the frequency response of the filter. Calculate the Roll-off rate
ALGORITHM:
1. 2. 3. 4. 5. 6.
DESIGN:
Gain = Af =3-2K www.Vidyarthiplus.com Page 40
K= damping factor= coefficient of s/2 = 1.414/2 = 0.707 Af = 3-2(0.707) = 1.586 Af= 1+ (Rf +R1) = 1.586 Choose Rf/R1 = 0.586, Let R1= 1K, Rf= Fh= upper 3db frequency = 1/(2*pi*( R2 * R3 * C2*C3)^(1/2) Let R2 = R3 = R =1K ohms, C= 0.79micro farads
CIRCUIT DIAGRAM:
PROGRAM:
Vcc 4 0 DC 12V VEE 0 7 DC 12V Vin 1 0 AC 1V R1 4 0 1K R2 1 2 1K R3 2 3 1K Rf 4 5 0.586K C2 2 5 0.79uf C3 3 0 0.79uf X1 4 3 5 0 OPAMP .subckt OPAMP 1 2 5 4 RI 1 2 2 MEG Ro 3 5 7 5 EA 3 4 2 1 2E+5 .ends OPAMP .AC DEC 10Hz 100Hz 1 MEGHz .probe .end
Page 41
RESULT:
The program for an active low pass filter is written and executed successfully
Ex.No: Date :
ASTABLE MULTIVIBRATOR
AIM : To simulate an astable multivibrator. ALGORITHM:
1. Mark the each node with a number. 2. Enter each component between nodes 3. Simulate the circuit using PSPICE. 4. Use the .PLOT TRAN function to obtain the graph. 5.Use the .TRAN function to obtain the transient function. CIRCUIT DIAGRAM: www.Vidyarthiplus.com Page 42
+10V
1k 10K 10K
1K
Vo 0.01uF 0.01uF
BC109
BC109
PROGRAM Vcc 6 0 DC 5V Rc1 6 1 1K Rc2 6 2 1K R1 6 3 30K R2 6 4 30K C1 1 4 150Pf C2 2 3 150Pf Q1 1 3 0 QN Q2 2 4 0 QN .model QN NPN ( IS = 2E-16 BF = 50 BR = 1 RB = 5 RC = 1 RE = 0 TF = .2ns TR = 5ns) .nodeset V(1) =0 V(3) =0 .TRAN / OP 0.1us 10us www.Vidyarthiplus.com Page 43
.options ABSTOL = 1.0N REILTOL = 10M VNTOL = 1M ITL5 = 40 000 .probe .end
RESULT: The program for an astable multivibrator is written and executed successfully
CMOS INVERTOR
AIM:
To plot the transient response of the output signal of the CMOS INVERTOR circuit from 0ms to 50ms in steps of 1ms using Pspice.
SIMULATOR:
Pspice simulator.
Page 44
THEORY:
CMOS circuits
take the advantage of the fact that both N-channel and P-
channel devices can be fabricated on the same substrate. The basic CMOS circuit is the invertor which consist of one P-channel and one N-channel transistor. The source terminal of the P-channel is at VDD and source terminal of N-channel device is at ground. When the input is low, both gates are at zero potential. The input is at VDD relative to the source of the P-channel device and at 0V relative to the source of the
N-channel
device. The result is that the P-channel device is under these conditions,
there is a low impedance path from VDD to the output and a very high impedance from output to ground. Therefore, the output voltage goes to high level , VDD under normal loading conditions. When the input is high both gates are at VDD and the situation is reversed. The P-channel device is turned OFF and N-channel is turned ON. The result is that the output approaches low level of 0V.
NETLIST:
CMOS INVERTOR
VDD VIN M1 M2 TRAN PROBE 1 1 3 0 0 2 PMOD 2 NMOD 1M 50M 0 DC 5V 5V PMOD 0 1N 1N 5M 10M ) PULSE ( 0 1 1 PMOS 0 NMOS NMOD
MODEL 3
MODEL
Page 45
END
CIRCUIT DIAGRAM:
Page 46
TRUTH TABLE:
INPUT A 0 1
OUTPUT Y=A 1 0
RESULT:
Thus, the transient response of the output signal for 0to 50ms in steps of 1ms was plotted.
CMOS NAND
www.Vidyarthiplus.com Page 47
AIM:
To plot the transient response of the output signal of the CMOS NAND circuit from 0ms to 50ms in steps of 1ms using Pspice.
SIMULATOR:
Pspice simulator.
THEORY:
CMOS circuits take the advantage of the fact that both N-channel and P-
channel devices can be fabricated on the same substrate. CMOS circuits consists of both types of MOS devices, interconnected to form logic functions. Another CMOS basic gate is the NAND gate which consists of two P-type units in parallel and two N-type units in series as shown in circuit. If all inputs are high, both P-type transistors are turned OFF and both N-channel transistors are turned
ON. The output has low impedance to the ground and produces a low state. If any
input is low, the associated N-channel transistor is turned OFF and the associated Pchannel transistor is turned ON. The output is coupled to VDD and goes to high state. If both the inputs are low, the P-type transistor are turned ON and both the Nchannel transistor are turned OFF. The output has a high impedance to the ground and produces a high state. Multiple input NAND gates may be formed by placing equal number of P-type and N-type transistors in parallel and series respectively.
NETLIST:
CMOS NAND
VDD V1 V2 M1 1 3 2 5 0 0 0 2 DC 5V 5V 5V PMOD 0 0 1N 1N 5M 5M 10M ) 10M ) PULSE( 0 PULSE( 0 1 1
Page 48
M2 M3 M4 TRAN PROBE END 5 3 PMOD 3 2 NMOD 1M 50M 4 0 1 1 PMOS 4 0 NMOS NMOD NMOD PMOD
MODEL 5 4
MODEL
CIRCUIT DIAGRAM:
TRUTH TABLE:
INPUT A B OUTPUT Y=(AB)
0 0 1 1
0 1 0 1
1 1 1 0
RESULT:
CMOS NOR
AIM:
To plot the transient response of the output signal of the CMOS NOR circuit from 0ms to 50ms in steps of 1ms using Pspice.
SIMULATOR:
Pspice simulator.
THEORY:
CMOS circuits take the advantage of the fact that both N-channel and P-
channel devices can be fabricated on the same substrate. CMOS circuits consists of both types of MOS devices, interconnected to form logic functions. Another CMOS basic gate is the NOR gate which consists of two N-type units in parallel and two P-type units in series as shown in circuit. If all inputs are low, both P-type transistors are turned ON and both N-channel transistors are turned
OFF. The output is coupled to VDD and goes to high state. If any input is high, the
associated P-channel transistor is turned OFF and the associated N-channel transistor is turned ON, connecting the output to the ground and causing a low level output. If both the inputs are high, the P-channel units are turned OFF and both the
N-channel units are turned ON. The output goes to low state.
NETLIST:
CMOS NOR
VDD V1 V2 M1 M2 M3 M4 TRAN PROBE END 3 1 2 4 5 0 0 0 1 2 PMOD 1 2 NMOD 1M 50M 0 0 DC 5V 5V 5V PMOD PMOD 0 0 1N 1N 1N 1N 5M 5M 10M ) 10M ) PULSE ( 0 PULSE ( 0 3 4 3 4 PMOS 0 0 NMOS NMOD NMOD
MODEL 5 5
MODEL
CIRCUIT DIAGRAM:
TRUTH TABLE:
INPUT A B OUTPUT Y=(AB)
0 0 1 1
0 1 0 1
1 1 1 0
RESULT:
Page 53
www.Vidyarthiplus.com DIFFERENTIAL AMPLIFIER USING OP-AMP
AIM: To calculate the difference output using OP-AMP and to plot the transient response of output using Pspice.
SIMULATOR: Pspice simulator.
THEORY: A circuit that amplifier the difference between two signals is called as difference amplifier or differential amplifier. This type of amplifier is very useful in instrumentation circuits. The output voltage of the differential amplifier is given by Vo =R2/R 1 [V 1 V 2] Such a circuit is very useful in detecting even very small difference in the signals, since the gain R2/R 1 can be chosen to be very large. The main purpose of difference amplifier is to provide high gain to the difference mode signal and to cancel the common mode signal. The relative sensitivity of an OP-AMP to a difference signal as compared to a common mode signal is called common mode rejection ratio and gives the figure of merit of the differential amplifier.
Page 54
NETLIST:
DIFFERENTIAL AMPLIFIER
*V1 *V 2 V1 V2 V3 V4 R1 R2 R3 R4 X LIB TRAN PROBE END 1M 50M 2 2 1 2 5 6 2 1 3 4 4 0 0 0 0 0 0 3 4 7 6 3 DC DC 10V 5V 10V 5V 2K ) 2K )
SIN ( 0V SIN ( 0V DC DC 1K 1K 1K 1K 5 6 +15V -15V
UA741
Page 55
CIRCUIT DIAGRAM:
TRUTH TABLE:
ANALYSIS AC AC
V1 [Volts] 10 10
V2[Volts] 5 5
Vo =R2/R 1 [V 1 V 2] 5 10
RESULT:
Thus, the transient response of the difference output of a differential amplifier using OP-AMP was plotted.
Page 56

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SIMULATION USING PSPICE

CURRENT SERIES FEEDBACK AMPLIFIER

Collector Base BC107

0.1uF Vin CRO R2 10K

0.1uF Vin CRO R2 10K 560

Gain (in dB)

Frequency (in Hz)

S.No FREQUENCY in Hz OUTPUT VOLTAGE GAIN = 20 log(Vo/Vi)in db Vo in volts

S.No FREQUENCY in Hz OUTPUT VOLTAGE GAIN = 20 log(Vo/Vi)in db Vo in volts

VOLTAGE SHUNT FEEDBACK AMPLIFIER

Collector Base BC107

Rc Rf 10K Q1 0.01uF Vin CRO 2.2K

0.01uF Q1 0.01uF Vin CRO 2.2K

Gain (in dB)

Frequency (in Hz)

S.No FREQUENCY in Hz OUTPUT VOLTAGE GAIN = 20 log(Vo/Vi)in db Vo in volts

Tabulation: Without feedback

S.No FREQUENCY in Hz OUTPUT VOLTAGE GAIN = 20 log(Vo/Vi)in db Vo in volts

RC PHASE SHIFT OSCILLATOR

Collector Base BC109

Amplitude in volts Time period (ms) (T) Frequency in Hz ( f= 1/ T)

Frequency: L1 = L2 = 60mH, C = 0.01F F = 1/(2(LC)) L = L1+L2 = 0.12H F = 1/(2(0.12*0.01)) = 4.59 KHz

+10V 10K R1 83K Vo

0.03uF 60mH 0.01uF BC148

0.01uF R2 22K 1K 22uF 60mH

Amplitude in volts Time period (ms) (T) Frequency in Hz ( f= 1/ T)

Amplitude in volts Time period (ms) (T) Frequency in Hz ( f= 1/ T)

+10V R1 100K Rc 4K C2 0.01uF BC148 0.01uF 0.01uF C1 R2 22K Re 1K Ce 22uF L 60mH

Amplitude in volts Time period (ms) (T) Frequency in Hz ( f= 1/ T)

COLLECTOR COUPLED ASTABLE MULTIVIBRATOR

Period (in us)

Collector Base BC109

+10V 1k 10K 10K Vo 0. 01uF 0. 01uF 1K

TABULATION: Amplitude (in volts) Time Period (in msec)

EMITTER COUPLED ASTABLE MULTIVIBRATOR

To design an emitter coupled astable multivibrator for a pulsewidth of 6.9S.

Collector Base BC107

2.2K 100K 100K

Amplitude (in volts)

Period (in us)

To design, construct and test a monostable multivibrator.

1K 1N4007 FG 1K 150 0.06uF BC107

Amplitude (in volts)

Period (in us)

Amplitude (in volts)

Pulse width (in msec)

CLASS C TUNED AMPLIFIER

Fr = 1/ 2LC , fr = 7KHz Let C= .001F, then L = 1/((2 ftune)^2*C) L = 1/((2*3.14*7*10^3)^2*0.001*10^-6) ; L = 516mH

0.01uF Vin CRO R2 4.7K

S.No FREQUENCY in Hz OUTPUT VOLTAGE GAIN = 20 log(Vo/Vi)in db Vo in volts

INTEGRATOR ,DIFFERENTIATOR , CLIPPERS AND CLAMPERS

Tabulation Differentiator Amplitude Time period in V (ms) Input Output

Integrator Amplitude Time period in V (ms) Input Output

CLIPPERS Positive Clipper:

CLAMPERS Positive Clamper:

Positive Clamped Output:

Negative Clipped Output:

Negative Clamped Output:

Positive Clipped Output:

SIMULATION USING PSPICE

SECOND ORDER LOW PASS FILTER

ACTIVE HIGH PASS FILTER. Date:

Fr = 1/ 2LC , fr = 7KHz Let C= .001F, then L = 1/((2 ftune)^2C) L = 1/((23.14710^3)^20.00110^-6) ; L = 516mH