MSP 430 FG 4618

MSP430xG461x MIXED SIGNAL MICROCONTROLLER
SLAS508I APRIL 2006 REVISED MARCH 2011
D Low Supply-Voltage Range: 1.8 V to 3.6 V D Ultralow-Power Consumption:
D Universal Serial Communication Interface

Enhanced UART Supporting Auto-Baudrate Detection IrDA Encoder and Decoder Synchronous SPI I2CTM Serial Onboard Programming, Programmable Code Protection by Security Fuse Brownout Detector Basic Timer With Real Time Clock Feature Integrated LCD Driver up to 160 Segments With Regulated Charge Pump Family Members Include: MSP430xG4616: 92KB+256B Flash or ROM Memory 4KB RAM MSP430xG4617: 92KB+256B Flash or ROM Memory, 8KB RAM MSP430xG4618: 116KB+256B Flash or ROM Memory, 8KB RAM MSP430xG4619: 120KB+256B Flash or ROM Memory, 4KB RAM For Complete Module Descriptions, See the MSP430x4xx Family Users Guide (literature number SLAU056)
D D D D D D D D D D D D
Active Mode: 400 A at 1 MHz, 2.2 V Standby Mode: 1.3 A Off Mode (RAM Retention): 0.22 A Five Power-Saving Modes Wake-Up From Standby Mode in Less Than 6 s 16-Bit RISC Architecture, Extended Memory, 125-ns Instruction Cycle Time Three Channel Internal DMA 12-Bit A/D Converter With Internal Reference, Sample-and-Hold, and Autoscan Feature Three Configurable Operational Amplifiers Dual 12-Bit Digital-to-Analog (D/A) Converters With Synchronization 16-Bit Timer_A With Three Capture/Compare Registers 16-Bit Timer_B With Seven Capture/Compare-With-Shadow Registers On-Chip Comparator Supply Voltage Supervisor/Monitor With Programmable Level Detection Serial Communication Interface (USART1), Select Asynchronous UART or Synchronous SPI by Software
D D D D D
description
The Texas Instruments MSP430 family of ultralow-power microcontrollers consists of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low-power modes, is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 6 s. The MSP430xG461x series are microcontroller configurations with two 16-bit timers, a high-performance 12-bit A/D converter, dual 12-bit D/A converters, three configurable operational amplifiers, one universal serial communication interface (USCI), one universal synchronous/asynchronous communication interface (USART), DMA, 80 I/O pins, and a liquid crystal display (LCD) driver with regulated charge pump. Typical applications for this device include portable medical applications and e-meter applications.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. These devices have limited built-in ESD protection. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2011, Texas Instruments Incorporated
POST OFFICE BOX 655303
DALLAS, TEXAS 75265

AVAILABLE OPTIONS{ PACKAGED DEVICES} TA PLASTIC 100-PIN TQFP (PZ) MSP430FG4616IPZ MSP430FG4617IPZ MSP430FG4618IPZ 40 40C to 85C MSP430FG4619IPZ MSP430CG4616IPZ MSP430CG4617IPZ MSP430CG4618IPZ MSP430CG4619IPZ
PLASTIC 113-BALL BGA (ZQW) MSP430FG4616IZQW MSP430FG4617IZQW MSP430FG4618IZQW MSP430FG4619IZQW MSP430CG4616IZQW MSP430CG4617IZQW MSP430CG4618IZQW MSP430CG4619IZQW
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
DEVELOPMENT TOOL SUPPORT

All MSP430 microcontrollers include an Embedded Emulation Module (EEM) allowing advanced debugging and programming through easy-to-use development tools. Recommended hardware options include:
D Debugging and Programming Interface

MSP-FET430UIF (USB) MSP-FET430PIF (Parallel Port)
D Debugging and Programming Interface with Target Board

MSP-FET430U100 (for PZ package)
D Standalone Target Board

MSP-TS430PZ100 (for PZ package)
D Production Programmer
MSP-GANG430
DALLAS, TEXAS 75265

pin designation, MSP430xG461xIPZ

P1.3/TBOUTH/SVSOUT P1.4/TBCLK/SMCLK P1.5/TACLK/ACLK P1.6/CA0 P1.7/CA1
TDI/TCLK TDO/TDI XT2IN XT2OUT P1.0/TA0 P1.1/TA0/MCLK P1.2/TA1
P6.2/A2/OA0I1 P6.1/A1/OA0O P6.0/A0/OA0I0 RST/NMI TCK TMS
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83
AVCC DV SS1 AVSS
DVCC1 P6.3/A3/OA1O P6.4/A4/OA1I0 P6.5/A5/OA2O P6.6/A6/DAC0/OA2I0 P6.7/A7/DAC1/SVSIN VREF+ XIN XOUT VeREF+/DAC0 VREF/VeREF P5.1/S0/A12/DAC1 P5.0/S1/A13/OA1I1 P10.7/S2/A14/OA2I1 P10.6/S3/A15 P10.5/S4 P10.4/S5 P10.3/S6 P10.2/S7 P10.1/S8 P10.0/S9 P9.7/S10 P9.6/S11 P9.5/S12 P9.4/S13
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
P2.0/TA2 P2.1/TB0 P2.2/TB1
P2.3/TB2
MSP430xG4616IPZ MSP430xG4617IPZ MSP430xG4618IPZ MSP430xG4619IPZ
P2.4/UCA0TXD P2.5/UCA0RXD P2.6/CAOUT P2.7/ADC12CLK/DMAE0 P3.0/UCB0STE P3.1/UCB0SIMO/UCB0SDA P3.2/UCB0SOMI/UCB0SCL P3.3/UCB0CLK P3.4/TB3 P3.5/TB4 P3.6/TB5 P3.7/TB6 P4.0/UTXD1 P4.1/URXD1 DVSS2 DVCC2 LCDCAP/R33 P5.7/R23 P5.6/LCDREF/R13 P5.5/R03 P5.4/COM3 P5.3/COM2 P5.2/COM1 COM0 P4.2/STE1/S39
P8.1/S24 P8.0/S25 P7.7/S26 P7.6/S27 P7.5/S28 P7.4/S29 P7.3/UCA0CLK/S30 P7.2/UCA0SOMI/S31 P7.1/UCA0SIMO/S32 P7.0/UCA0STE/S33 P4.7/UCA0RXD/S34 P4.6/UCA0TXD/S35 P4.5/UCLK1/S36 P4.4/SOMI1/S37 P4.3/SIMO1/S38
P9.3/S14 P9,2/S15 P9.1/S16 P9.0/S17 P8.7/S18 P8.6/S19
P8.5/S20 P8.4/S21 P8.3/S22 P8.2/S23
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
DALLAS, TEXAS 75265

pin designation, MSP430xG461xIZQW (top view)
A B C D E F G H J K L M
10
11
12
NOTE: For terminal assignments, see the MSP430xG461x Terminal Functions table.
DALLAS, TEXAS 75265

functional block diagram

XIN/ XT2IN XOUT / XT2OUT 2 2 DVCC1/2 DVSS 1/2 AVCC AVSS P1.x/P2.x 2x8 P3.x/P4.x P5.x/P6.x 4x8 P7.x/P8.x P9.x/P10.x 4x8/2x16
Oscillators FLL+ MCLK
ACLK SMCLK
Flash (FG) ROM (CG) 120kB 116kB 92kB 92kB
RAM 4kB 8kB 8kB 4kB
ADC12 12 Bit 12 Channels
DAC12 12 Bit 2 Channels Voltage out
OA0, OA1, OA2 3 Op Amps
Ports P1/P2 Comparator _A 2x8 I/O Interrupt capability
Ports P3/P4 P5/P6 4x8 I/O
Ports P7/P8 P9/P10 4x8/2x16 I/O
8MHz CPUX incl. 16 Registers
MAB
DMA Controller 3 Channels
MDB
Enhanced Emulation (FG only ) JTAG Interface
Brownout Protection SVS /SVM
Hardware Multiplier MPY, MPYS , MAC, MACS
Timer_B7 Watchdog WDT+ 15/16 Bit Timer_A3 3 CC Registers 7 CC Registers , Shadow Reg Basic Timer & Real Time Clock
LCD_A 160 Segments 1,2,3,4 Mux
USCI_A0: UART , IrDA, SPI USCI_B0: SPI, I2C
USART 1 UART, SPI
RST/NMI
DALLAS, TEXAS 75265

Terminal Functions
TERMINAL NAME DVCC1 P6.3/A3/OA1O P6.4/A4/OA1I0 P6.5/A5/OA2O P6.6/A6/DAC0/OA2I0 NO. PZ 1 2 3 4 5 NO. ZQW A1 B1 B2 C2 C1 C3 D2 D1 E1 E2 E4 F1 F2 E5 G1 G2 F4 H1 H2 F5 J1 J2 G4 K1 L1 M2 K2 L3 M3 H4 L4 M4 G5 L5 I/O I/O I/O I/O I/O DESCRIPTION Digital supply voltage, positive terminal General-purpose digital I/O / analog input a312-bit ADC / OA1 output General-purpose digital I/O / analog input a412-bit ADC / OA1 input multiplexer on +terminal and terminal General-purpose digital I/O / analog input a512-bit ADC / OA2 output General-purpose digital I/O / analog input a612-bit ADC / DAC12.0 output / OA2 input multiplexer on +terminal and terminal General-purpose digital I/O / analog input a712-bit ADC / DAC12.1 output / analog input to brownout, supply voltage supervisor Output of positive terminal of the reference voltage in the ADC Input port for crystal oscillator XT1. Standard or watch crystals can be connected. Output terminal of crystal oscillator XT1 Input for an external reference voltage to the ADC / DAC12.0 output Negative terminal for the ADC reference voltage for both sources, the internal reference voltage, or an external applied reference voltage General-purpose digital I/O / LCD segment output 0 / analog input a12 12bit ADC / DAC12.1 output General-purpose digital I/O / LCD segment output 1 / analog input a13 12bit ADC/OA1 input multiplexer on +terminal and terminal General-purpose digital I/O / LCD segment output 2 / analog input a14 12bit ADC/OA2 input multiplexer on +terminal and terminal General-purpose digital I/O / LCD segment output 3 / analog input a15 12bit ADC General-purpose digital I/O / LCD segment output 4 General-purpose digital I/O / LCD segment output 5 General-purpose digital I/O / LCD segment output 6 General-purpose digital I/O / LCD segment output 7 General-purpose digital I/O / LCD segment output 8 General-purpose digital I/O / LCD segment output 9 General-purpose digital I/O / LCD segment output 10 General-purpose digital I/O / LCD segment output 11 General-purpose digital I/O / LCD segment output 12 General-purpose digital I/O / LCD segment output 13 General-purpose digital I/O / LCD segment output 14 General-purpose digital I/O / LCD segment output 15 General-purpose digital I/O / LCD segment output 16 General-purpose digital I/O / LCD segment output 17 General-purpose digital I/O / LCD segment output 18 General-purpose digital I/O / LCD segment output 19 General-purpose digital I/O / LCD segment output 20 General-purpose digital I/O / LCD segment output 21 General-purpose digital I/O / LCD segment output 22
P6.7/A7/DAC1/SVSIN VREF+ XIN XOUT VeREF+/DAC0 VREF/VeREF P5.1/S0/A12/DAC1 (see Note 1) P5.0/S1/A13/OA1I1 (see Note 1) P10.7/S2/A14/OA2I1 (see Note 1) P10.6/S3/A15 (see Note 1) P10.5/S4 P10.4/S5 P10.3/S6 P10.2/S7 P10.1/S8 P10.0/S9 P9.7/S10 P9.6/S11 P9.5/S12 P9.4/S13 P9.3/S14 P9.2/S15 P9.1/S16 P9.0/S17 P8.7/S18 P8.6/S19 P8.5/S20 P8.4/S21 P8.3/S22
6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
I/O O I O I/O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
NOTES: 1. Segments S0 through S3 are disabled when the LCD charge pump feature is enabled (LCDCPEN = 1) and cannot be used together with the LCD charge pump. In addition, when using segments S0 through S3 with an external LCD voltage supply, VLCD AVCC.
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Terminal Functions (Continued)

TERMINAL NAME P8.2/S23 P8.1/S24 P8.0/S25 P7.7/S26 P7.6/S27 P7.5/S28 P7.4/S29 P7.3/UCA0CLK/S30 P7.2/UCA0SOMI/S31 P7.1/UCA0SIMO/S32 P7.0/UCA0STE/S33 P4.7/UCA0RXD/S34 P4.6/UCA0TXD/S35 P4.5/UCLK1/S36 P4.4/SOMI1/S37 P4.3/SIMO1/S38 P4.2/STE1/S39 COM0 P5.2/COM1 P5.3/COM2 P5.4/COM3 P5.5/R03 P5.6/LCDREF/R13 P5.7/R23 LCDCAP/R33 DVCC2 DVSS2 P4.1/URXD1 P4.0/UTXD1 P3.7/TB6 P3.6/TB5 P3.5/TB4 NO. PZ 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 NO. ZQW M5 H5 J5 M6 L6 J6 M7 H6 L7 M8 L8 J7 M9 L9 H7 M10 M11 L10 L12 J8 K12 K11 J12 J11 H11 H12 G12 G11 H9 F12 F11 G9 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O I/O I/O I/O I/O I/O I/O I DESCRIPTION General-purpose digital I/O / LCD segment output 23 General-purpose digital I/O / LCD segment output 24 General-purpose digital I/O / LCD segment output 25 General-purpose digital I/O / LCD segment output 26 General-purpose digital I/O / LCD segment output 27 General-purpose digital I/O / LCD segment output 28 General-purpose digital I/O / LCD segment output 29 General-purpose digital I/O / external clock input USCI_A0/UART or SPI mode, clock output USCI_A0/SPI mode / LCD segment 30 General-purpose digital I/O / slave out/master in of USCI_A0/SPI mode / LCD segment output 31 General-purpose digital I/O / slave in/master out of USCI_A0/SPI mode / LCD segment output 32 General-purpose digital I/O / slave transmit enableUSCI_A0/SPI mode / LCD segment output 33 General-purpose digital I/O / receive data in USCI_A0/UART or IrDA mode / LCD segment output 34 General-purpose digital I/O / transmit data out USCI_A0/UART or IrDA mode / LCD segment output 35 General-purpose digital I/O / external clock input USART1/UART or SPI mode, clock output USART1/SPI MODE / LCD segment output 36 General-purpose digital I/O / slave out/master in of USART1/SPI mode / LCD segment output 37 General-purpose digital I/O / slave in/master out of USART1/SPI mode / LCD segment output 38 General-purpose digital I/O / slave transmit enableUSART1/SPI mode / LCD segment output 39 COM03 are used for LCD backplanes. General-purpose digital I/O / common output, COM03 are used for LCD backplanes. General-purpose digital I/O / common output, COM03 are used for LCD backplanes. General-purpose digital I/O / common output, COM03 are used for LCD backplanes. General-purpose digital I/O / Input port of lowest analog LCD level (V5) General-purpose digital I/O / External reference voltage input for regulated LCD voltage / Input port of third most positive analog LCD level (V4 or V3) General-purpose digital I/O / Input port of second most positive analog LCD level (V2) LCD capacitor connection / Input/output port of most positive analog LCD level (V1) Digital supply voltage, positive terminal Digital supply voltage, negative terminal General-purpose digital I/O / receive data inUSART1/UART mode General-purpose digital I/O / transmit data outUSART1/UART mode General-purpose digital I/O / Timer_B7 CCR6. Capture: CCI6A/CCI6B input, compare: Out6 output General-purpose digital I/O / Timer_B7 CCR5. Capture: CCI5A/CCI5B input, compare: Out5 output General-purpose digital I/O / Timer_B7 CCR4. Capture: CCI4A/CCI4B input, compare: Out4 output
DALLAS, TEXAS 75265


TERMINAL NAME P3.4/TB3 P3.3/UCB0CLK P3.2/UCB0SOMI/ UCB0SCL P3.1/UCB0SIMO/ UCB0SDA P3.0/UCB0STE P2.7/ADC12CLK/ DMAE0 P2.6/CAOUT P2.5/UCA0RXD P2.4/UCA0TXD P2.3/TB2 P2.2/TB1 P2.1/TB0 P2.0/TA2 P1.7/CA1 P1.6/CA0 P1.5/TACLK/ACLK P1.4/TBCLK/SMCLK P1.3/TBOUTH/SVSOUT P1.2/TA1 P1.1/TA0/MCLK P1.0/TA0 XT2OUT XT2IN TDO/TDI TDI/TCLK TMS TCK RST/NMI P6.0/A0/OA0I0 P6.1/A1/OA0O P6.2/A2/OA0I1 NO. PZ 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 NO. ZQW E12 E11 F9 D12 D11 E9 C12 C11 B12 A11 E8 D8 A10 B10 A9 B9 B8 A8 D7 E7 A7 B7 B6 A6 D6 E6 A5 B5 A4 D5 B4 I/O DESCRIPTION General-purpose digital I/O / Timer_B7 CCR3. Capture: CCI3A/CCI3B input, compare: Out3 output General-purpose digital I/O / external clock inputUSCI_B0/UART or SPI mode, clock outputUSCI_B0/SPI mode General-purpose digital I/O / slave out/master in of USCI_B0/SPI mode /I2C clockUSCI_B0/I2C mode General-purpose digital I/O / slave in/master out of USCI_B0/SPI mode, I2C dataUSCI_B0/I2C mode General-purpose digital I/O / slave transmit enableUSCI_B0/SPI mode General-purpose digital I/O / conversion clock12-bit ADC / DMA Channel 0 external trigger General-purpose digital I/O / Comparator_A output General-purpose digital I/O / receive data inUSCI_A0/UART or IrDA mode General-purpose digital I/O / transmit data outUSCI_A0/UART or IrDA mode General-purpose digital I/O / Timer_B7 CCR2. Capture: CCI2A/CCI2B input, compare: Out2 output General-purpose digital I/O / Timer_B7 CCR1. Capture: CCI1A/CCI1B input, compare: Out1 output General-purpose digital I/O / Timer_B7 CCR0. Capture: CCI0A/CCI0B input, compare: Out0 output General-purpose digital I/O / Timer_A Capture: CCI2A input, compare: Out2 output General-purpose digital I/O / Comparator_A input General-purpose digital I/O / Comparator_A input General-purpose digital I/O / Timer_A, clock signal TACLK input / ACLK output (divided by 1, 2, 4, or 8) General-purpose digital I/O / input clock TBCLKTimer_B7 / submain system clock SMCLK output General-purpose digital I/O / switch all PWM digital output impedanceTimer_B7 TB0 to TB6 / SVS: output of SVS comparator ports to high
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O I I/O I I I I I/O I/O I/O
General-purpose digital I/O / Timer_A, Capture: CCI1A input, compare: Out1 output General-purpose digital I/O / Timer_A. Capture: CCI0B input / MCLK output. Note: TA0 is only an input on this pin / BSL receive General-purpose digital I/O / Timer_A. Capture: CCI0A input, compare: Out0 output / BSL transmit Output terminal of crystal oscillator XT2 Input port for crystal oscillator XT2. Only standard crystals can be connected. Test data output port. TDO/TDI data output or programming data input terminal Test data input or test clock input. The device protection fuse is connected to TDI/TCLK. Test mode select. TMS is used as an input port for device programming and test. Test clock. TCK is the clock input port for device programming and test. Reset input or nonmaskable interrupt input port General-purpose digital I/O / analog input a012-bit ADC / OA0 input multiplexer on + terminal and terminal General-purpose digital I/O / analog input a112-bit ADC / OA0 output General-purpose digital I/O / analog input a212-bit ADC / OA0 input multiplexer on + terminal and terminal
DALLAS, TEXAS 75265


TERMINAL NAME AVSS DVSS1 (see Note 1) AVCC NO. PZ 98 99 100 NO. ZQW A3 B3 A2 I/O DESCRIPTION Analog supply voltage, negative terminal. Supplies SVS, brownout, oscillator, comparator_A, port 1 Digital supply voltage, negative terminal Analog supply voltage, positive terminal. Supplies SVS, brownout, oscillator, comparator_A, port 1; must not power up prior to DVCC1/DVCC2.
NOTE 1: All unassigned ball locations on the ZQW package should be electrically tied to the ground supply. The shortest ground return path to the device should be established via ball location B3.
DALLAS, TEXAS 75265

short-form description
CPU The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand. The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register operation execution time is one cycle of the CPU clock. Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant generator respectively. The remaining registers are general-purpose registers. Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all instructions. The MSP430xG461x device family utilizes the MSP430X CPU and is completely backwards compatible with the MSP430 CPU. For a complete description of the MSP430X CPU, see the MSP430x4xx Family Users Guide (SLAU056). instruction set The instruction set consists of the original 51 instructions with three formats and seven address modes and additional instructions for the expanded address range. Each instruction can operate on word and byte data. Table 1 shows examples of the three types of instruction formats; Table 2 shows the address modes.
Program Counter Stack Pointer Status Register Constant Generator General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register PC/R0 SP/R1 SR/CG1/R2 CG2/R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
10
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Table 1. Instruction Word Formats

Dual operands, source-destination Single operands, destination only Relative jump, un/conditional e.g., ADD R4,R5 e.g., CALL e.g., JNE R8 R4 + R5 > R5 PC >(TOS), R8> PC Jump-on-equal bit = 0
Table 2. Address Mode Descriptions

ADDRESS MODE Register Indexed Symbolic (PC relative) Absolute Indirect Indirect autoincrement Immediate NOTE: S = source S D F F F F F F F F F F F D = destination SYNTAX MOV Rs,Rd MOV X(Rn),Y(Rm) MOV EDE,TONI MOV & MEM, & TCDAT MOV @Rn,Y(Rm) MOV @Rn+,Rm MOV #X,TONI MOV @R10,Tab(R6) MOV @R10+,R11 MOV #45,TONI EXAMPLE MOV R10,R11 MOV 2(R5),6(R6) OPERATION R10 > R11 M(2+R5)> M(6+R6) M(EDE) > M(TONI) M(MEM) > M(TCDAT) M(R10) > M(Tab+R6) M(R10) > R11 R10 + 2> R10 #45 > M(TONI)
DALLAS, TEXAS 75265
11

operating modes The MSP430 has one active mode and five software-selectable low-power modes of operation. An interrupt event can wake up the device from any of the five low-power modes, service the request, and restore back to the low-power mode on return from the interrupt program. The following six operating modes can be configured by software:
D Active mode (AM)

All clocks are active
D Low-power mode 0 (LPM0)

CPU is disabled ACLK and SMCLK remain active. MCLK is disabled FLL+ loop control remains active

CPU is disabled FLL+ loop control is disabled ACLK and SMCLK remain active, MCLK is disabled

CPU is disabled MCLK, FLL+ loop control and DCOCLK are disabled DCOs dc-generator remains enabled ACLK remains active

CPU is disabled MCLK, FLL+ loop control, and DCOCLK are disabled DCOs dc-generator is disabled ACLK remains active

CPU is disabled ACLK is disabled MCLK, FLL+ loop control, and DCOCLK are disabled DCOs dc-generator is disabled Crystal oscillator is stopped
12
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interrupt vector addresses The interrupt vectors and the power-up start address are located in the address range 0FFFFh to 0FFC0h. The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence. Table 3. Interrupt Sources, Flags, and Vectors of MSP430xG461x Configurations
INTERRUPT SOURCE Power-Up External Reset Watchdog Flash Memory NMI Oscillator Fault Flash Memory Access Violation Timer_B7 Timer_B7 Comparator_A Watchdog Timer+ USCI_A0/USCI_B0 Receive USCI_A0/USCI_B0 Transmit ADC12 Timer_A3 Timer_A3 I/O Port P1 (Eight Flags) USART1 Receive USART1 Transmit I/O Port P2 (Eight Flags) Basic Timer1/RTC DMA DAC12 INTERRUPT FLAG WDTIFG KEYV (see Note 1 and 5) NMIIFG (see Notes 1 and 3) OFIFG (see Notes 1 and 3) ACCVIFG (see Notes 1, 2, and 5) TBCCR0 CCIFG0 (see Note 2) TBCCR1 CCIFG1 ... TBCCR6 CCIFG6, TBIFG (see Notes 1 and 2) CAIFG WDTIFG UCA0RXIFG, UCB0RXIFG (see Note 1) UCA0TXIFG, UCB0TXIFG (see Note 1) ADC12IFG (see Notes 1 and 2) TACCR0 CCIFG0 (see Note 2) TACCR1 CCIFG1 and TACCR2 CCIFG2, TAIFG (see Notes 1 and 2) P1IFG.0 to P1IFG.7 (see Notes 1 and 2) URXIFG1 UTXIFG1 P2IFG.0 to P2IFG.7 (see Notes 1 and 2) BTIFG DMA0IFG, DMA1IFG, DMA2IFG (see Notes 1 and 2) DAC12.0IFG, DAC12.1IFG (see Notes 1 and 2) SYSTEM INTERRUPT Reset WORD ADDRESS 0FFFEh PRIORITY 31, highest
(Non)maskable (Non)maskable (Non)maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable
0FFFCh 0FFFAh 0FFF8h 0FFF6h 0FFF4h 0FFF2h 0FFF0h 0FFEEh 0FFECh 0FFEAh 0FFE8h 0FFE6h 0FFE4h 0FFE2h 0FFE0h 0FFDEh 0FFDCh 0FFDAh ... 0FFC0h
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 ... 0, lowest
Reserved
Reserved (see Note 4)
NOTES: 1. Multiple source flags 2. Interrupt flags are located in the module. 3. A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh). (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it. 4. The interrupt vectors at addresses 0FFDAh to 0FFC0h are not used in this device and can be used for regular program code if necessary. 5. Access and key violations, KEYV and ACCVIFG, only applicable to F devices.
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special function registers (SFRs)

The MSP430 SFRs are located in the lowest address space and are organized as byte mode registers. SFRs should be accessed with byte instructions.
interrupt enable 1 and 2

Address 0h 7 6 5 ACCVIE rw0 WDTIE OFIE NMIIE ACCVIE Address 01h 7 BTIE rw0 UCA0RXIE UCA0TXIE UCB0RXIE UCB0TXIE URXIE1 UTXIE1 BTIE 4 NMIIE rw0 3 2 1 OFIE rw0 0 WDTIE rw0
Watchdog-timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog timer is configured as a general-purpose timer. Oscillator-fault-interrupt enable Nonmaskable-interrupt enable Flash access violation interrupt enable 6 5 UTXIE1 rw0 USCI_A0 receive-interrupt enable USCI_A0 transmit-interrupt enable USCI_B0 receive-interrupt enable USCI_B0 transmit-interrupt enable USART1 UART and SPI receive-interrupt enable USART1 UART and SPI transmit-interrupt enable Basic timer interrupt enable 4 URXIE1 rw0 3 UCB0TXIE rw0 2 UCB0RXIE rw0 1 UCA0TXIE rw0 0 UCA0RXIE rw0
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interrupt flag register 1 and 2

Address 02h 7 6 5 4 NMIIFG rw0 WDTIFG: OFIFG: NMIIFG: Address 03h 7 BTIFG rw0 UCA0RXIFG UCA0TXIFG UCB0RXIFG UCB0TXIFG URXIFG0: UTXIFG0: BTIFG: Set on watchdog timer overflow (in watchdog mode) or security key violation Reset on VCC power-on or a reset condition at the RST/NMI pin in reset mode Flag set on oscillator fault Set via RST/NMI pin 6 5 UTXIFG1 rw1 USCI_A0 receive-interrupt flag USCI_A0 transmit-interrupt flag USCI_B0 receive-interrupt flag USCI_B0 transmit-interrupt flag USART1: UART and SPI receive flag USART1: UART and SPI transmit flag Basic timer flag 4 URXIFG1 rw0 3 UCB0TXIFG rw0 2 1 0 UCA0RXIFG rw0 3 2 1 OFIFG rw1 0 WDTIFG rw(0)
UCB0RXIFG UCA0TXIFG rw0 rw0
module enable registers 1 and 2

Address 04h Address 05h 7 6 5 UTXE1 rw0 URXE1: UTXE1: USPIE1: Legend 4 URXE1 USPIE1 rw0 3 2 1 0 7 6 5 4 3 2 1 0
USART1: UART mode receive enable USART1: UART mode transmit enable USART1: SPI mode transmit and receive enable rw: rw-0,1: rw-(0,1): Bit can be read and written. Bit can be read and written. It is Reset or Set by PUC. Bit can be read and written. It is Reset or Set by POR. SFR bit is not present in device
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memory organization
MSP430FG4616 Memory Main: interrupt vector Main: code memory RAM (Total) Extended Mirrored Information memory Boot memory RAM (mirrored at 018FFh 01100h) Peripherals Size Flash Flash Size Size Size Size Flash Size ROM Size 92KB 0FFFFh 0FFC0h 018FFFh 002100h 4KB 020FFh 01100h 2KB 020FFh 01900h 2KB 018FFh 01100h 256 Byte 010FFh 01000h 1KB 0FFFh 0C00h 2KB 09FFh 0200h 01FFh 0100h 0FFh 010h 0Fh 00h MSP430CG4616 Memory Main: interrupt vector Main: code memory RAM (Total) Extended Mirrored Information memory Boot memory (Optional on CG) RAM (mirrored at 018FFh 01100h) Peripherals Size ROM ROM Size Size Size Size ROM Size ROM Size 92KB 0FFFFh 0FFC0h 018FFFh 002100h 4KB 020FFh 01100h 2KB 020FFh 01900h 2KB 018FFh 01100h 256 Byte 010FFh 01000h 1KB 0FFFh 0C00h 2KB 09FFh 0200h 01FFh 0100h 0FFh 010h 0Fh 00h MSP430FG4617 92KB 0FFFFh 0FFC0h 019FFFh 003100h 8KB 030FFh 01100h 6KB 030FFh 01900h 2KB 018FFh 01100h 256 Byte 010FFh 01000h 1KB 0FFFh 0C00h 2KB 09FFh 0200h 01FFh 0100h 0FFh 010h 0Fh 00h MSP430CG4617 92KB 0FFFFh 0FFC0h 019FFFh 003100h 8KB 030FFh 01100h 6KB 030FFh 01900h 2KB 018FFh 01100h 256 Byte 010FFh 01000h 1KB 0FFFh 0C00h 2KB 09FFh 0200h 01FFh 0100h 0FFh 010h 0Fh 00h MSP430FG4618 116KB 0FFFFh 0FFC0h 01FFFFh 003100h 8KB 030FFh 01100h 6KB 030FFh 01900h 2KB 018FFh 01100h 256 Byte 010FFh 01000h 1KB 0FFFh 0C00h 2KB 09FFh 0200h 01FFh 0100h 0FFh 010h 0Fh 00h MSP430CG4618 116KB 0FFFFh 0FFC0h 01FFFFh 003100h 8KB 030FFh 01100h 6KB 030FFh 01900h 2KB 018FFh 01100h 256 Byte 010FFh 01000h 1KB 0FFFh 0C00h 2KB 09FFh 0200h 01FFh 0100h 0FFh 010h 0Fh 00h MSP430FG4619 120KB 0FFFFh 0FFC0h 01FFFFh 002100h 4KB 020FFh 01100h 2KB 020FFh 01900h 2KB 018FFh 01100h 256 Byte 010FFh 01000h 1KB 0FFFh 0C00h 2KB 09FFh 0200h 01FFh 0100h 0FFh 010h 0Fh 00h MSP430CG4619 120KB 0FFFFh 0FFC0h 01FFFFh 002100h 4KB 020FFh 01100h 2KB 020FFh 01900h 2KB 018FFh 01100h 256 Byte 010FFh 01000h 1KB 0FFFh 0C00h 2KB 09FFh 0200h 01FFh 0100h 0FFh 010h 0Fh 00h
16 bit 8 bit 8-bit SFR
16 bit 8 bit 8-bit SFR
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bootstrap loader (BSL)

The MSP430 BSL enables users to program the flash memory or RAM using a UART serial interface. Access to the MSP430 memory via the BSL is protected by user-defined password. A bootstrap loader security key is provided at address 0FFBEh to disable the BSL completely or to disable the erasure of the flash if an invalid password is supplied. The BSL is optional for ROM-based devices. For complete description of the features of the BSL and its implementation, see the application report Features of the MSP430 Bootstrap Loader, literature number SLAA089.
BSLKEY 00000h 0AA55h any other value BSL disabled BSL enabled BSL FUNCTION Data Transmit Data Receive PZ/ZQW PACKAGE PINS 87/A7 P1.0 86/E7 P1.1 DESCRIPTION Erasure of flash disabled if an invalid password is supplied
flash memory
The flash memory can be programmed via the JTAG port, the bootstrap loader, or in system by the CPU. The CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
D Flash memory has n segments of main memory and two segments of information memory (A and B) of
128 bytes each. Each segment in main memory is 512 bytes in size.
D Segments 0 to n may be erased in one step, or each segment may be individually erased. D Segments A and B can be erased individually, or as a group with segments 0 to n.
Segments A and B are also called information memory.
D New devices may have some bytes programmed in the information memory (needed for test during
manufacturing). The user should perform an erase of the information memory prior to the first use.
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peripherals
Peripherals are connected to the CPU through data, address, and control buses and can be handled using all instructions. For complete module descriptions, see the MSP430x4xx Family Users Guide (SLAU056).
DMA controller
The DMA controller allows movement of data from one memory address to another without CPU intervention. For example, the DMA controller can be used to move data from the ADC12 conversion memory to RAM. Using the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces system power consumption by allowing the CPU to remain in sleep mode without having to awaken to move data to or from a peripheral.
oscillator and system clock

The clock system in the MSP430xG461x family of devices is supported by the FLL+ module, which includes support for a 32768-Hz watch crystal oscillator, an internal digitally controlled oscillator (DCO), and a high-frequency crystal oscillator. The FLL+ clock module is designed to meet the requirements of both low system cost and low power consumption. The FLL+ features digital frequency locked loop (FLL) hardware that, in conjunction with a digital modulator, stabilizes the DCO frequency to a programmable multiple of the watch crystal frequency. The internal DCO provides a fast turn-on clock source and stabilizes in less than 6 s. The FLL+ module provides the following clock signals:
D D D D
Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high frequency crystal Main clock (MCLK), the system clock used by the CPU Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, or ACLK/8
brownout, supply voltage supervisor

The brownout circuit is implemented to provide the proper internal reset signal to the device during power-on and power-off. The supply voltage supervisor (SVS) circuitry detects if the supply voltage drops below a user selectable level and supports both supply voltage supervision (the device is automatically reset) and supply voltage monitoring (SVM, the device is not automatically reset). The CPU begins code execution after the brownout circuit releases the device reset. However, VCC may not have ramped to VCC(min) at that time. The user must insure the default FLL+ settings are not changed until VCC reaches VCC(min). If desired, the SVS circuit can be used to determine when VCC reaches VCC(min).
digital I/O
There are ten 8-bit I/O ports implementedports P1 through P10:
D D D D D
All individual I/O bits are independently programmable. Any combination of input, output, and interrupt conditions is possible. Edge-selectable interrupt input capability for all the eight bits of ports P1 and P2. Read/write access to port-control registers is supported by all instructions. Ports P7/P8 and P9/P10 can be accessed word-wise as ports PA and PB respectively.
Basic Timer1 and Real-Time Clock

The Basic Timer1 has two independent 8-bit timers that can be cascaded to form a 16-bit timer/counter. Both timers can be read and written by software. Basic Timer1 is extended to provide an integrated real-time clock (RTC). An internal calendar compensates for months with less than 31 days and includes leap-year correction.
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LCD_A drive with regulated charge pump

The LCD_A driver generates the segment and common signals required to drive an LCD display. The LCD_A controller has dedicated data memory to hold segment drive information. Common and segment signals are generated as defined by the mode. Static, 2-MUX, 3-MUX, and 4-MUX LCDs are supported by this peripheral. The module can provide a LCD voltage independent of the supply voltage with its integrated charge pump. Furthermore it is possible to control the level of the LCD voltage and, thus, contrast by software.
watchdog timer (WDT+)

The primary function of the WDT+ module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals.
universal serial communication interface (USCI)

The USCI modules are used for serial data communication. The USCI module supports synchronous communication protocols like SPI (3 or 4 pin), I2C and asynchronous communication protocols like UART, enhanced UART with automatic baudrate detection, and IrDA. The USCI_A0 module provides support for SPI (3 or 4 pin), UART, enhanced UART and IrDA. The USCI_B0 module provides support for SPI (3 or 4 pin) and I2C.
USART1
The hardware universal synchronous/asynchronous receive transmit (USART) peripheral module is used for serial data communication. The USART supports synchronous SPI (3 or 4 pin) and asynchronous UART communication protocols, using double-buffered transmit and receive channels.
hardware multiplier
The multiplication operation is supported by a dedicated peripheral module. The module performs 16 16, 16 8, 8 16, and 8 8 bit operations. The module is capable of supporting signed and unsigned multiplication, as well as signed and unsigned multiply and accumulate operations. The result of an operation can be accessed immediately after the operands have been loaded into the peripheral registers. No additional clock cycles are required.
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Timer_A3
Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.
Timer_A3 Signal Connections Input Pin Number PZ/ZQW 82/B9 - P1.5 Device Input Signal TACLK ACLK SMCLK 82/B9 - P1.5 87/A7 - P1.0 86/E7 - P1.1 TACLK TA0 TA0 DVSS DVCC 85/D7 - P1.2 TA1 CAOUT (internal) DVSS DVCC 79/A10 - P2.0 TA2 ACLK (internal) DVSS DVCC Module Input Name TACLK ACLK SMCLK INCLK CCI0A CCI0B GND VCC CCI1A CCI1B GND VCC CCI2A CCI2B GND VCC CCR2 TA2 79/A10 - P2.0 CCR1 TA1 85/D7 - P1.2 ADC12 (internal) CCR0 TA0 87/A7 - P1.0 Timer NA Module Block Module Output Signal Output Pin Number PZ/ZQW
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Timer_B7
Timer_B7 is a 16-bit timer/counter with seven capture/compare registers. Timer_B7 can support multiple capture/compares, PWM outputs, and interval timing. Timer_B7 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.
Timer_B7 Signal Connections Input Pin Number PZ/ZQW 83/B8 - P1.4 Device Input Signal TBCLK ACLK SMCLK 83/B8 - P1.4 78/D8 - P2.1 78/D8 - P2.1 TBCLK TB0 TB0 DVSS DVCC 77/E8 - P2.2 77/E8 - P2.2 TB1 TB1 DVSS DVCC 76/A11 - P2.3 76/A11 - P2.3 TB2 TB2 DVSS DVCC 67/E12 - P3.4 67/E12 - P3.4 TB3 TB3 DVSS DVCC 66/G9 - P3.5 66/G9 - P3.5 TB4 TB4 DVSS DVCC 65/F11 - P3.6 65/F11 - P3.6 TB5 TB5 DVSS DVCC 64/F12 - P3.7 TB6 ACLK (internal) DVSS DVCC Module Input Name TBCLK ACLK SMCLK INCLK CCI0A CCI0B GND VCC CCI1A CCI1B GND VCC CCI2A CCI2B GND VCC CCI3A CCI3B GND VCC CCI4A CCI4B GND VCC CCI5A CCI5B GND VCC CCI6A CCI6B GND VCC CCR6 TB6 64/F12 - P3.7 CCR5 TB5 65/F11 - P3.6 CCR4 TB4 66/G9 - P3.5 CCR3 TB3 67/E12 - P3.4 CCR2 TB2 76/A11 - P2.3 CCR1 TB1 77/E8 - P2.2 ADC12 (internal) CCR0 TB0 78/D8 - P2.1 ADC12 (internal) Timer NA Module Block Module Output Signal Output Pin Number PZ/ZQW
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Comparator_A
The primary function of the comparator_A module is to support precision slope analog-to-digital conversions, battery-voltage supervision, and monitoring of external analog signals.
ADC12
The ADC12 module supports fast, 12-bit analog-to-digital conversions. The module implements a 12-bit SAR core, sample select control, reference generator and a 16 word conversion-and-control buffer. The conversion-and-control buffer allows up to 16 independent ADC samples to be converted and stored without any CPU intervention.
DAC12
The DAC12 module is a 12-bit, R-ladder, voltage output DAC. The DAC12 may be used in 8- or 12-bit mode, and may be used in conjunction with the DMA controller. When multiple DAC12 modules are present, they may be grouped together for synchronous operation.
OA
The MSP430xG461x has three configurable low-current general-purpose operational amplifiers. Each OA input and output terminal is software-selectable and offer a flexible choice of connections for various applications. The OA op amps primarily support front-end analog signal conditioning prior to analog-to-digital conversion.
OA Signal Connections Input Pin Number PZ 95 - P6.0 97 - P6.2 Device Input Signal OA0I0 OA0I1 DAC12_0OUT (internal) DAC12_1OUT (internal) 3 - P6.4 13 - P5.0 OA1I0 OA1I1 DAC12_0OUT (internal) DAC12_1OUT (internal) 5 - P6.6 14 - P10.7 OA2I0 OA2I1 DAC12_0OUT (internal) DAC12_1OUT (internal) Module Input Name OA0I0 OA0I1 DAC12_0OUT DAC12_1OUT OA1I0 OA1I1 DAC12_0OUT DAC12_1OUT OA2I0 OA2I1 DAC12_0OUT DAC12_1OUT OA2 OA2OUT OA2O OA2O OA2O 4 - P6.5 14 - P10.7 ADC12 (internal) OA1 OA1OUT OA1O OA1O OA1O 2 - P6.3 13- P5.0 ADC12 (internal) OA0 OA0OUT Module Block Module Output Signal Device Output Signal OA0O OA0O Output Pin Number PZ 96 - P6.1 ADC12 (internal)
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peripheral file map

PERIPHERALS WITH WORD ACCESS Watchdog+ Timer_B7 _ Watchdog timer control Capture/compare register 6 Capture/compare register 5 Capture/compare register 4 Capture/compare register 3 Capture/compare register 2 Capture/compare register 1 Capture/compare register 0 Timer_B register Capture/compare control 6 Capture/compare control 5 Capture/compare control 4 Capture/compare control 3 Capture/compare control 2 Capture/compare control 1 Capture/compare control 0 Timer_B control Timer_B interrupt vector Timer_A3 _ Capture/compare register 2 Capture/compare register 1 Capture/compare register 0 Timer_A register Capture/compare control 2 Capture/compare control 1 Capture/compare control 0 Timer_A control Timer_A interrupt vector Hardware Multiplier Sum extend Result high word Result low word Second operand Multiply signed + accumulate/operand1 Multiply + accumulate/operand1 Multiply signed/operand1 Multiply unsigned/operand1 Flash (FG devices only) Flash control 3 Flash control 2 Flash control 1 WDTCTL TBCCR6 TBCCR5 TBCCR4 TBCCR3 TBCCR2 TBCCR1 TBCCR0 TBR TBCCTL6 TBCCTL5 TBCCTL4 TBCCTL3 TBCCTL2 TBCCTL1 TBCCTL0 TBCTL TBIV TACCR2 TACCR1 TACCR0 TAR TACCTL2 TACCTL1 TACCTL0 TACTL TAIV SUMEXT RESHI RESLO OP2 MACS MAC MPYS MPY FCTL3 FCTL2 FCTL1 0120h 019Eh 019Ch 019Ah 0198h 0196h 0194h 0192h 0190h 018Eh 018Ch 018Ah 0188h 0186h 0184h 0182h 0180h 011Eh 0176h 0174h 0172h 0170h 0166h 0164h 0162h 0160h 012Eh 013Eh 013Ch 013Ah 0138h 0136h 0134h 0132h 0130h 012Ch 012Ah 0128h
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peripheral file map (continued)

PERIPHERALS WITH WORD ACCESS (CONTINUED) DMA DMA module control 0 DMA module control 1 DMA interrupt vector DMA Channel 0 DMA channel 0 control DMA channel 0 source address DMA channel 0 destination address DMA channel 0 transfer size DMA Channel 1 DMA channel 1 control DMA channel 1 source address DMA channel 1 destination address DMA channel 1 transfer size DMA Channel 2 DMA channel 2 control DMA channel 2 source address DMA channel 2 destination address DMA channel 2 transfer size DMACTL0 DMACTL1 DMAIV DMA0CTL DMA0SA DMA0DA DMA0SZ DMA1CTL DMA1SA DMA1DA DMA1SZ DMA2CTL DMA2SA DMA2DA DMA2SZ 0122h 0124h 0126h 01D0h 01D2h 01D6h 01DAh 01DCh 01DEh 01E2h 01E6h 01E8h 01EAh 01EEh 01F2h
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PERIPHERALS WITH WORD ACCESS (CONTINUED) ADC12 See also Peripherals With Byte y Access Conversion memory 15 Conversion memory 14 Conversion memory 13 Conversion memory 12 Conversion memory 11 Conversion memory 10 Conversion memory 9 Conversion memory 8 Conversion memory 7 Conversion memory 6 Conversion memory 5 Conversion memory 4 Conversion memory 3 Conversion memory 2 Conversion memory 1 Conversion memory 0 Interrupt-vector-word register Inerrupt-enable register Inerrupt-flag register Control register 1 Control register 0 DAC12 DAC12_1 data DAC12_1 control DAC12_0 data DAC12_0 control Port PA Port PA selection Port PA direction Port PA output Port PA input Port PB Port PB selection Port PB direction Port PB output Port PB input ADC12MEM15 ADC12MEM14 ADC12MEM13 ADC12MEM12 ADC12MEM11 ADC12MEM10 ADC12MEM9 ADC12MEM8 ADC12MEM7 ADC12MEM6 ADC12MEM5 ADC12MEM4 ADC12MEM3 ADC12MEM2 ADC12MEM1 ADC12MEM0 ADC12IV ADC12IE ADC12IFG ADC12CTL1 ADC12CTL0 DAC12_1DAT DAC12_1CTL DAC12_0DAT DAC12_0CTL PASEL PADIR PAOUT PAIN PBSEL PBDIR PBOUT PBIN 015Eh 015Ch 015Ah 0158h 0156h 0154h 0152h 0150h 014Eh 014Ch 014Ah 0148h 0146h 0144h 0142h 0140h 01A8h 01A6h 01A4h 01A2h 01A0h 01CAh 01C2h 01C8h 01C0h 03Eh 03Ch 03Ah 038h 00Eh 00Ch 00Ah 008h
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PERIPHERALS WITH BYTE ACCESS OA2 OA1 OA0 LCD_A Operational Amplifier 2 control register 1 Operational Amplifier 2 control register 0 Operational Amplifier 1 control register 1 Operational Amplifier 1 control register 0 Operational Amplifier 0 control register 1 Operational Amplifier 0 control register 0 LCD Voltage Control 1 LCD Voltage Control 0 LCD Voltage Port Control 1 LCD Voltage Port Control 0 LCD memory 20 : LCD memory 16 LCD memory 15 : LCD memory 1 LCD control and mode OA2CTL1 OA2CTL0 OA1CTL1 OA1CTL0 OA0CTL1 OA0CTL0 LCDAVCTL1 LCDAVCTL0 LCDAPCTL1 LCDAPCTL0 LCDM20 : LCDM16 LCDM15 : LCDM1 LCDCTL ADC12MCTL15 ADC12MCTL14 ADC12MCTL13 ADC12MCTL12 ADC12MCTL11 ADC12MCTL10 ADC12MCTL9 ADC12MCTL8 ADC12MCTL7 ADC12MCTL6 ADC12MCTL5 ADC12MCTL4 ADC12MCTL3 ADC12MCTL2 ADC12MCTL1 ADC12MCTL0 U1TXBUF U1RXBUF U1BR1 U1BR0 U1MCTL U1RCTL U1TCTL U1CTL 0C5h 0C4h 0C3h 0C2h 0C1h 0C0h 0AFh 0AEh 0ADh 0ACh 0A4h : 0A0h 09Fh : 091h 090h 08Fh 08Eh 08Dh 08Ch 08Bh 08Ah 089h 088h 087h 086h 085h 084h 083h 082h 081h 080h 07Fh 07Eh 07Dh 07Ch 07Bh 07Ah 079h 078h
ADC12 ADC memory-control register 15 (Memory control ADC memory-control register 14 registers require byte ADC memory-control register 13 access) ADC memory-control register 12 ADC memory-control register 11 ADC memory-control register 10 ADC memory-control register 9 ADC memory-control register 8 ADC memory-control register 7 ADC memory-control register 6 ADC memory-control register 5 ADC memory-control register 4 ADC memory-control register 3 ADC memory-control register 2 ADC memory-control register 1 ADC memory-control register 0 USART1 Transmit buffer Receive buffer Baud rate Baud rate Modulation control Receive control Transmit control USART control
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PERIPHERALS WITH BYTE ACCESS (CONTINUED) USCI USCI I2C Slave Address USCI I2C Own Address USCI Synchronous Transmit Buffer USCI Synchronous Receive Buffer USCI Synchronous Status USCI I2C Interrupt Enable USCI Synchronous Bit Rate 1 USCI Synchronous Bit Rate 0 USCI Synchronous Control 1 USCI Synchronous Control 0 USCI Transmit Buffer USCI Receive Buffer USCI Status USCI Modulation Control USCI Baud Rate 1 USCI Baud Rate 0 USCI Control 1 USCI Control 0 USCI IrDA Receive Control USCI IrDA Transmit Control USCI LIN Control Comparator_A p _ Comparator_A port disable Comparator_A control 2 Comparator_A control 1 BrownOUT, SVS FLL+Clock SVS control register (Reset by brownout signal) FLL+ Control 1 FLL+ Control 0 System clock frequency control System clock frequency integrator System clock frequency integrator RTC (Basic ( Timer 1) ) Real Time Clock Year High Byte Real Time Clock Year Low Byte Real Time Clock Month Real Time Clock Day of Month Basic Timer1 Counter 2 Basic Timer1 Counter 1 Real Time Counter 4 (Real Time Clock Day of Week) Real Time Counter 3 (Real Time Clock Hour) Real Time Counter 2 (Real Time Clock Minute) Real Time Counter 1 (Real Time Clock Second) Real Time Clock Control Basic Timer1 Control UCBI2CSA UCBI2COA UCBTXBUF UCBRXBUF UCBSTAT UCBI2CIE UCBBR1 UCBBR0 UCBCTL1 UCBCTL0 UCATXBUF UCARXBUF UCASTAT UCAMCTL UCABR1 UCABR0 UCACTL1 UCACTL0 UCAIRRCTL UCAIRTCTL UCAABCTL CAPD CACTL2 CACTL1 SVSCTL FLL_CTL1 FLL_CTL0 SCFQCTL SCFI1 SCFI0 RTCYEARH RTCYEARL RTCMON RTCDAY BTCNT2 BTCNT1 RTCNT4 (RTCDOW) RTCNT3 (RTCHOUR) RTCNT2 (RTCMIN) RTCNT1 (RTCSEC) RTCCTL BTCTL 011Ah 0118h 06Fh 06Eh 06Dh 06Ch 06Bh 06Ah 069h 068h 067h 066h 065h 064h 063h 062h 061h 060h 05Fh 05Eh 05Dh 05Bh 05Ah 059h 056h 054h 053h 052h 051h 050h 04Fh 04Eh 04Dh 04Ch 047h 046h 045h 044h 043h 042h 041h 040h
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PERIPHERALS WITH BYTE ACCESS (CONTINUED) Port P10 Port P10 selection Port P10 direction Port P10 output Port P10 input Port P9 Port P9 selection Port P9 direction Port P9 output Port P9 input Port P8 Port P8 selection Port P8 direction Port P8 output Port P8 input Port P7 Port P7 selection Port P7 direction Port P7 output Port P7 input Port P6 Port P6 selection Port P6 direction Port P6 output Port P6 input Port P5 Port P5 selection Port P5 direction Port P5 output Port P5 input Port P4 Port P4 selection Port P4 direction Port P4 output Port P4 input Port P3 Port P3 selection Port P3 direction Port P3 output Port P3 input Port P2 Port P2 selection Port P2 interrupt enable Port P2 interrupt-edge select Port P2 interrupt flag Port P2 direction Port P2 output Port P2 input Port P1 Port P1 selection Port P1 interrupt enable Port P1 interrupt-edge select Port P1 interrupt flag Port P1 direction Port P1 output Port P1 input P10SEL P10DIR P10OUT P10IN P9SEL P9DIR P9OUT P9IN P8SEL P8DIR P8OUT P8IN P7SEL P7DIR P7OUT P7IN P6SEL P6DIR P6OUT P6IN P5SEL P5DIR P5OUT P5IN P4SEL P4DIR P4OUT P4IN P3SEL P3DIR P3OUT P3IN P2SEL P2IE P2IES P2IFG P2DIR P2OUT P2IN P1SEL P1IE P1IES P1IFG P1DIR P1OUT P1IN 00Fh 00Dh 00Bh 009h 00Eh 00Ch 00Ah 008h 03Fh 03Dh 03Bh 039h 03Eh 03Ch 03Ah 038h 037h 036h 035h 034h 033h 032h 031h 030h 01Fh 01Eh 01Dh 01Ch 01Bh 01Ah 019h 018h 02Eh 02Dh 02Ch 02Bh 02Ah 029h 028h 026h 025h 024h 023h 022h 021h 020h
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PERIPHERALS WITH BYTE ACCESS (CONTINUED) Special p functions SFR module enable 2 SFR module enable 1 SFR interrupt flag 2 SFR interrupt flag 1 SFR interrupt enable 2 SFR interrupt enable 1 ME2 ME1 IFG2 IFG1 IE2 IE1 005h 004h 003h 002h 001h 000h
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absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Voltage range applied at VCC to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to 4.1 V Voltage range applied to any pin (see Note) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to VCC + 0.3 V Diode current at any device terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 mA Storage temperature range, Tstg: Unprogrammed device . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55C to 150C Programmed device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40C to 85C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE: All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is applied to the TDI/TCLK pin when blowing the JTAG fuse.
recommended operating conditions

MIN Supply voltage during program execution (see Note 1), VCC (AVCC = DVCC1/2 = VCC) Supply voltage during flash memory programming (see Note 1), VCC (AVCC = DVCC1/2 = VCC) Supply voltage during program execution, SVS enabled and PORON = 1 (see Note 1 and Note 2), VCC (AVCC = DVCC1/2 = VCC) Supply voltage (see Note 1), VSS (AVSS = DVSS1/2 = VSS) Operating free-air temperature range, TA LF selected, XTS_FLL = 0 LFXT1 crystal t l frequency, f f(LFXT1) (see Note 2) XT1 selected, XTS_FLL = 1 XT1 selected, XTS_FLL = 1 frequency f(XT2) XT2 crystal frequency, MSP430xG461x Watch crystal Ceramic resonator Crystal Ceramic resonator Crystal VCC = 1.8 V Processor frequency (signal MCLK), f(System) VCC = 2.0 V VCC = 3.6 V 450 1000 450 1000 DC DC DC MSP430xG461x MSP430FG461x 1.8 2.7 NOM MAX 3.6 3.6 UNITS V V
MSP430xG461x
2 0 40 32.768
3.6 0 85 8000 8000 8000 8000 3.0 4.6 8.0
V V C kHz
kHz
MHz
NOTES: 1. It is recommended to power AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can be tolerated during power up and operation. 2. The minimum operating supply voltage is defined according to the trip point where POR is going active by decreasing the supply voltage. POR is going inactive when the supply voltage is raised above the minimum supply voltage plus the hysteresis of the SVS circuitry. 3. In LF mode, the LFXT1 oscillator requires a watch crystal. In XT1 mode, LFXT1 accepts a ceramic resonator or a crystal. fSystem (MHz) 8.0 MHz
Supply voltage range, MSP430xG461x, during program execution
4.6 MHz 3.0 MHz
1.8
2.0 2.7 3 Supply Voltage V
Supply voltage range, MSP430FG461x, during flash memory programming
3.6
Figure 1. Frequency vs Supply Voltage, Typical Characteristic
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DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature (unless otherwise noted)
supply current into AVCC + DVCC excluding external current
PARAMETER Active mode ( (see Note 1 and Note 4) ) f(MCLK) = f(SMCLK) = 1 MHz, MH f(ACLK) = 32,768 Hz XTS=0, SELM=(0,1) (FG461x: Program executes from flash) Low-power Low power mode (LPM0) (see Note 1 and Note 4) CG461x TEST CONDITIONS TA = 40 40C to 85C VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V TA = 40 40C to 85C VCC = 3 V TA = 40C TA = 25C TA = 60C TA = 85C TA = 40C TA = 25C TA = 60C TA = 85C Low-power Low power mode (LPM3) f(MCLK) = f(SMCLK) = 0 MHz, f(ACLK) = 32,768 Hz, SCG0 = 1 Basic Timer1 enabled, ACLK selected LCD A enabled LCD_A enabled, LCDCPEN = 0; (4mux mode; fLCD = f(ACLK) /32) (see Note 2 and Note 3 and Note 4) TA = 40C TA = 25C TA = 60C TA = 85C TA = 40C TA = 25C TA = 60C TA = 85C TA = 40C TA = 25C Low-power mode (LPM4) f(MCLK) = 0 MHz, f(SMCLK) = 0 MHz, f(ACLK) = 0 Hz, SCG0 = 1 (see Note Note ( N t 2 and dN t 4) TA = 60C TA = 85C TA = 40C TA = 25C TA = 60C TA = 85C NOTES: 1. 2. 3. 4. VCC = 3 V VCC = 2 2.2 2V VCC = 3 V VCC = 2 2.2 2V VCC = 3 V 2V VCC = 2 2.2 17 1.3 1.3 2.22 6.5 1.9 1.9 2.5 7.5 1.5 1.5 2.8 7.2 2.5 2.5 3.2 8.5 0.13 0.22 0.9 4.3 0.13 0.3 1.1 5.0 24 4.0 4.0 6.5 15.0 5.0 5.0 7.5 18.0 5.5 5.5 7.0 17.0 6.5 6.5 8.0 20.0 1.0 1.0 2.5 12.5 1.6 1.6 3.0 15.0 A A A MIN TYP 280 470 400 600 45 75 11 MAX 370 580 480 740 70 110 20 A UNIT A
I(AM)
FG461x xG461x
TA = 40 40C to 85C 40C to 85C TA = 40
A A
I(LPM0)
I(LPM2)
Low-power mode (LPM2), f(MCLK) = f (SMCLK) = 0 MHz, f(ACLK) = 32,768 Hz, SCG0 = 0 (see Note 2 and Note 4) Low-power Low power mode (LPM3) f(MCLK) = f(SMCLK) = 0 MHz, f(ACLK) = 32,768 Hz, SCG0 = 1 Basic Timer1 enabled, ACLK selected LCD A enabled LCD_A enabled, LCDCPEN = 0; (static mode; fLCD = f(ACLK) /32) (see Note 2 and Note 3 and Note 4)
I(LPM3)
I(LPM3)
I(LPM4)
Timer_B is clocked by f(DCOCLK) = f(DCO) = 1 MHz. All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. The LPM3 currents are characterized with a Micro Crystal CC4VT1A (9 pF) crystal and OSCCAPx = 1h. Current for brownout included.
Current consumption of active mode versus system frequency, F version: I(AM) = I(AM) [1 MHz] f(System) [MHz] Current consumption of active mode versus supply voltage, F version: I(AM) = I(AM) [3 V] + 200 A/V (VCC 3 V)
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electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)
Schmitt-trigger inputs Ports P1 to P10, RST/NMI, JTAG (TCK, TMS, TDI/TCLK, TDO/TDI)
PARAMETER VIT+ VIT Vhys Positive going input threshold voltage Positive-going Negative going input threshold voltage Negative-going Input voltage hysteresis (VIT+ VIT) TEST CONDITIONS VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V MIN 1.1 1.5 0.4 0.9 0.3 0.5 TYP MAX 1.55 1.98 0.9 1.3 1.1 1 V V V UNIT
inputs Px.x, TAx, TBx

PARAMETER t(int) External interrupt timing Timer_A, Timer_B capture timing Timer_A, Timer_B clock frequency externally applied to pin Timer_A, Timer_B clock frequency TEST CONDITIONS Port P1, P2: P1.x to P2.x, external trigger signal for the interrupt flag, (see Note 1) TA0, TA1, TA2 TB0, TB1, TB2, TB3, TB4, TB5, TB6 TACLK TBCLK TACLK, TBCLK, INCLK: t(H) = t(L) VCC 2.2 V 3V 2.2 V 3V 2.2 V 3V 2.2 V SMCLK or ACLK signal selected 3V MIN 62 50 62 50 8 MHz 10 8 10 MHz ns ns TYP MAX UNIT
t(cap) f(TAext) f(TBext) f(TAint) f(TBint)
NOTES: 1. The external signal sets the interrupt flag every time the minimum t(int) parameters are met. It may be set even with trigger signals shorter than t(int).
leakage current Ports P1 to P10 (see Note 1)

PARAMETER Ilkg(Px.y) Leakage current Port Px TEST CONDITIONS V(Px.y) (see Note 2) (1 x 10, 0 y 7) VCC = 2.2 V/3 V MIN TYP MAX 50 UNIT nA
NOTES: 1. The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted. 2. The port pin must be selected as input.
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outputs Ports P1 to P10
PARAMETER TEST CONDITIONS IOH(max) = 1.5 mA, VOH High level output voltage High-level IOH(max) = 6 mA, IOH(max) = 1.5 mA, IOH(max) = 6 mA, IOL(max) = 1.5 mA, VOL Low level output voltage Low-level IOL(max) = 6 mA, IOL(max) = 1.5 mA, IOL(max) = 6 mA, VCC = 2.2 V, VCC = 2.2 V, VCC = 3 V, VCC = 3 V, VCC = 2.2 V, VCC = 2.2 V, VCC = 3 V, VCC = 3 V, See Note 1 See Note 2 See Note 1 See Note 2 See Note 1 See Note 2 See Note 1 See Note 2 MIN VCC0.25 VCC0.6 VCC0.25 VCC0.6 VSS VSS VSS VSS TYP MAX VCC VCC VCC VCC VSS+0.25 VSS+0.6 VSS+0.25 VSS+0.6 V V UNIT
NOTES: 1. The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed 12 mA to satisfy the maximum specified voltage drop. 2. The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed 48 mA to satisfy the maximum specified voltage drop.
output frequency
PARAMETER f(Px.y) f(MCLK) f(SMCLK) f(ACLK) (1 x 10 10, 0 y 7) P1.1/TA0/MCLK, P1.4/TBCLK/SMCLK, P1.5/TACLK/ACLK P1.5/TACLK/ACLK, CL = 20 pF VCC = 2.2 V / 3 V t(Xdc) Duty cycle of output frequency P1.1/TA0/MCLK, CL = 20 pF, VCC = 2.2 V / 3 V P1.4/TBCLK/SMCLK, CL = 20 pF, VCC = 2.2 V / 3 V CL = 20 pF VCC = 2 2.2 2V VCC = 3 V f(ACLK) = f(LFXT1) = f(XT1) f(ACLK) = f(LFXT1) = f(LF) f(ACLK) = f(LFXT1) f(MCLK) = f(XT1) f(MCLK) = f(DCOCLK) f(SMCLK) = f(XT2) f(SMCLK) = f(DCOCLK) 40% 50% 15 ns 40% 50% 15 ns 50% 50% DC 40% 30% 50% 60% 50%+ 15 ns 60% 50%+ 15 ns 10 12 60% 70% MHz MHz CL = 20 pF, IL = 1.5 mA TEST CONDITIONS VCC = 2.2 V VCC = 3 V MIN DC DC TYP MAX 10 12 UNIT MHz MHz
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electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued)
typical characteristics outputs
TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE
25.0 I OL Typical Low-Level Output Current mA VCC = 2.2 V P2.0 20.0 I OL Typical Low-Level Output Current mA TA = 25C TA = 85C 50.0 VCC = 3 V P2.0 40.0 TA = 85C 30.0 TA = 25C
TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE
15.0
10.0
20.0
5.0
10.0
0.0 0.0
0.5
1.0
1.5
2.0
2.5
0.0 0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VOL Low-Level Output Voltage V
VOL Low-Level Output Voltage V
Figure 2
TYPICAL HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE
0.0 I OH Typical High-Level Output Current mA I OH Typical High-Level Output Current mA VCC = 2.2 V P2.0 5.0 0.0 VCC = 3 V P2.0 10.0
Figure 3
TYPICAL HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE
10.0
20.0
15.0
30.0
20.0
TA = 85C TA = 25C 0.5 1.0 1.5 2.0 2.5 VOH High-Level Output Voltage V
40.0
TA = 85C
25.0 0.0
50.0 0.0
TA = 25C 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VOH High-Level Output Voltage V
Figure 4
Figure 5
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DALLAS, TEXAS 75265

wake-up LPM3
PARAMETER TEST CONDITIONS f = 1 MHz td(LPM3) Delay time f = 2 MHz f = 3 MHz VCC = 2.2 V/3 V MIN TYP MAX 6 6 6 s UNIT
RAM
PARAMETER VRAMh TEST CONDITIONS CPU halted (see Note 1) MIN 1.6 TYP MAX UNIT V
NOTE 1: This parameter defines the minimum supply voltage when the data in program memory RAM remain unchanged. No program execution should take place during this supply voltage condition.
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LCD_A
PARAMETER VCC(LCD) Supply voltage (see Note 2) TEST CONDITIONS Charge pump enabled (LCDCPEN = 1; VLCDx > 0000) VLCD(typ)=3 V; LCDCPEN = 1, VLCDx= 1000; all segments on, fLCD = fACLK/32, no LCD connected (see Note 4) TA = 25C Charge pump enabled (LCDCPEN = 1; VLCDx > 0000) VCC MIN 2.2 TYP MAX 3.6 UNIT V
ICC(LCD)
Supply current (see Note 2 )
2.2 V
CLCD fLCD
Capacitor on LCDCAP (see Note 1 and Note 3) LCD frequency
4.7 1.1
F kHz
VLCDx = 0000 VLCDx = 0001 VLCDx = 0010 VLCDx = 0011 VLCDx = 0100 VLCDx = 0101 VLCDx = 0110 VLCDx = 0111 VLCD LCD voltage (see Note 3) VLCDx = 1000 VLCDx = 1001 VLCDx = 1010 VLCDx = 1011 VLCDx = 1100 VLCDx = 1101 VLCDx = 1110 VLCDx = 1111 RLCD LCD driver output impedance VLCD=3 V; CPEN = 1; VLCDx = 1000, ILOAD = 10 2.2 V
VCC 2.60 2.66 2.72 2.78 2.84 2.90 2.96 3.02 3.08 3.14 3.20 3.26 3.32 3.38 3.44 3.60 10 k V
NOTES: 1. Enabling the internal charge pump with an external capacitor smaller than the minimum specified might damage the device. 2. Refer to the supply current specifications I(LPM3) for additional current specifications with the LCD_A module active. 3. Segments S0 through S3 are disabled when the LCD charge pump feature is enabled (LCDCPEN = 1) and cannot be used together with the LCD charge pump. In addition, when using segments S0 through S3 with an external LCD voltage supply, VLCD AVCC. 4. Connecting an actual display will increase the current consumption depending on the size of the LCD.
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DALLAS, TEXAS 75265

Comparator_A (see Note 1)
PARAMETER I(CC) TEST CONDITIONS CAON 1 CARSEL=0, CAON=1, CARSEL 0 CAREF=0 CAREF 0 CAON=1, CARSEL=0, CAREF=1/2/3, No load at P1.6/CA0 P1 6/CA0 and P1.7/CA1 CC node V PCA0=1, CARSEL=1, CAREF=1, No load at P1.6/CA0 and P1.7/CA1 PCA0=1, CARSEL=1, CAREF=2, No load at P1.6/CA0 and P1.7/CA1 PCA0=1, CARSEL=1, CAREF=3, No load at P1.6/CA0 P1 6/CA0 and P1.7/CA1; P1 7/CA1; TA = 85C Common-mode input voltage range Offset voltage Input hysteresis CAON=1 See Note 2 CAON = 1 TA = 25C, Overdrive 10 mV, without filter: CAF = 0 t(response LH) TA = 25C Overdrive 10 mV, with filter: CAF = 1 TA = 25C Overdrive 10 mV, without filter: CAF = 0 t(response HL) TA = 25C, Overdrive 10 mV, with filter: CAF = 1 VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V / 3 V 0.23 MIN TYP 25 45 30 45 0.24 MAX 40 60 50 71 0.25 A UNIT A
I(Refladder/RefDiode) Voltage @ 0.25 V CC Voltage @ 0.5 V V CC
V(Ref025)
V(Ref050)
CC
node
VCC = 2.2V / 3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V / 3 V VCC = 2.2 V / 3 V VCC = 2.2 V / 3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V
0.47 390 400 0 30 0 160 80 1.4 0.9 130 80 1.4 0.9
0.48 480 490
0.5 540 mV 550 VCC1 30 V mV mV ns s ns s
V(RefVT) VIC VpVS Vhys
0.7 210 150 1.9 1.5 210 150 1.9 1.5
1.4 300 240 3.4 2.6 300 240 3.4 2.6
NOTES: 1. The leakage current for the Comparator_A terminals is identical to Ilkg(Px.x) specification. 2. The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A inputs on successive measurements. The two successive measurements are then summed together.
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typical characteristics
REFERENCE VOLTAGE vs FREE-AIR TEMPERATURE
650 VCC = 3 V VREF Reference Voltage mV VREF Reference Voltage mV 600 Typical 550 600 Typical 550 650 VCC = 2.2 V
REFERENCE VOLTAGE vs FREE-AIR TEMPERATURE
500
500
450
450
400 45
25
15
35
55
75
95
400 45
25
15
35
55
75
95
TA Free-Air Temperature C
TA Free-Air Temperature C
Figure 6. V(RefVT) vs Temperature

0V 0 VCC 1 CAON
Figure 7. V(RefVT) vs Temperature
CAF
Low-Pass Filter + _ 0 1 0 1
To Internal Modules
V+ V
CAOUT Set CAIFG Flag 2 s
Figure 8. Block Diagram of Comparator_A Module

Overdrive V VCAOUT
400 mV V+ t(response)
Figure 9. Overdrive Definition
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DALLAS, TEXAS 75265

POR/brownout reset (BOR) (see Note 1)
PARAMETER td(BOR) VCC(start) V(B_IT) Vhys(B_IT) t(reset) Brownout (see Notes 2 and 3) dVCC/dt 3 V/s (see Figure 10) dVCC/dt 3 V/s (see Figure 10 through Figure 12) dVCC/dt 3 V/s (see Figure 10) Pulse length needed at RST/NMI pin to accepted reset internally, VCC = 2.2 V/3 V 70 2 130 0.7 V(B_IT) 1.79 210 TEST CONDITIONS MIN TYP MAX 2000 UNIT s V V mV s
NOTES: 1. The current consumption of the brownout module is already included in the ICC current consumption data. 2. The voltage level V(B_IT) + Vhys(B_IT) is 1.89V. 3. During power up, the CPU begins code execution following a period of td(BOR) after VCC = V(B_IT) + Vhys(B_IT). The default FLL+ settings must not be changed until VCC VCC(min), where VCC(min) is the minimum supply voltage for the desired operating frequency. See the MSP430x4xx Family Users Guide for more information on the brownout/SVS circuit.
VCC Vhys(B_IT) V(B_IT) VCC(start)
0 t d(BOR)
Figure 10. POR/Brownout Reset (BOR) vs Supply Voltage

2 VCC = 3 V Typical Conditions VCC(drop) V 1.5 1 0.5 0 0.001 VCC(drop) VCC 3V t pw
1 tpw Pulse Width s
1000 1 ns 1 ns tpw Pulse Width s
Figure 11. VCC(drop) Level With a Square Voltage Drop to Generate a POR/Brownout Signal
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typical characteristics (continued)

VCC 2 VCC = 3 V VCC(drop) V 1.5 1 VCC(drop) 0.5 0 0.001 tf = tr 1 tpw Pulse Width s 1000 tf tr tpw Pulse Width s Typical Conditions 3V t pw
Figure 12. VCC(drop) Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal
SVS (supply voltage supervisor/monitor) (see Note 1)
PARAMETER t(SVSR) td(SVSon) tsettle V(SVSstart) dVCC/dt 30 V/ms SVS on, switch from VLD = 0 to VLD 0, VCC = 3 V VLD 0 VLD 0, VCC/dt 3 V/s (see Figure 13) VLD = 1 VCC/dt 3 V/s (see Figure 13) Vhys(SVS_IT) VCC/dt 3 V/s (see Figure 13), external voltage applied on A7 VLD = 2 .. 14 VLD = 15 VLD = 1 VLD = 2 VLD = 3 VLD = 4 VLD = 5 VLD = 6 VCC/dt 3 V/s (see Figure 13) V(SVS_IT) (SVS IT ) VLD = 7 VLD = 8 VLD = 9 VLD = 10 VLD = 11 VLD = 12 VLD = 13 VLD = 14 VCC/dt 3 V/s (see Figure 13), external voltage applied on A7 ICC(SVS) (see Note 1)

TEST CONDITIONS dVCC/dt > 30 V/ms (see Figure 13)
MIN 5
TYP
MAX 150 2000
UNIT s s s V mV
150 1.55 70 V(SVS_IT) x 0.001 4.4 1.8 1.94 2.05 2.14 2.24 2.33 2.46 2.58 2.69 2.83 2.94 3.11 3.24 3.43 1.1 1.9 2.1 2.2 2.3 2.4 2.5 2.65 2.8 2.9 3.05 3.2 3.35 3.5 3.7 1.2 10 120
300 12 1.7 155 V(SVS_IT) x 0.016 20 2.05 2.23 2.35 2.46 2.58 2.69 2.84 2.97 3.10 3.26 3.39 3.58 3.73 3.96 1.3 15
mV
VLD = 15
VLD 0, VCC = 2.2 V/3 V
The recommended operating voltage range is limited to 3.6 V. tsettle is the settling time that the comparator o/p needs to have a stable level after VLD is switched VLD 0 to a different VLD value somewhere between 2 and 15. The overdrive is assumed to be > 50 mV. NOTE 1: The current consumption of the SVS module is not included in the ICC current consumption data.
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DALLAS, TEXAS 75265

VCC V(SVS_IT) V(SVSstart) V(B_IT) VCC(start) Brownout Region BrownOut Region Software Sets VLD>0: SVS is Active Vhys(SVS_IT) Vhys(B_IT)
Brownout 1 0 SVSOut 1 0 Set POR 1
td(BOR)
SVS Circuit is Active From VLD > to VCC < V(B_IT)
t d(BOR)
td(SVSon) undefined
td(SVSR)
Figure 13. SVS Reset (SVSR) vs Supply Voltage

VCC 3V t pw
2 Rectangular Drop 1.5 VCC(drop) V Triangular Drop 1 1 ns 0.5 VCC 3V 0 1 10 100 1000 tpw Pulse Width s VCC(drop) tf = tr tf tr t pw 1 ns VCC(drop)
t Pulse Width s
Figure 14. VCC(drop) With a Square Voltage Drop and a Triangle Voltage Drop to Generate an SVS Signal
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DCO
PARAMETER f(DCOCLK) f(DCO=2) f(DCO=27) f(DCO=2) f(DCO=27) f(DCO=2) f(DCO=27) f(DCO=2) f(DCO=27) f(DCO=2) f(DCO=27) Sn Dt DV TEST CONDITIONS N(DCO)=01Eh, FN_8=FN_4=FN_3=FN_2=0, D = 2; DCOPLUS= 0 FN 8 FN 4 FN 3 FN 2 0 ; DCOPLUS = 1 FN_8=FN_4=FN_3=FN_2=0 FN 8 FN 4 FN 3 FN 2 0; DCOPLUS = 1 FN_8=FN_4=FN_3=FN_2=0; FN 8 FN 4 FN 3 0 FN FN_8=FN_4=FN_3=0, FN_2=1; 2 1; DCOPLUS = 1 FN 8 FN 4 FN 3 0 FN FN_8=FN_4=FN_3=0, FN_2=1; 2 1; DCOPLUS = 1 FN 8 FN 4 0 FN 3 1 2 x; DCOPLUS = 1 FN_8=FN_4=0, FN_3= 1, FN FN_2=x; FN 8 FN 4 0 FN FN_8=FN_4=0, FN_3= 3 1 1, FN FN_2=x; 2 x; DCOPLUS = 1 FN 8 0 FN FN_8=0, FN_4= 4 1 1, FN FN_3= 3 FN FN_2=x; 2 x; DCOPLUS = 1 FN 8 0 FN FN_8=0, FN_4=1, 4 1 FN FN_3= 3 FN FN_2=x; 2 x; DCOPLUS = 1 FN 8 1 FN FN_8=1, FN_4=FN_3=FN_2=x; 4 FN 3 FN 2 x; DCOPLUS = 1 FN 8 1 FN 4 FN 3 FN 2 x; DCOPLUS = 1 FN_8=1,FN_4=FN_3=FN_2=x; Step size between adjacent DCO taps: Sn = fDCO(Tap n+1) / fDCO(Tap n) (see Figure 16 for taps 21 to 27) Temperature drift, N(DCO) = 01Eh, FN_8=FN_4=FN_3=FN_2=0 D = 2; DCOPLUS = 0 Drift with VCC variation, N(DCO) = 01Eh, FN_8=FN_4=FN_3=FN_2=0 D = 2; DCOPLUS = 0 f f VCC 2.2 V/3 V 2.2 V 3V 2.2 V 3V 2.2 V 3V 2.2 V 3V 2.2 V 3V 2.2 V 3V 2.2 V 3V 2.2 V 3V 2.2 V 3V 2.2 V 3V 1 < TAP 20 TAP = 27 2.2 V 3V 0.3 0.3 2.5 2.7 0.7 0.8 5.7 6.5 1.2 1.3 9 10.3 1.8 2.1 13.5 16 2.8 4.2 21 30 1.06 1.07 0.2 0.2 0 0.3 0.3 5 MIN TYP 1 0.65 0.7 5.6 6.1 1.3 1.5 10.8 12.1 2 2.2 15.5 17.9 2.8 3.4 21.5 26.6 4.2 6.3 32 46 1.25 1.3 10.5 11.3 2.3 2.5 18 20 3 3.5 25 28.5 4.2 5.2 33 41 6.2 9.2 46 70 1.11 1.17 0.4 0.4 15 %/_C %/V MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MAX UNIT MHz
f f
(DCO)
(DCO)
(DCO3V)
(DCO20 5 C)
1.0
1.0
1.8
2.4
3.0
3.6 VCC V
40
20
20
40
60
85 TA C
Figure 15. DCO Frequency vs Supply Voltage VCC and vs Ambient Temperature
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DALLAS, TEXAS 75265

1.17
1.11
1.07 1.06

Max Min 1 DCO Tap 20 27
Sn - Stepsize Ratio between DCO Taps
Figure 16. DCO Tap Step Size
f(DCO)
Legend Tolerance at Tap 27 DCO Frequency Adjusted by Bits 29 to 25 in SCFI1 {N{DCO}} Tolerance at Tap 2 Overlapping DCO Ranges: Uninterrupted Frequency Range
FN_2=0 FN_3=0 FN_4=0 FN_8=0
FN_2=1 FN_3=0 FN_4=0 FN_8=0
FN_2=x FN_3=1 FN_4=0 FN_8=0
FN_2=x FN_3=x FN_4=1 FN_8=0
FN_2=x FN_3=x FN_4=x FN_8=1
Figure 17. Five Overlapping DCO Ranges Controlled by FN_x Bits
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43

crystal oscillator, LFXT1 oscillator (see Notes 1 and 2)
PARAMETER TEST CONDITIONS OSCCAPx = 0h, VCC = 2.2 V / 3 V CXIN Integrated input capacitance (see Note 4) OSCCAPx = 1h, VCC = 2.2 V / 3 V OSCCAPx = 2h, VCC = 2.2 V / 3 V OSCCAPx = 3h, VCC = 2.2 V / 3 V OSCCAPx = 0h, VCC = 2.2 V / 3 V CXOUT Integrated output capacitance (see Note 4) OSCCAPx = 1h, VCC = 2.2 V / 3 V OSCCAPx = 2h, VCC = 2.2 V / 3 V OSCCAPx = 3h, VCC = 2.2 V / 3 V VIL VIH Input levels at XIN VCC = 2 2.2 2 V/3 V (see Note 3) VSS 0.8VCC MIN TYP 0 10 14 18 0 10 14 18 0.2VCC VCC V pF pF MAX UNIT
NOTES: 1. The parasitic capacitance from the package and board may be estimated to be 2 pF. The effective load capacitor for the crystal is (CXIN x CXOUT) / (CXIN + CXOUT). This is independent of XTS_FLL. 2. To improve EMI on the low-power LFXT1 oscillator, particularly in the LF mode (32 kHz), the following guidelines should be observed. Keep the trace between the device and the crystal as short as possible. Design a good ground plane around the oscillator pins. Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT. Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins. Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins. If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins. Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This signal is no longer required for the serial programming adapter. 3. Applies only when using an external logic-level clock source. XTS_FLL must be set. Not applicable when using a crystal or resonator. 4. External capacitance is recommended for precision real-time clock applications; OSCCAPx = 0h.
crystal oscillator, XT2 oscillator (see Note 1)

PARAMETER CXT2IN CXT2OUT VIL VIH Integrated input capacitance Integrated output capacitance Input levels at XT2IN TEST CONDITIONS VCC = 2.2 V/3 V VCC = 2.2 V/3 V 2 2 V/3 V (see Note 2) VCC = 2.2 VSS 0.8 VCC MIN NOM 2 2 0.2 VCC VCC MAX UNIT pF pF V V
NOTES: 1. The oscillator needs capacitors at both terminals, with values specified by the crystal manufacturer. 2. Applies only when using an external logic-level clock source. Not applicable when using a crystal or resonator.
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DALLAS, TEXAS 75265

USCI (UART mode)
PARAMETER fUSCI USCI input clock frequency BITCLK clock frequency (equals Baudrate in MBaud) UART receive deglitch time (see Note 1) TEST CONDITIONS Internal: SMCLK, ACLK External: UCLK Duty Cycle = 50% 10% 2.2V /3 V 2.2 V 3V 50 50 150 100 VCC MIN TYP MAX fSYSTEM UNIT MHz
fBITCLK t
1 600 600
MHz ns
NOTE 1: Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are correctly recognized their width should exceed the maximum specification of the deglitch time.
USCI (SPI master mode) (see Figure 18 and Figure 19)

PARAMETER fUSCI tSU,MI tHD,MI tVALID,MO USCI input clock frequency SOMI input data setup time SOMI input data hold time SIMO output data valid time UCLK edge to SIMO valid; CL = 20 pF TEST CONDITIONS SMCLK, ACLK Duty Cycle = 50% 10% 2.2 V 3V 2.2 V 3V 2.2 V 3V 110 75 0 0 30 20 ns ns ns VCC MIN TYP MAX fSYSTEM UNIT MHz
USCI (SPI slave mode) (see Figure 20 and Figure 21)

PARAMETER tSTE,LEAD tSTE,LAG tSTE,ACC tSTE,DIS tSU,SI tHD,SI tVALID,SO STE lead time STE low to clock STE lag time Last clock to STE high STE access time STE low to SOMI data out STE disable time STE high to SOMI high impedance SIMO input data setup time SIMO input data hold time SOMI output data valid time UCLK edge to SOMI valid; CL = 20 pF TEST CONDITIONS VCC 2.2 V/3 V 2.2 V/3 V 2.2 V/3 V 2.2 V/3 V 2.2 V 3V 2.2 V 3V 2.2 V 3V 20 15 10 10 75 50 110 75 ns ns ns 10 50 50 MIN TYP 50 MAX UNIT ns ns ns ns
DALLAS, TEXAS 75265
45

1/fUCxCLK CKPL UCLK CKPL =1 tLOW/HIGH tLOW/HIGH tSU,MI tHD,MI SOMI =0
tVALID ,MO SIMO
Figure 18. SPI Master Mode, CKPH = 0

1/fUCxCLK CKPL UCLK CKPL =1 tLOW/HIGH tLOW/HIGH tSU,MI SOMI tHD,MI =0
tVALID ,MO SIMO
Figure 19. SPI Master Mode, CKPH = 1
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DALLAS, TEXAS 75265

tSTE,LEAD STE 1/fUCxCLK CKPL UCLK CKPL =1 tLOW/HIGH tLOW/HIGH tSU,SIMO tHD,SIMO SIMO =0 tSTE,LAG
tACC SOMI
tVALID ,SOMI
tDIS
Figure 20. SPI Slave Mode, CKPH = 0

tSTE,LEAD STE 1/fUCxCLK CKPL=0 UCLK CKPL=1 tLOW/HIGH tLOW/HIGH tSU,SI SIMO tHD,SI tSTE,LAG
tACC SOMI
tVALID ,SO
tDIS
Figure 21. SPI Slave Mode, CKPH = 1
DALLAS, TEXAS 75265
47

USCI (I2C mode) (see Figure 22)
PARAMETER fUSCI fSCL tHD,STA tSU,STA tHD,DAT tSU,DAT tSU,STO tSP USCI input clock frequency SCL clock frequency Hold time (repeated) START Set up time for a repeated START Setup Data hold time Data setup time Setup time for STOP Pulse width of spikes suppressed by input filter tHD , STA
SDA
TEST CONDITIONS Internal: SMCLK, ACLK External: UCLK Duty Cycle = 50% 10%
VCC
MIN
TYP
MAX fSYSTEM
UNIT MHz kHz s s ns ns s
2.2 V/3 V fSCL 100kHz fSCL > 100kHz fSCL 100kHz fSCL > 100kHz 2.2 V/3 V 2.2 V/3 V 2.2 V/3 V 2.2 V/3 V 2.2 V/3 V 2.2 V/3 V 2.2 V/3 V 2.2 V 3V tSU , STA tHD , STA
0 4.0 0.6 4.7 0.6 0 250 4.0 50 50 150 100 tBUF
400
600 600 ns
t
SCL
LOW
tHIGH
tSP
tSU ,DAT tHD ,DAT
tSU , STO
Figure 22. I2C Mode Timing USART1 (see Note 1)

PARAMETER t() USART1 deglitch time TEST CONDITIONS VCC = 2.2 V, SYNC = 0, UART mode VCC = 3 V, SYNC = 0, UART mode MIN 200 150 TYP 430 280 MAX 800 500 UNIT ns
NOTE 1: The signal applied to the USART1 receive signal/terminal (URXD1) should meet the timing requirements of t() to ensure that the URXS flip-flop is set. The URXS flip-flop is set with negative pulses meeting the minimum-timing condition of t(). The operating conditions to set the flag must be met independently from this timing constraint. The deglitch circuitry is active only on negative transitions on the URXD1 line.
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DALLAS, TEXAS 75265

12-bit ADC, power supply and input range conditions (see Note 1)
PARAMETER AVCC Analog supply voltage TEST CONDITIONS AVCC and DVCC are connected together, AVSS and DVSS are connected together, V(AVSS) = V(DVSS) = 0 V All external Ax terminals. Analog inputs selected in ADC12MCTLx register and P6Sel.x=1, V(AVSS) VAx V(AVCC) fADC12CLK = 5.0 MHz, ADC12ON = 1, 1 REFON = 0, 0 SHT0=0, SHT1=0, ADC12DIV=0 fADC12CLK = 5.0 MHz, ADC12ON = 0, REFON = 1, REF2_5V = 1 fADC12CLK = 5.0 MHz, ADC12ON = 0 0, REFON = 1, REF2_5V = 0 Only one terminal can be selected at one time, Ax 0V VAx VAVCC VCC = 2.2 V VCC = 3 V VCC = 3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V MIN 2.2 TYP MAX 3.6 UNIT V
V(P6.x/Ax)
Analog input voltage range (see Note 2) Operating supply current into AVCC terminal (see Note 3)
0 0.65 0.8 0.5 0.5 0.5
VAVCC 1.3
IADC12
mA 1.6 0.8 0.8 mA 0.8 40 2000 pF mA
IREF+
Operating supply current i t AVCC t into terminal i l (see Note 4)
CI RI NOTES: 1. 2. 3. 4.
Input capacitance Input MUX ON resistance
The leakage current is defined in the leakage current table with Ax parameter. The analog input voltage range must be within the selected reference voltage range VR+ to VR for valid conversion results. The internal reference supply current is not included in current consumption parameter IADC12. The internal reference current is supplied via terminal AVCC. Consumption is independent of the ADC12ON control bit, unless a conversion is active. The REFON bit enables to settle the built-in reference before starting an A/D conversion.
12-bit ADC, external reference (see Note 1)

PARAMETER VeREF+ VREF /VeREF (VeREF+ VREF/VeREF) IVeREF+ IVREF/VeREF Positive external reference voltage input Negative external reference voltage input Differential external reference voltage input Input leakage current Input leakage current TEST CONDITIONS VeREF+ > VREF/VeREF, (see Note 2) VeREF+ > VREF/VeREF, (see Note 3) VeREF+ > VREF/VeREF, (see Note 4) 0V VeREF+ VAVCC 0V VeREF VAVCC VCC = 2.2 V/3 V VCC = 2.2 V/3 V MIN 1.4 0 1.4 TYP MAX VAVCC 1.2 VAVCC 1 1 UNIT V V V A A
NOTES: 1. The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, CI, is also the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy. 2. The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced accuracy requirements. 3. The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced accuracy requirements. 4. The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with reduced accuracy requirements.
DALLAS, TEXAS 75265
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12-bit ADC, built-in reference
PARAMETER Positive built in reference built-in voltage output TEST CONDITIONS REF2_5V = 1 for 2.5 V, IVREF+max IVREF+ IVREF+min REF2_5V = 0 for 1.5 V, IVREF+max IVREF+ IVREF+min VCC = 3 V VCC = 2.2 V/3 V MIN 2.4 1.44 2.2 2.8 2.9 0.01 0.01 0.5 1 2 2 2 LSB mA V NOM 2.5 1.5 MAX 2.6 V 1.56 UNIT
VREF+
AVCC(min)
AVCC minimum voltage, Positive built-in built in reference active Load current out of VREF+ terminal
REF2_5V = 0, IVREF+max IVREF+ IVREF+min REF2_5V = 1, IVREF+min IVREF+ 0.5mA REF2_5V = 1, IVREF+min IVREF+ 1mA VCC = 2.2 V VCC = 3 V IVREF+ = 500 A +/ 100 A, Analog input voltage ~0.75 0 75 V; REF2_5V = 0 IVREF+ = 500 A 100 A, Analog input voltage ~1.25 V, REF2_5V = 1 IVREF+ =100 A 900 A, CVREF+=5 5 F F, ax ~0.5 0 5 x VREF+, Error of conversion result 1 LSB REFON =1, 0 mA IVREF+ IVREF+max IVREF+ is a constant in the range of 0 mA IVREF+ 1 mA IVREF+ = 0.5 mA, CVREF+ = 10 F, VREF+ = 1.5 V, VAVCC = 2.2 V VCC = 2.2 V VCC = 3 V VCC = 3 V
IVREF+
IL(VREF)+
Load current regulation Load-current VREF+ terminal
LSB
IDL(VREF) + CVREF+ TREF+
Load current regulation VREF+ terminal Capacitance at pin VREF+ (see Note 1) Temperature coefficient of built-in reference Settle time of internal reference voltage (see Figure 23 and Note 2)
VCC = 3 V VCC = 2.2 V/3 V VCC = 2.2 V/3 V 5 10
20
ns F
100
ppm/C
tREFON
17
ms
NOTES: 1. The internal buffer operational amplifier and the accuracy specifications require an external capacitor. All INL and DNL tests uses two capacitors between pins VREF+ and AVSS and VREF/VeREF and AVSS: 10 F tantalum and 100 nF ceramic. 2. The condition is that the error in a conversion started after tREFON is less than 0.5 LSB. The settling time depends on the external capacitive load. CVREF+ 100 F
10 F
tREFON .66 x CVREF+ [ms] with CVREF+ in F
1 F 0 1 ms 10 ms 100 ms tREFON
Figure 23. Typical Settling Time of Internal Reference tREFON vs External Capacitor on VREF+
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DALLAS, TEXAS 75265

From Power Supply
DVCC1/2 + 10 F DVSS1/2 100 nF AVCC AVSS 100 nF VREF+ or VeREF+
+ 10 F Apply External Reference [VeREF+] or Use Internal Reference [VREF+] + 10 F + 10 F 100 nF 100 nF
MSP430FG461x
Apply External Reference
VREF/VeREF
Figure 24. Supply Voltage and Reference Voltage Design VREF/VeREF External Supply
From Power Supply DVCC1/2 + 10 F DVSS1/2 100 nF AVCC AVSS 100 nF VREF+ or VeREF+
+ Apply External Reference [VeREF+] or Use Internal Reference [VREF+] 10 F + 10 F Reference Is Internally Switched to AVSS 100 nF
MSP430FG461x
VREF/VeREF
Figure 25. Supply Voltage and Reference Voltage Design VREF/VeREF = AVSS, Internally Connected
DALLAS, TEXAS 75265
51

12-bit ADC, timing parameters
PARAMETER fADC12CLK fADC12OSC Internal ADC12 oscillator TEST CONDITIONS For specified performance of ADC12 linearity parameters ADC12DIV=0, fADC12CLK=fADC12OSC CVREF+ 5 F, Internal oscillator, fADC12OSC = 3.7 MHz to 6.3 MHz VCC = 2.2V/3 V VCC = 2.2 V/ 3 V VCC = 2.2 V/ 3 V MIN 0.45 3.7 2.06 13ADC12DIV 1/fADC12CLK 100 VCC = 3 V VCC = 2.2 V 1220 ns 1400 NOM 5 5 MAX 6.3 6.3 3.51 UNIT MHz MHz s s ns
tCONVERT
Conversion time
External fADC12CLK from ACLK, MCLK, or SMCLK, ADC12SSEL 0 (see Note 1) RS = 400 , RI = 1000 , CI = 30 pF pF, = [RS + RI] x CI, (see Note 2)
tADC12ON
Turn on settling time of the ADC Sampling time
tSample
NOTES: 1. The condition is that the error in a conversion started after tADC12ON is less than 0.5 LSB. The reference and input signal are already settled. 2. Approximately ten Tau () are needed to get an error of less than 0.5 LSB: tSample = ln(2n+1) x (RS + RI) x CI+ 800 ns where n = ADC resolution = 12, RS = external source resistance.
12-bit ADC, linearity parameters

PARAMETER EI ED Integral linearity error Differential linearity error Offset error TEST CONDITIONS 1.4 V (VeREF+ VREF/VeREF) min 1.6 V 1.6 V < (VeREF+ VREF/VeREF) min [VAVCC] (VeREF+ VREF/VeREF)min (VeREF+ VREF/VeREF), CVREF+ = 10 F (tantalum) and 100 nF (ceramic) (VeREF+ VREF/VeREF)min (VeREF+ VREF/VeREF), Internal impedance of source RS < 100 , CVREF+ = 10 F (tantalum) and 100 nF (ceramic) (VeREF+ VREF/VeREF)min (VeREF+ VREF/VeREF), CVREF+ = 10 F (tantalum) and 100 nF (ceramic) (VeREF+ VREF/VeREF)min (VeREF+ VREF/VeREF), CVREF+ = 10 F (tantalum) and 100 nF (ceramic) VCC = 2.2 V/3 V VCC = 2.2 V/3 V VCC = 2.2 V/3 V VCC = 2.2 V/3 V VCC = 2.2 V/3 V 2 1.1 2 MIN NOM MAX 2 1.7 1 4 2 5 UNIT LSB LSB
EO
LSB
EG ET
Gain error Total unadjusted error
LSB LSB
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DALLAS, TEXAS 75265

12-bit ADC, temperature sensor and built-in VMID
PARAMETER ISENSOR VSENSOR TCSENSOR Sample time required if channel 10 is selected (see Note 3) Current into divider at channel 11 (see Note 4) AVCC divider at channel 11 Sample time required if channel 11 is selected (see Note 5) Operating supply current into AVCC terminal (see Note 1) (see Note 2) TEST CONDITIONS REFON = 0, INCH = 0Ah, ADC12ON=NA, TA = 25_C ADC12ON = 1, INCH = 0Ah, TA = 0C ADC12ON = 1 1, INCH = 0Ah ADC12ON = 1, INCH = 0Ah, Error of conversion result 1 LSB ADC12ON = 1 1, INCH = 0Bh ADC12ON = 1, INCH = 0Bh, VMID is ~0.5 x VAVCC ADC12ON = 1, INCH = 0Bh, Error of conversion result 1 LSB VCC 2.2 V 3V 2.2 V/ 3V 2.2 V/ 3V 2.2 V 3V 2.2 V 3V 2.2 V 3V 2.2 V 3V 1400 ns 1220 1.1 1.5 30 30 NA NA 1.10.04 1.500.04 s MIN NOM 40 60 986 3 553% 3.55 MAX 120 160 UNIT A mV mV/C
tSENSOR(sample)
IVMID VMID
A V
tVMID(sample)
NOTES: 1. The sensor current ISENSOR is consumed if (ADC12ON = 1 and REFON=1), or (ADC12ON=1 AND INCH=0Ah and sample signal is high). When REFON = 1, ISENSOR is already included in IREF+. 2. The temperature sensor offset can be as much as 20_C. A single-point calibration is recommended in order to minimize the offset error of the built-in temperature sensor. 3. The typical equivalent impedance of the sensor is 51 k. The sample time required includes the sensor-on time tSENSOR(on) 4. No additional current is needed. The VMID is used during sampling. 5. The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed.
12-bit DAC, supply specifications

PARAMETER AVCC Analog supply voltage TEST CONDITIONS AVCC = DVCC, AVSS = DVSS =0 V DAC12AMPx=2, DAC12IR=0, DAC12_xDAT=0800h Supply current: Single DAC Channel (see Notes 1 and 2) DAC12AMPx=2, DAC12IR=1, DAC12_xDAT=0800h , VeREF+=VREF+= AVCC DAC12AMPx=5, DAC12IR=1, DAC12_xDAT=0800h, VeREF+=VREF+= AVCC DAC12AMPx=7, DAC12IR=1, DAC12_xDAT=0800h, VeREF+=VREF+= AVCC Power-supply rejection ratio (see Notes 3 and 4) DAC12_xDAT = 800h, VREF = 1.5 V, AVCC = 100mV DAC12_xDAT = 800h, VREF = 1.5 V or 2.5 V, AVCC = 100mV 2.2 V 70 3V dB VCC MIN 2.20 50 50 2 2 V/3 V 2.2 200 700 440 1500 TYP MAX 3.60 110 110 A UNIT V
IDD
PSRR
NOTES: 1. No load at the output pin, DAC12_0 or DAC12_1, assuming that the control bits for the shared pins are set properly. 2. Current into reference terminals not included. If DAC12IR = 1 current flows through the input divider; see Reference Input specifications. 3. PSRR = 20*log{AVCC/VDAC12_xOUT}. 4. VREF is applied externally. The internal reference is not used.
DALLAS, TEXAS 75265
53

12-bit DAC, linearity specifications (see Figure 26)
PARAMETER Resolution Integral nonlinearity (see Note 1) TEST CONDITIONS (12-bit Monotonic) Vref = 1.5 V, DAC12AMPx = 7, DAC12IR = 1 Vref = 2.5 V, DAC12AMPx = 7, DAC12IR = 1 Vref = 1.5 V, DAC12AMPx = 7, DAC12IR = 1 Vref = 2.5 V, DAC12AMPx = 7, DAC12IR = 1 Vref = 1.5 V, DAC12AMPx = 7, DAC12IR = 1 Vref = 2.5 V, DAC12AMPx = 7, DAC12IR = 1 Vref = 1.5 V, DAC12AMPx = 7, DAC12IR = 1 Vref = 2.5 V, DAC12AMPx = 7, DAC12IR = 1 2.2 V 2.0 20 3V 2.2 V 0.4 04 3V 2.2 V 21 3V mV 2.2 V 2.5 25 3V 1.0 10 LSB 8.0 80 LSB VCC MIN 12 TYP MAX UNIT bits
INL
DNL
Differential nonlinearity (see Note 1)
EO
Offset voltage without calibration (see Notes 1, 2)
Offset voltage with calibration (see Notes 1, 2) dE(O)/dT Offset error temperature coefficient (see Note 1) Gain error (see Note 1) Gain temperature coefficient (see Note 1)
2.2 V/3 V VREF = 1.5 V VREF = 2.5 V 2.2 V 3V 2.2 V/3 V DAC12AMPx = 2
30
V/C
EG dE(G)/dT
3.50 3 50 10 100
% FSR ppm of FSR/C
tOffset_Cal
Time for offset calibration (see Note 3)
DAC12AMPx = 3,5 DAC12AMPx = 4,6,7
2.2 V/3 V
32 6
ms
NOTES: 1. Parameters calculated from the best-fit curve from 0x0A to 0xFFF. The best-fit curve method is used to deliver coefficients a and b of the first order equation: y = a + b*x. VDAC12_xOUT = EO + (1 + EG) * (VeREF+/4095) * DAC12_xDAT, DAC12IR = 1. 2. The offset calibration works on the output operational amplifier. Offset Calibration is triggered setting bit DAC12CALON 3. The offset calibration can be done if DAC12AMPx = {2, 3, 4, 5, 6, 7}. The output operational amplifier is switched off with DAC12AMPx = {0, 1}. It is recommended that the DAC12 module be configured prior to initiating calibration. Port activity during calibration may effect accuracy and is not recommended. DAC V OUT DAC Output RLoad = AV CC 2 CLoad = 100pF Offset Error Positive Negative Gain Error DAC Code VR+ Ideal transfer function
Figure 26. Linearity Test Load Conditions and Gain/Offset Definition
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DALLAS, TEXAS 75265

12-bit DAC, linearity specifications (continued)
TYPICAL INL ERROR vs DIGITAL INPUT DATA
4 INL Integral Nonlinearity Error LSB 3 2 1 0 1 2 3 4 0 512 1024 1536 2048 2560 3072 3584 4095 DAC12_xDAT Digital Code VCC = 2.2 V, VREF = 1.5V DAC12AMPx = 7 DAC12IR = 1
TYPICAL DNL ERROR vs DIGITAL INPUT DATA

2.0 DNL Differential Nonlinearity Error LSB 1.5 1.0 0.5 0.0 0.5 1.0 1.5 2.0 0 512 1024 1536 2048 2560 3072 3584 4095 DAC12_xDAT Digital Code VCC = 2.2 V, VREF = 1.5V DAC12AMPx = 7 DAC12IR = 1
DALLAS, TEXAS 75265
55

12-bit DAC, output specifications
PARAMETER TEST CONDITIONS No Load, VeREF+ = AVCC, DAC12_xDAT = 0h, DAC12IR = 1, DAC12AMPx = 7 No Load, VeREF+ = AVCC, DAC12_xDAT = 0FFFh, DAC12IR = 1, DAC12AMPx = 7 RLoad= 3 k, VeREF+ = AVCC, DAC12_xDAT = 0h, DAC12IR = 1, DAC12AMPx = 7 RLoad= 3 k, VeREF+ = AVCC, DAC12_xDAT = 0FFFh, DAC12IR = 1, DAC12AMPx = 7 CL(DAC12) Max DAC12 load capacitance Max DAC12 load current RLoad= 3 k, VO/P(DAC12) < 0.3 V, DAC12AMPx = 2, DAC12_xDAT = 0h RO/P(DAC12) Output resistance ( g ) (see Figure 29) RLoad= 3 k, VO/P(DAC12) > AVCC0.3 V DAC12_xDAT = 0FFFh 2.2 V/3 V 2.2V/3V 2.2V 3V 0.5 1.0 150 2 2 V/3 V 2.2 0 0.1 VCC MIN 0 TYP MAX 0.005 UNIT
VO
Output voltage range (see Note 1, Figure 29)
AVCC0.05
AVCC V
AVCC0.13
AVCC
100 +0.5 +1.0 250
pF
IL(DAC12)
mA
150
250
RLoad= 3 k, 0.3V VO/P(DAC12) AVCC 0.3V NOTE 1: Data is valid after the offset calibration of the output amplifier. RO/P(DAC12_x) Max AV CC 2 O/P(DAC12_x) CLoad= 100pF Min 0.3
ILoad DAC12
RLoad
AV CC0.3V
VOUT
AV CC
Figure 29. DAC12_x Output Resistance Tests
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DALLAS, TEXAS 75265

12-bit DAC, reference input specifications
PARAMETER VeREF+ Reference input voltage range TEST CONDITIONS DAC12IR=0 (see Notes 1 and 2) DAC12IR=1 (see Notes 3 and 4) DAC12_0 IR=DAC12_1 IR =0 DAC12_0 IR=1, DAC12_1 IR = 0 Ri(VREF+), Ri(VeREF+) Reference input p resistance DAC12_0 IR=0, DAC12_1 IR = 1 40 2 2 V/3 V 2.2 48 56 k DAC12_0 IR=DAC12_1 IR =1, DAC12_0 SREFx = DAC12_1 SREFx 20 24 28 (see Note 5) For a full-scale output, the reference input voltage can be as high as 1/3 of the maximum output voltage swing (AVCC). The maximum voltage applied at reference input voltage terminal VeREF+ = [AVCC VE(O)] / [3*(1 + EG)]. For a full-scale output, the reference input voltage can be as high as the maximum output voltage swing (AVCC). The maximum voltage applied at reference input voltage terminal VeREF+ = [AVCC VE(O)] / (1 + EG). When DAC12IR = 1 and DAC12SREFx = 0 or 1 for both channels, the reference input resistive dividers for each DAC are in parallel reducing the reference input resistance. 2 2 V/3 V 2.2 20 VCC MIN TYP AVCC/3 AVcc MAX AVCC+0.2 AVcc+0.2 UNIT V M
NOTES: 1. 2. 3. 4. 5.
12-bit DAC, dynamic specifications; Vref = VCC, DAC12IR = 1 (see Figure 30 and Figure 31)
PARAMETER DAC12 on-time on time TEST CONDITIONS DAC12_xDAT = 800h, ErrorV(O) < 0.5 LSB (see Note 1,Figure 30) DAC12_xDAT DAC12 xDAT = 80h F7Fh 80h DAC12_xDAT = 3F8h 408h 3F8h BF8h C08h BF8h DAC12_xDAT = 80h F7Fh 80h (see Note 2) DAC12 xDAT = DAC12_xDAT 80h F7Fh 80h DAC12AMPx = 0 {2, 3, 4} DAC12AMPx = 0 {5, 6} DAC12AMPx = 0 7 DAC12AMPx = 2 tS(FS) Settling time, time full-scale full scale DAC12AMPx = 3,5 DAC12AMPx = 4,6,7 DAC12AMPx = 2 DAC12AMPx = 3,5 DAC12AMPx = 4,6,7 DAC12AMPx = 2 DAC12AMPx = 3,5 DAC12AMPx = 4,6,7 DAC12AMPx = 2 Glitch energy, full full-scale scale DAC12AMPx = 3,5 DAC12AMPx = 4,6,7 2.2 V/3 V 2.2 V/3 V 0.05 0.35 1.5 2.2 V/3 V 2.2 V/3 V 2.2 V/3 V VCC MIN TYP 60 15 6 100 40 15 5 2 1 0.12 0.7 2.7 600 150 30 nV-s nV s V/s s MAX 120 30 12 200 80 30 s s UNIT
tON
tS(C-C)
Settling time, time code to code
SR
Slew rate
NOTES: 1. RLoad and CLoad connected to AVSS (not AVCC/2) in Figure 30. 2. Slew rate applies to output voltage steps >= 200mV. Conversion 1 DAC Output ILoad RLoad = 3 k AV CC 2 RO/P(DAC12.x) CLoad = 100pF +/ 1/2 LSB VOUT Glitch Energy Conversion 2 +/ 1/2 LSB Conversion 3
tsettleLH
tsettleHL
Figure 30. Settling Time and Glitch Energy Testing
DALLAS, TEXAS 75265
57

Conversion 1 VOUT 90% 90% Conversion 2 Conversion 3
10%
10%
tSRLH
tSRHL
Figure 31. Slew Rate Testing 12-bit DAC, dynamic specifications continued (TA = 25C unless otherwise noted)
PARAMETER TEST CONDITIONS DAC12AMPx = {2, 3, 4}, DAC12SREFx = 2, DAC12IR = 1, DAC12_xDAT = 800h BW3dB 3 dB bandwidth, b d idth 3-dB VDC=1.5V, VAC=0.1VPP (see Figure 32) DAC12AMPx = {5, 6}, DAC12SREFx = 2, DAC12IR = 1, DAC12_xDAT = 800h DAC12AMPx = 7, DAC12SREFx = 2, DAC12IR = 1, DAC12_xDAT = 800h DAC12_0DAT = 800h, No Load, DAC12_1DAT = 80h<>F7Fh, RLoad = 3k fDAC12_1OUT = 10kHz @ 50/50 duty cycle Channel-to-channel crosstalk (see Note 1 and Figure 33) NOTE 1: RLOAD = 3 k, CLOAD = 100 pF DAC12_0DAT = 80h<>F7Fh, RLoad = 3k, DAC12_1DAT = 800h, No Load, fDAC12_0OUT = 10kHz @ 50/50 duty cycle 2.2 V/3 V VCC MIN 40 180 550 kHz TYP MAX UNIT
80 2 2 V/3 V 2.2 80 dB
Ve REF+ DAC12_x AC DC
ILoad DACx
RLoad = 3 k AV CC 2 CLoad = 100pF
Figure 32. Test Conditions for 3-dB Bandwidth Specification

ILoad DAC12_0 DAC0 CLoad= 100pF VREF+ ILoad e DAC12_1 DAC1 CLoad= 100pF RLoad AV CC 2 V DAC12_yOUT V DAC12_xOUT fToggle RLoad AV CC 2 DAC12_xDAT 080h V OUT 7F7h 080h 7F7h 080h
Figure 33. Crosstalk Test Conditions
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DALLAS, TEXAS 75265

operational amplifier OA, supply specifications
PARAMETER VCC Supply voltage Fast Mode, OARRIP = 1 (rail-to-rail mode off) Medium Mode, OARRIP = 1 (rail-to-rail mode off) Slow Mode, OARRIP = 1 (rail-to-rail mode off) Fast Mode, OARRIP = 0 (rail-to-rail mode on) Medium Mode, OARRIP = 0 (rail-to-rail mode on) Slow Mode, OARRIP = 0 (rail-to-rail mode on) PSRR Power supply rejection ratio Non-inverting 2.2 V/3 V NOTE 1: P6SEL.x = 1 for each corresponding pin when used in OA input or OA output mode. 2 2 V/3 V 2.2 300 190 90 70 490 350 190 dB TEST CONDITIONS VCC MIN 2.2 180 110 50 TYP MAX 3.6 290 190 80 A UNIT V
ICC
Supply current (see Note 1)
DALLAS, TEXAS 75265
59

operational amplifier OA, input/output specifications

PARAMETER VI/P IIkg Voltage supply supply, I/P Input leakage current, I/P (see Notes 1 and 2) TEST CONDITIONS OARRIP = 1 (rail-to-rail mode off) OARRIP = 0 (rail-to-rail mode on) TA = 40 to +55_C TA = +55 to +85_C Fast Mode Medium Mode Slow Mode Vn Voltage noise density density, I/P Fast Mode Medium Mode Slow Mode VIO Offset voltage voltage, I/P Offset temperature drift, I/P Offset voltage drift with supply, I/P VOH VOL High level output voltage High-level voltage, O/P Low level output voltage Low-level voltage, O/P see Note 3 0.3V VIN VCC0.3V VCC 10%, TA = 25C Fast Mode, ISOURCE 500A Slow Mode,ISOURCE 150A Fast Mode, ISOURCE +500A Slow Mode,ISOURCE +150A RLoad= 3 k, CLoad = 50pF, OARRIP = 0 (rail-to-rail mode on), VO/P(OAx) < 0.2 V RO/P (OAx) Output Resistance (see Figure 34 and Note 4) RLoad= 3 k, CLoad = 50pF, OARRIP = 0 (rail-to-rail mode on), VO/P(OAx) > AVCC 0.2 V RLoad= 3 k, CLoad = 50pF, OARRIP = 0 (rail-to-rail mode on), 0.2 V VO/P(OAx) AVCC 0.2 V CMRR Common-mode rejection ratio Non-inverting 2.2 V/3 V NOTES: 1. 2. 3. 4. ESD damage can degrade input current leakage. The input bias current is overridden by the input leakage current. Calculated using the box method. Specification valid for voltage-follower OAx configuration. 2.2 V/3 V 2 2 V/3 V 2.2 2.2 V/3 V 2.2 V/3 V 2.2 V 3V 2.2 V 3V VCC0.2 VCC0.1 VSS VSS 150 10 1.5 VCC VCC 0.2 0.1 250 V fV(I/P) = 10 kHz fV(I/P) = 1 kHz VCC MIN 0.1 0.1 5 20 0.5 5 50 80 140 30 50 65 10 mV V/C mV/V V nV/Hz TYP MAX VCC1.2 VCC+0.1 5 20 nA UNIT V
150
250
0.1 70
4 dB
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DALLAS, TEXAS 75265

RO/P(OAx) ILoad OAx O/P(OAx) CLoad RLoad AV CC 2 Min 0.2V AV CC 0.2VAV V CC OUT Max
Figure 34. OAx Output Resistance Tests operational amplifier OA, dynamic specifications
PARAMETER Fast Mode SR Slew rate Open-loop voltage gain m Phase margin Gain margin Gain-bandwidth product (see Figure 35 and Figure 36) Enable time on Enable time off CL = 50 pF CL = 50 pF Non inverting Fast Mode Noninverting, Mode, RL = 47k, CL = 50pF Non inverting Medium Mode Noninverting, Mode, RL =300k 300k, CL = 50pF Non inverting Slow Mode 300k, CL = 50pF Noninverting, Mode, RL =300k ton, non-inverting, Gain = 1 2.2 V/3 V 2.2 V/3 V 2 2 V/3 V 2.2 Medium Mode Slow Mode TEST CONDITIONS VCC MIN TYP 1.2 0.8 0.3 100 60 20 22 2.2 14 1.4 05 0.5 10 20 1 s s MHz dB deg dB V/s MAX UNIT
GBW ten(on) ten(off)
TYPICAL OPEN-LOOP GAIN vs FREQUENCY

140 120 100 80 Gain dB 60 40 20 0 20 40 60 80 0.001 250 1 200 Slow Mode Phase degrees Medium Mode Fast Mode 50 0
TYPICAL PHASE vs FREQUENCY
Fast Mode 100
Medium Mode 150 Slow Mode
0.01
0.1 1 10 100 Input Frequency kHz
1000 10000
10
100
1000
10000
Input Frequency kHz
Figure 35
Figure 36
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operational amplifier OA feedback network, noninverting amplifier mode (OAFCx = 4)
PARAMETER TEST CONDITIONS OAFBRx = 0 OAFBRx = 1 OAFBRx = 2 OAFBRx = 3 G Gain OAFBRx = 4 OAFBRx = 5 OAFBRx = 6 OAFBRx = 7 THD tSettle Total harmonic distortion/ nonlinearity Settling time (see Note 1) 2.2 V All gains All power modes 3V 2.2 V/3 V 2 2 V/ 3 V 2.2 VCC MIN 0.996 1.329 1.987 2.64 3.93 5.22 7.76 15.0 TYP 1.00 1.334 2.001 2.667 4.00 5.33 7.97 15.8 60 70 7 12 dB s MAX 1.002 1.340 2.016 2.70 4.06 5.43 8.18 16.6 UNIT
NOTES: 1. The settling time specifies the time until an ADC result is stable. This includes the minimum required sampling time of the ADC. The settling time of the amplifier itself might be faster.
operational amplifier OA feedback network, inverting amplifier mode (OAFCx = 6) (see Note 1)
PARAMETER TEST CONDITIONS OAFBRx = 1 OAFBRx = 2 OAFBRx = 3 G Gain OAFBRx = 4 OAFBRx = 5 OAFBRx = 6 OAFBRx = 7 THD tSettle Total harmonic distortion/ nonlinearity Settling time (see Note 2) 2.2 V All gains All power modes 3V 2.2 V/3 V 2 2 V/ 3 V 2.2 VCC MIN 0.371 1.031 1.727 3.142 4.581 7.529 17.04 0 TYP 0.335 1.002 1.668 3.00 4.33 6.97 14.8 60 70 7 12 dB s MAX 0.298 0.972 1.609 2.856 4.073 6.379 12.27 9 UNIT
NOTES: 1. This includes the 2 OA configuration inverting amplifier with input buffer. Both OA needs to be set to the same power mode OAPMx. 2. The settling time specifies the time until an ADC result is stable. This includes the minimum required sampling time of the ADC. The settling time of the amplifier itself might be faster.
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flash memory (MSP430FG461x devices only)
PARAMETER VCC(PGM/
ERASE)
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
Program and Erase supply voltage Flash Timing Generator frequency Supply current from DVCC during program Supply current from DVCC during erase Supply current from DVCC during global mass erase Cumulative program time Cumulative mass erase time Program/Erase endurance Data retention duration Word or byte program time Block program time for 1st byte or word Block program time for each additional byte or word Block program end-sequence wait time Mass erase time Global mass erase time Segment erase time S Note N t 2 See TJ = 25C See Note 3 See Note 4 See Note 1 2.7 V/ 3.6 V 2.7 V/ 3.6 V 2.7 V/ 3.6 V 2.7 V/ 3.6 V 2.7 V/ 3.6 V
2.7 257 3 3 6
3.6 476 5 7 14 10
V kHz mA mA mA ms ms cycles years
fFTG IPGM IERASE IGMERASE tCPT tCMErase tRetention tWord tBlock, 0 tBlock, 1-63 tBlock, End tMass Erase tGlobal Mass Erase tSeg Erase
20 104 100 30 25 18 6 10593 10593 4819 105
tFTG
NOTES: 1. The cumulative program time must not be exceeded during a block-write operation. This parameter is only relevant if the block write feature is used. 2. These values are hardwired into the Flash Controllers state machine (tFTG = 1/fFTG). 3. Lower 64-KB or upper 64-KB Flash memory erased. 4. All Flash memory erased.
JTAG interface
PARAMETER fTCK RInternal TCK input frequency Internal pull-up resistance on TMS, TCK, TDI/TCLK TEST CONDITIONS See Note 1 See Note 2 VCC 2.2 V 3V 2.2 V/ 3 V MIN 0 0 25 60 TYP MAX 5 10 90 UNIT MHz MHz k
NOTES: 1. fTCK may be restricted to meet the timing requirements of the module selected. 2. TMS, TDI/TCLK, and TCK pull-up resistors are implemented in all versions.
JTAG fuse (see Note 1)

PARAMETER VCC(FB) VFB IFB tFB Supply voltage during fuse-blow condition Voltage level on TDI/TCLK for fuse-blow: F versions Supply current into TDI/TCLK during fuse blow Time to blow fuse TEST CONDITIONS TA = 25C VCC MIN 2.5 6 7 100 1 TYP MAX UNIT V V mA ms
NOTE 1: Once the fuse is blown, no further access to the MSP430 JTAG/Test and emulation features is possible. The JTAG block is switched to bypass mode.
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APPLICATION INFORMATION input/output schematics

Port P1, P1.0 to P1.5, input/output with Schmitt trigger Pad Logic DVSS DVSS DVSS P1DIR.x
0 1
Direction 0: Input 1: Output
P1OUT.x Module X OUT P1SEL.x
0 1 Bus Keeper EN P1.0/TA0 P1.1/TA0/MCLK P1.2/TA1 P1.3/TBOUTH/SVSOUT P1.4/TBCLK /SMCLK P1.5/TACLK/ACLK
P1IN.x EN Module X IN D
P1IE.x P1IRQ.x P1IFG.x P1SEL.x P1IES.x Note: x = 0,1,2,3,4,5 Q
EN Set Interrupt Edge Select
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Port P1 (P1.0 to P1.5) pin functions

(P1 X) PIN NAME (P1.X) P1.0/TA0 CONTROL BITS / SIGNALS X 0 P1.0 (I/O) Timer_A3.CCI0A Timer_A3.TA0 P1.1/TA0/MCLK 1 P1.1 (I/O) Timer_A3.CCI0B MCLK P1.2/TA1 2 P1.2 (I/O) Timer_A3.CCI1A Timer_A3.TA1 P1.3/TBOUTH/SVSOUT 3 P1.3 (I/O) Timer_B7.TBOUTH SVSOUT P1.4/TBCLK/SMCLK 4 P1.4 (I/O) Timer_B7.TBCLK SMCLK P1.5/TACLK/ACLK 5 P1.5 (I/O) Timer_A3.TACLK ACLK FUNCTION P1DIR.x I: 0; O: 1 0 1 I: 0; O: 1 0 1 I: 0; O: 1 0 1 I: 0; O: 1 0 1 I: 0; O: 1 0 1 I: 0; O: 1 0 1 P1SEL.x 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1
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Port P1, P1.6, P1.7, input/output with Schmitt trigger Pad Logic DVSS DVSS CAPD.x P1DIR.x
0 1
0 1 Bus Keeper EN P1.6/CA0 P1.7/CA1
P1IN.x EN Module X IN D P2CA0 P1IE.x P1IRQ.x P1IFG.x P1SEL.x P1IES.x Note: x = 6,7 Port P1 (P1.6 and P1.7) pin functions
PIN NAME (P1.X) (P1 X) P1.6/CA0 P1.7/CA1 NOTE 1: X: Dont care CONTROL BITS / SIGNALS X 6 7 P1.6 (I/O) CA0 P1.7 (I/O) CA1 FUNCTION CAPD.x 0 1 0 1 P1DIR.x I: 0; O: 1 X I: 0; O: 1 X P1SEL.x 0 X 0 X
EN Q Set
Comp_A +
0 1 CA0 0 1 CA1 P2CA1
Interrupt Edge Select
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DALLAS, TEXAS 75265

port P2, P2.0 to P2.3, P2.6 to P2.7, input/output with Schmitt trigger Pad Logic DVSS DVSS TBOUTH P2DIR.x
0 1
0 1 Bus Keeper EN P2.0/TA2 P2.1/TB0 P2.2/TB1 P2.3/TB2 P2.6/CAOUT P2.7/ADC12CLK/DMAE0
P2IE.x P2IRQ.x P2IFG.x P2SEL.x P2IES.x Note: x = 0,1,2,3,6,7 Q
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Port P2 (P2.0, P2.1, P2.2, P2.3, P2.6 and P2.7) pin functions
(P2 X) PIN NAME (P2.X) P2.0/TA2 CONTROL BITS / SIGNALS X 0 P2.0 (I/O) Timer_A3.CCI2A Timer_A3.TA2 P2.1/TB0 1 P2.1 (I/O) Timer_B7.CCI0A and Timer_B7.CCI0B Timer_B7.TB0 (see Note 1) P2.2/TB1 2 P2.2 (I/O) Timer_B7.CCI1A and Timer_B7.CCI1B Timer_B7.TB1 (see Note 1) P2.3/TB3 3 P2.3 (I/O) Timer_B7.CCI2A and Timer_B7.CCI2B Timer_B7.TB3 (see Note 1) P2.6/CAOUT P2.7/ADC12CLK/DMAE0 6 7 P2.6 (I/O) CAOUT P2.7 (I/O) ADC12CLK DMAE0 NOTE 1: Setting TBOUTH causes all Timer_B outputs to be set to high impedance. FUNCTION P2DIR.x I: 0; O: 1 0 1 I: 0; O: 1 0 1 I: 0; O: 1 0 1 I: 0; O: 1 0 1 I: 0; O: 1 1 I: 0; O: 1 1 0 P2SEL.x 0 1 1 0 1 1 0 1 1 0 1 1 0 1 0 1 1
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port P2, P2.4 to P2.5, input/output with Schmitt trigger Pad Logic DVSS DVSS DVSS P2DIR.x Direction control from Module X P2OUT.x Module X OUT P2SEL.x
0 1 0 1
Bus Keeper EN
P2.4/UCA0TXD P2.5/UCA0RXD
P2IE.x P2IRQ.x P2IFG.x P2SEL.x P2IES.x Note: x = 4,5 Q
Port P2 (P2.4 and P2.5) pin functions

PIN NAME (P2.X) (P2 X) P2.4/UCA0TXD P2.5/UCA0RXD CONTROL BITS / SIGNALS X 4 5 P2.4 (I/O) USCI_A0.UCA0TXD (see Note 1, 2) P2.5 (I/O) USCI_A0.UCA0RXD (see Note 1, 2) NOTES: 1. X: Dont care 2. When in USCI mode, P2.4 is set to output, P2.5 is set to input. FUNCTION P2DIR.x I: 0; O: 1 X I: 0; O: 1 X P2SEL.x 0 1 0 1
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port P3, P3.0 to P3.3, input/output with Schmitt trigger Pad Logic DVSS DVSS DVSS P3DIR.x
0 1
0 1 Bus Keeper EN P3.0/UCB0STE P3.1/UCB0SIMO/UCB0SDA P3.2/UCB0SOMI/UCB0SCL P3.3/UCB0CLK
P3IN.x EN Module X IN Note: x = 0,1,2,3 Port P3 (P3.0 to P3.3) pin functions

PIN NAME (P3.X) (P3 X) P3.0/UCB0STE P3.1/UCB0SIMO/ UCB0SDA P3.2/UCB0SOMI/ UCB0SCL P3.3/UCB0CLK CONTROL BITS / SIGNALS X 0 1 2 3 P3.0 (I/O) UCB0STE (see Notes 1, 2) P3.1 (I/O) UCB0SIMO/UCB0SDA (see Notes 1, 2, 3) P3.2 (I/O) UCB0SOMI/UCB0SCL (see Notes 1, 2, 3) P3.3 (I/O) UCB0CLK (see Notes 1, 2) NOTES: 1. X: Dont care 2. The pin direction is controlled by the USCI module. 3. In case the I2C functionality is selected the output drives only the logical 0 to VSS level. FUNCTION P3DIR.x I: 0; O: 1 X I: 0; O: 1 X I: 0; O: 1 X I: 0; O: 1 X P3SEL.x 0 1 0 1 0 1 0 1
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DALLAS, TEXAS 75265

port P3, P3.4 to P3.7, input/output with Schmitt trigger Pad Logic DVSS DVSS TBOUTH P3DIR.x
0 1
0 1 Bus Keeper EN P3.4/TB3 P3.5/TB4 P3.6/TB5 P3.7/TB6
P3IN.x EN Module X IN Note: x = 4,5,6,7 Port P3 (P3.4 to P3.7) pin functions

PIN NAME (P3.X) (P3 X) P3.4/TB3 CONTROL BITS / SIGNALS X 4 P3.4 (I/O) Timer_B7.CCI3A and Timer_B7.CCI3B Timer_B7.TB3 (see Note 1) P3.5/TB4 5 P3.5 (I/O) Timer_B7.CCI4A and Timer_B7.CCI4B Timer_B7.TB4 (see Note 1) P3.6/TB5 6 P3.6 (I/O) Timer_B7.CCI5A and Timer_B7.CCI5B Timer_B7.TB5 (see Note 1) P3.7/TB6 7 P3.7 (I/O) Timer_B7.CCI6A and Timer_B7.CCI6B Timer_B7.TB6 (see Note 1) NOTE 1: Setting TBOUTH causes all Timer_B outputs to be set to high impedance. FUNCTION P3DIR.x I: 0; O: 1 0 1 I: 0; O: 1 0 1 I: 0; O: 1 0 1 I: 0; O: 1 0 1 P3SEL.x 0 1 1 0 1 1 0 1 1 0 1 1
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port P4, P4.0 to P4.1, input/output with Schmitt trigger Pad Logic DVSS DVSS DVSS P4DIR.x Direction control from Module X P4OUT.x Module X OUT P4SEL.x 0 1 0 1 Bus Keeper EN P4IN.x EN Module X IN D P4.1/URXD1 P4.0/UTXD1
Note: x = 0,1 Port P4 (P4.0 to P4.1) pin functions

PIN NAME (P4.X) (P4 X) P4.0/UTXD1 P4.1/URXD1 CONTROL BITS / SIGNALS X 0 1 P4.0 (I/O) USART1.UTXD1 (see Notes 1, 2) P4.1 (I/O) USART1.URXD1 (see Notes 1, 2) NOTES: 1. X: Dont care 2. When in USART1 mode, P4.0 is set to output, P4.1 is set to input. FUNCTION P4DIR.x I: 0; O: 1 X I: 0; O: 1 X P4SEL.x 0 1 0 1
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DALLAS, TEXAS 75265

port P4, P4.2 to P4.7, input/output with Schmitt trigger Pad Logic LCDS32/36 Segment Sy DVSS P4DIR.x Direction control from Module X P4OUT.x Module X OUT P4SEL.x 0 1 0 1 Bus Keeper EN P4IN.x EN Module X IN D P4.7/UCA0RXD/S34 P4.6/UCA0TXD/S35 P4.5/UCLK1/S36 P4.4/SOMI1/S37 P4.3/SIMO1/S38 P4.2/STE1/S39
Note : x = 2,3,4,5,6,7 y = 34,35,36,37,38,39
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(P4 X) PIN NAME (P4.X) P4.2/STE1/S39 CONTROL BITS / SIGNALS X 2 P4.2 (I/O) USART1.STE1 S39 (see Note 1) P4.3/SIMO/S38 3 P4.3 (I/O) USART1.SIMO1 (see Notes 1, 2) S38 (see Note 1) P4.4/SOMI/S37 4 P4.4 (I/O) USART1.SOMI1 (see Notes 1, 2) S37 (see Note 1) P4.5/SOMI/S36 5 P4.5 (I/O) USART1.UCLK1 (see Notes 1, 2) S36 (see Note 1) P4.6/UCA0TXD/S35 6 P4.6 (I/O) USCI_A0.UCA0TXD (see Notes 1, 3) S35 (see Note 1) P4.7/UCA0RXD/S34 7 P4.7 (I/O) USCI_A0.UCA0RXD (see Notes 1, 3) S34 (see Note 1) NOTES: 1. X: Dont care 2. The pin direction is controlled by the USART1 module. 3. When in USCI mode, P4.6 is set to output, P4.7 is set to input. FUNCTION P4DIR.x I: 0; O: 1 X X I: 0; O: 1 X X I: 0; O: 1 X X I: 0; O: 1 X X I: 0; O: 1 X X I: 0; O: 1 X X P4SEL.x 0 1 X 0 1 X 0 1 X 0 1 X 0 1 X 0 1 X LCDS36 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1
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DALLAS, TEXAS 75265

port P5, P5.0, input/output with Schmitt trigger INCH=13# A13# Pad Logic
LCDS0 Segment Sy
P5DIR.x
0 1
P5OUT.x DVSS P5SEL.x
0 1 Bus Keeper EN P5.0/S1/A13/OA1I1
P5IN.x
Note: x = 0 y=1 + OA1
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Port P5 (P5.0) pin functions

CONTROL BITS / SIGNALS PIN NAME (P5.X) P5.0/S1/A13/OA1I1 X 0 FUNCTION P5.0 (I/O) (see Note 1) OAI11 (see Note 1) A13 (see Notes 1, 3) S1 enabled (see Note 1) S1 disabled (see Note 1) P5DIR.x I: 0; O: 1 0 X X X P5SEL.x 0 X 1 0 1 INCHx X X 13 X X OAPx(OA1) OANx(OA1) X 1 X X X LCDS0 0 0 X 1 1
NOTES: 1. X: Dont care 2. N/A: Not available or not applicable. 3. Setting the P5SEL.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying analog signals.
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DALLAS, TEXAS 75265

LCDS0 Segment Sy DAC12.1OPS
P5DIR.x
0 1
0 1 Bus Keeper EN P5.1/S0/A12/DAC1
P5IN.x
Note: x = 1 y=0
DVSS DAC1
0 1 2
0 if DAC 12.1AMPx = 0 and DAC 12.1OPS = 1 1 if DAC 12.1AMPx = 1 and DAC 12.1OPS = 1 2 if DAC 12.1AMPx > 1 and DAC 12.1OPS = 1
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(P5 X) PIN NAME (P5.X) P5.1/S0/A12/DAC1 CONTROL BITS / SIGNALS X 1 FUNCTION P5.1 (I/O) (see Note 1) DAC1 high impedance (see Note 1) DVSS (see Note 1) DAC1 output (see Note 1) A12 (see Notes 1, 2) S0 enabled (see Note 1) S0 disabled (see Note 1) P5DIR.x I: 0; O: 1 X X X X X X P5SEL.x 0 X X X 1 0 1 INCHx X X X X 12 X X DAC12.1OPS 0 1 1 1 0 0 0 DAC12.1AMPx X 0 1 >1 X X X LCDS0 0 X X X 0 1 1
NOTES: 1. X: Dont care 2. Setting the P5SEL.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying analog signals.
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port P5, P5.2 to P5.4, input/output with Schmitt trigger Pad Logic
LCD Signal DVSS P5DIR.x
0 1
0 1 Bus Keeper EN P5.2/COM1 P5.3/COM2 P5.4/COM3
P5IN.x
Note: x = 2,3,4

(P5 X) PIN NAME (P5.X) P5.2/COM1 P5.3/COM2 P5.4/COM3 NOTE 1: X: Dont care CONTROL BITS / SIGNALS X 2 3 4 P5.2 (I/O) COM1 (see Note 1) P5.3 (I/O) COM2 (see Note 1) P5.4 (I/O) COM3 (see Note 1) FUNCTION P5DIR.x I: 0; O: 1 X I: 0; O: 1 X I: 0; O: 1 X P5SEL.x 0 1 0 1 0 1
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port P5, P5.5 to P5.7, input/output with Schmitt trigger Pad Logic
LCD Signal DVSS P5DIR.x
0 1
0 1 Bus Keeper EN P5.5/R03 P5.6/LCDREF/R13 P5.7/R03
P5IN.x
Note: x = 5,6,7

(P5 X) PIN NAME (P5.X) P5.5/R03 P5.6/LCDREF/R13 P5.7/R03 CONTROL BITS / SIGNALS X 5 6 7 P5.5 (I/O) R03 (see Note 1) P5.6 (I/O) R13 or LCDREF (see Notes 1, 2) P5.7 (I/O) R03 (see Note 1) FUNCTION P5DIR.x I: 0; O: 1 X I: 0; O: 1 X I: 0; O: 1 X P5SEL.x 0 1 0 1 0 1
NOTES: 1. X: Dont care 2. External reference for the LCD_A charge pump is applied when VLCDREFx = 01. Otherwise R13 is selected.
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DALLAS, TEXAS 75265

port P6, P6.0, P6.2, and P6.4, input/output with Schmitt trigger INCH=0/2/4# Ay# Pad Logic
P6DIR.x
0 1
0 1 Bus Keeper EN
P6.0/A0/OA0I0 P6.2/A2/OA0I1 P6.4/A4/OA1I0
P6IN.x Note: x = 0, 2, 4 y = 0, 1 # = Signal from or to ADC12 + OA0/1 Port P6 (P6.0, P6.2, and P6.4) pin functions
CONTROL BITS / SIGNALS PIN NAME (P6.X) P6.0/A0/OA0I0 X 0 FUNCTION P6.0 (I/O) (see Note 1) OA0I0 (see Note 1) A0 (see Notes 1, 3) P6.2/A2/OA0I1 2 P6.2 (I/O) (see Note 1) OA0I1 (see Note 1) A2 (see Notes 1, 3) P6.4/A4/OA1I0 4 P6.4 (I/O) (see Note 1) OA1I0 (see Note 1) A4 (see Notes 1, 3) P6DIR.x I: 0; O: 1 0 X I: 0; O: 1 0 X I: 0; O: 1 0 X P6SEL.x 0 X 1 0 X 1 0 X 1 OAPx (OA0) OANx (OA0) X 0 X X 1 X X X X OAPx (OA1) OANx(OA1) X X X X X X X 0 X INCHx X X 0 X X 2 X X 4
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port P6, P6.1, P6.3, and P6.5 input/output with Schmitt trigger INCH=1/3/5# Ay# Pad Logic
P6DIR.x
0 1
0 1 Bus Keeper EN
P6.1/A1/OA0O P6.3/A3/OA1O P6.5/A5/OA2O
P6IN.x
OAPMx> 0 OAADC1 + OAy
Note: x = 1, 3, 5 y = 0, 1, 2 # = Signal from or to ADC12
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Port P6 (P6.1, P6.3, and P6.5) pin functions

(P6 X) PIN NAME (P6.X) P6.1/A1/OA0O CONTROL BITS / SIGNALS X 1 FUNCTION P6.1 (I/O) (see Note 1) OA0O (see Notes 1, 4) A1 (see Notes 1, 3) P6.3/A3/OA1O 3 P6.3 (I/O) (see Note 1) OA1O (see Notes 1, 4) A3 (see Notes 1, 3) P6.5/A5/OA2O 5 P6.5 (I/O) (see Note 1) OA2O (see Notes 1, 4) A5 (see Notes 1, 3) P6DIR.x I: 0; O: 1 X X I: 0; O: 1 X X I: 0; O: 1 X X P6SEL.x 0 X 1 0 X 1 0 X 1 OAADC1 X 1 X X 1 X X 1 X OAPMx 0 >0 0 0 >0 0 0 >0 0 INCHx X X 1 X X 3 X X 5
NOTES: 1. X: Dont care 2. N/A: Not available or not applicable. 3. Setting the P6SEL.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. 4. Setting the OAADC1 bit or setting OAFCx = 00 will cause the operational amplifier to be present at the pin as well as internally connected to the corresponding ADC12 input.
DALLAS, TEXAS 75265
83

P6DIR.x
0 1
P6.6/A6/DAC0/OA2I0
P6OUT.x DVSS P6SEL.x DAC12.0AMP > 0 DAC12.0OPS P6IN.x
0 1 Bus Keeper EN
Note: x = 6 # = Signal from or to ADC12
+ OA2
DVSS DAC0
0 1 2
0 if DAC12.0AMPx= 0 and DAC 12.0OPS = 0 1 if DAC12.0AMPx= 1 and DAC 12.0OPS = 0 2 if DAC12.0AMPx> 1 and DAC 12.0OPS = 0
84
DALLAS, TEXAS 75265


CONTROL BITS / SIGNALS PIN NAME (P6.X) P6.6/A6/DAC0/OA2I0 X 6 FUNCTION P6.6 (I/O) (see Note 1) DAC0 high impedance (see Note 1) DVSS (see Note 1) DAC0 output (see Note 1) A6 (see Notes 1, 2) OA2I0 (see Note 1) P6DIR.x I: 0; O: 1 X X X X 0 P6SEL.x 0 X X X 1 X INCHx X X X X 6 0 DAC12.0OPS 1 0 0 0 X X DAC12.0AMPx X 0 1 >1 X X OAPx (OA2) OANx (OA2) X X X X X 0
NOTES: 1. X: Dont care 2. Setting the P6SEL.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying analog signals.
DALLAS, TEXAS 75265
85

port P6, P6.7, input/output with Schmitt trigger To SVS Mux # INCH=7 A7# Pad Logic
P6DIR.x
0 1
P6OUT.x DVSS P6SEL.x VLD =15 DAC12.1AMP > 0 DAC12.1OPS
0 1 Bus Keeper EN P6.7/A7/DAC1/SVSIN
P6IN.x
Note: x = 7 # = Signal from or to ADC12
DVSS DAC1
0 1 2
0 if DAC12.1AMPx = 0 and DAC 12.1OPS = 0 1 if DAC12.1AMPx = 1 and DAC 12.1OPS = 0 2 if DAC12.1AMPx > 1 and DAC 12.1OPS = 0
86
DALLAS, TEXAS 75265


(P6 X) PIN NAME (P6.X) P6.7/A7/DAC1/SVSIN CONTROL BITS / SIGNALS X 7 FUNCTION P6.7 (I/O) (see Note 1) DAC1 high impedance (see Note 1) DVSS (see Note 1) DAC1 output (see Note 1) A7 (see Notes 1, 2) SVSIN (see Notes 1,3) P6DIR.x I: 0; O: 1 X X X X 0 P6SEL.x 0 X X X 1 1 INCHx X X X X 7 0 DAC12.1OPS 1 0 0 0 X 1 DAC12.1AMPx X 0 1 >1 X X
NOTES: 1. X: Dont care 2. Setting the P6SEL.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying analog signals. 3. Setting VLDx = 15 will also cause the external SVSIN to be used. In this case, the P6SEL.x bit is a do not care.
DALLAS, TEXAS 75265
87

port P7, P7.0 to P7.3, input/output with Schmitt trigger Pad Logic LCDS28/32 Segment Sy DVSS P7DIR.x Direction control from Module X P7OUT.x Module X OUT P7SEL.x 0 1 0 1 Bus Keeper EN P7IN.x EN Module X IN Note: x = 0, 1, 2, 3 y = 30, 31, 32, 33 D P7.3/UCA0CLK/S30 P7.2/UCA0SOMI/S31 P7.1/UCA0SIMO/S32 P7.0/UCA0STE/S33
88
DALLAS, TEXAS 75265


(P7 X) PIN NAME (P7.X) P7.0/UCA0STE/S33 CONTROL BITS / SIGNALS X 0 P7.0 (I/O) USCI_A0.UCA0STE (see Notes 1, 2) S33 (see Note 1) P7.1/UCA0SIMO/S32 1 P7.1 (I/O) USCI_A0.UCA0SIMO (see Notes 1, 2) S32 (see Note 1) P7.2/UCA0SOMI/S31 2 P7.2 (I/O) USCI_A0.UCA0SOMI (see Notes 1, 3) S31 (see Note 1) P7.3/UCA0CLK/S30 3 P7.3 (I/O) USCI_A0.UCA0CLK (see Notes 1, 3) S30 (see Note 1) NOTES: 1. X: Dont care 2. The pin direction is controlled by the USCI module. 3. The pin direction is controlled by the USCI module. FUNCTION P7DIR.x I: 0; O: 1 X X I: 0; O: 1 X X I: 0; O: 1 X X I: 0; O: 1 X X P7SEL.x 0 1 X 0 1 X 0 1 X 0 1 X LCDS32 0 0 1 0 0 1 0 0 1 0 0 1
DALLAS, TEXAS 75265
89

port P7, P7.4 to P7.7, input/output with Schmitt trigger Pad Logic LCDS24/28 Segment Sy DVSS P7DIR.x 0 1 P7OUT.x DVSS P7SEL.x 0 1 Bus Keeper EN P7IN.x P7.7/S26 P7.6/S27 P7.5/S28 P7.4/S29
Note: x = 4, 5, 6, 7 y = 26, 27, 28, 29

PIN NAME (P7.X) (P7 X) P7.4/S29 P7.5/S28 P7.6/S27 P7.7/S26 NOTE 1: X: Dont care CONTROL BITS / SIGNALS X 4 5 6 7 P7.4 (I/O) S29 (see Note 1) P7.5 (I/O) S28 (see Note 1) P7.6 (I/O) S27 (see Note 1) P7.7 (I/O) S26 (see Note 1) FUNCTION P7DIR.x I: 0; O: 1 X I: 0; O: 1 X I: 0; O: 1 X I: 0; O: 1 X P7SEL.x 0 X 0 X 0 X 0 X LCDS28 0 1 0 1 0 1 0 1
90
DALLAS, TEXAS 75265

port P8, P8.0 to P8.7, input/output with Schmitt trigger Pad Logic LCDS16/20/24 Segment Sy DVSS P8DIR.x 0 1 P8OUT.x DVSS P8SEL.x 0 1 Bus Keeper EN P8IN.x P8.7/S18 P8.6/S19 P8.5/S20 P8.4/S21 P8.3/S22 P8.2/S23 P8.1/S24 P8.0/S25
Note: x = 0,1,2,3,4,5,6,7 y = 25,24,23,22,21,20,19,18
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91


(P8 X) PIN NAME (P8.X) P8.0/S18 P8.1/S19 P8.2/S20 P8.3/S21 P8.4/S22 P8.5/S23 NOTE 1: X: Dont care CONTROL BITS / SIGNALS X 0 0 2 3 4 5 P8.0 (I/O) S18 (see Note 1) P8.0 (I/O) S19 (see Note 1) P8.2 (I/O) S20 (see Note 1) P8.3 (I/O) S21 (see Note 1) P8.4 (I/O) S22 (see Note 1) P8.5 (I/O) S23 (see Note 1) FUNCTION P8DIR.x I: 0; O: 1 X I: 0; O: 1 X I: 0; O: 1 X I: 0; O: 1 X I: 0; O: 1 X I: 0; O: 1 X P8SEL.x 0 X 0 X 0 X 0 X 0 X 0 X LCDS16 0 1 0 1 0 1 0 1 0 1 0 1

PIN NAME (P8.X) (P8 X) P8.6/S24 P8.7/S25 NOTE 1: X: Dont care CONTROL BITS / SIGNALS X 6 7 P8.6 (I/O) S24 (see Note 1) P8.7 (I/O) S25 (see Note 1) FUNCTION P8DIR.x I: 0; O: 1 X I: 0; O: 1 X P8SEL.x 0 X 0 X LCDS24 0 1 0 1
92
DALLAS, TEXAS 75265

port P9, P9.0 to P9.7, input/output with Schmitt trigger Pad Logic LCDS8/12/16 Segment Sy DVSS P9DIR.x 0 1 P9OUT.x DVSS P9SEL.x 0 1 Bus Keeper EN P9IN.x P9.7/S10 P9.6/S11 P9.5/S12 P9.4/S13 P9.3/S14 P9.2/S15 P9.1/S16 P9.0/S17
Note: x = 0,1,2,3,4,5,6,7 y = 17,16,15,14,13,12,11,10
DALLAS, TEXAS 75265
93


(P9 X) PIN NAME (P9.X) P9.0/S17 P9.1/S16 P9.2/S20 P9.3/S21 P9.4/S22 P9.5/S23 P9.6/S24 P9.7/S25 NOTE 1: X: Dont care CONTROL BITS / SIGNALS X 0 1 2 3 4 5 6 7 P9.0 (I/O) S17 (see Note 1) P9.1 (I/O) S16 (see Note 1) P9.2 (I/O) S15 (see Note 1) P9.3 (I/O) S14 (see Note 1) P9.4 (I/O) S13 (see Note 1) P9.5 (I/O) S12 (see Note 1) P9.6 (I/O) S11 (see Note 1) P9.7 (I/O) S10 (see Note 1) FUNCTION P9DIR.x I: 0; O: 1 X I: 0; O: 1 X I: 0; O: 1 X I: 0; O: 1 X I: 0; O: 1 X I: 0; O: 1 X I: 0; O: 1 X I: 0; O: 1 X P9SEL.x 0 X 0 X 0 X 0 X 0 X 0 X 0 X 0 X LCDS16 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
94
DALLAS, TEXAS 75265

port P10, P10.0 to P10.5, input/output with Schmitt trigger Pad Logic LCDS4/8 Segment Sy DVSS P10DIR.x 0 1 P10OUT.x DVSS P10SEL.x 0 1 Bus Keeper EN P10IN.x P10.5/S4 P10.4/S5 P10.3/S6 P10.2/S7 P10.1/S8 P10.0/S9
Note: x = 0,1,2,3,4,5 y = 9,8,7,6,5,4

PIN NAME (P10 (P10.X) X) P10.0/S8 P10.1/S7 P10.2/S7 P10.3/S6 P10.4/S5 P10.5/S4 NOTE 1: X: Dont care CONTROL BITS / SIGNALS X 0 1 2 3 4 5 P10.0 (I/O) S8 (see Note 1) P10.1 (I/O) S7 (see Note 1) P10.2 (I/O) S7 (see Note 1) P10.3 (I/O) S6 (see Note 1) P10.4 (I/O) S5 (see Note 1) P10.5 (I/O) S4 (see Note 1) FUNCTION P10DIR.x I: 0; O: 1 X I: 0; O: 1 X I: 0; O: 1 X I: 0; O: 1 X I: 0; O: 1 X I: 0; O: 1 X P10SEL.x 0 X 0 X 0 X 0 X 0 X 0 X LCDS8 0 1 0 1 0 1 0 1 0 1 0 1
DALLAS, TEXAS 75265
95

LCDS0 Segment Sy
P10DIR.x
0 1
0 1 Bus Keeper EN P10.6/S3/A15
P10IN.x Note: x = 6 y =3

PIN NAME (P10 (P10.X) X) P10.6/S3/A15 CONTROL BITS / SIGNALS X 6 FUNCTION P5.0 (I/O) (see Note 1) A15 (see Notes 1, 3) S3 enabled (see Note 1) S3 disabled (see Note 1) P10DIR.x I: 0; O: 1 X X X P10SEL.x 0 1 0 1 INCHx X 15 X X LCDS0 0 0 1 1
96
DALLAS, TEXAS 75265

LCDS0 Segment Sy
P10DIR.x
0 1
0 1 Bus Keeper EN P10.7/S2/A14/OA2I1
P10IN.x
Note: x = 7 y= 2 + OA2
DALLAS, TEXAS 75265
97


CONTROL BITS / SIGNALS PIN NAME (P10.X) P10.7/S2/A14/OA2I1 X 7 FUNCTION P10.7 (I/O) (see Note 1) A14 (see Notes 1, 3) OA2I1 (see Notes 1, 3) S2 enabled (see Note 1) S2 disabled (see Note 1) P10DIR.x I: 0; O: 1 X 0 X X P10SEL.x 0 1 X 0 1 INCHx X 14 X X X OAPx (OA1) OANx (OA1) X X 1 X X LCDS0 0 0 0 1 1
98
DALLAS, TEXAS 75265

VeREF+/DAC0
DAC12.0OPS DAC0_2_OA 1 0 P6.6/A6/DAC0/OA2I0
Reference Voltage to DAC1
Reference Voltage to ADC12
Reference Voltage to DAC0
Ve REF+ /DAC0
0, if DAC12CALON = 0 DAC12AMPx>1 AND DAC12OPS=1

+ 1 0
1, if DAC12AMPx>1 1, if DAC12AMPx=1 DAC12OPS

#
If the reference of DAC0 is taken from pin VeREF+ /DAC0, unpredictable voltage levels will be on pin. In this situation, the DAC0 output is fed back to its own reference input.
DALLAS, TEXAS 75265
99

JTAG pins TMS, TCK, TDI/TCLK, TDO/TDI, input/output with Schmitt trigger or output
TDO Controlled by JTAG Controlled by JTAG JTAG Controlled by JTAG TDI DVCC TDO/TDI
Burn and Test Fuse TDI/TCLK Test and Emulation Module TMS DVCC TCK TCK RST/NMI TMS DVCC
Tau ~ 50 ns Brownout G D U S D U S
TCK
100
DALLAS, TEXAS 75265

JTAG fuse check mode

MSP430 devices that have the fuse on the TDI/TCLK terminal have a fuse check mode that tests the continuity of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check current (I(TF) ) of 1 mA at 3 V can flow from the TDI/TCLK pin to ground if the fuse is not burned. Care must be taken to avoid accidentally activating the fuse check mode and increasing overall system power consumption. Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if the TMS is being held low during power up. The second positive edge on the TMS pin deactivates the fuse check mode. After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the fuse check mode has the potential to be activated. The fuse check current only flows when the fuse check mode is active and the TMS pin is in a low state (see Figure 37). Therefore, the additional current flow can be prevented by holding the TMS pin high (default condition). The JTAG pins are terminated internally and therefore do not require external termination.
Time TMS Goes Low After POR TMS
I(TF) ITDI/TCLK
Figure 37. Fuse Check Mode Current
DALLAS, TEXAS 75265
101

Data Sheet Revision History

Literature Number SLAS508 SLAS508A SLAS508B SLAS508C SLAS508D Preliminary Product Preview datasheet release Production Data data sheet release Changed power consumption values in features (page 1) Changed tVALID,MO, tHD,SI, and tVALID,SO values (page 43) Changed I(AM) values for CG461x (page 29) Added ZQW package information Changed power consumption values for Standby and Off Modes in features (page 1) Corrected description of P7.3/UCA0CLK/S30 terminal (page 7) Clarified test conditions in recommended operating conditions table (page 30) Changed I(AM) values for CG461x and all TYP values for I(LPM3) in supply current into AVCC + DVCC table (page 31) Clarified test conditions in DCO table (page 42) Clarified test conditions in USART table (page 48) Clarified test conditions in operational amplifier OA, supply specifications table (page 59) Clarified test conditions in operational amplifier OA, input/output specifications table (page 60) Removed preview notice for MSP430CG461x in PZ package. Removed preview notice for all devices in ZQW package. Added operational amplifier OA feedback network, noninverting amplifier mode (OAFCx = 4) table and operational amplifier OA feedback network, inverting amplifier mode (OAFCx = 6) table (page 62) Changed limits on td(SVSon) parameter (page 40) Summary
SLAS508E
SLAS508F SLAS508G SLAS508H SLAS508I
NOTE: Page and figure numbers refer to the respective document revision.
102
DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
1-Mar-2011
PACKAGING INFORMATION
Orderable Device MSP430FG4616IPZ MSP430FG4616IPZR MSP430FG4616IZQW Status
(1)
Package Type Package Drawing LQFP LQFP BGA MICROSTAR JUNIOR BGA MICROSTAR JUNIOR BGA MICROSTAR JUNIOR LQFP LQFP BGA MICROSTAR JUNIOR BGA MICROSTAR JUNIOR BGA MICROSTAR JUNIOR LQFP LQFP BGA MICROSTAR JUNIOR PZ PZ ZQW
Pins 100 100 113
Package Qty 90 1000 250
Eco Plan
(2)
Lead/ Ball Finish
MSL Peak Temp
(3)
Samples (Requires Login)
ACTIVE ACTIVE ACTIVE
Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)
CU NIPDAU Level-3-260C-168 HR CU NIPDAU Level-3-260C-168 HR SNAGCU Level-3-260C-168 HR
MSP430FG4616IZQWR
ACTIVE
ZQW
113
2500
SNAGCU
Level-3-260C-168 HR
MSP430FG4616IZQWT
ACTIVE
ZQW
113
250
SNAGCU
Level-3-260C-168 HR
MSP430FG4617IPZ MSP430FG4617IPZR MSP430FG4617IZQW
PZ PZ ZQW
100 100 113
90 1000 250
MSP430FG4617IZQWR
ACTIVE
ZQW
113
2500
SNAGCU
Level-3-260C-168 HR
MSP430FG4617IZQWT
ACTIVE
ZQW
113
250
SNAGCU
Level-3-260C-168 HR
PZ PZ ZQW
100 100 113
90 1000 250
Addendum-Page 1
www.ti.com
1-Mar-2011
Orderable Device MSP430FG4618IZQWR
Status
(1)
Package Type Package Drawing BGA MICROSTAR JUNIOR BGA MICROSTAR JUNIOR LQFP LQFP BGA MICROSTAR JUNIOR BGA MICROSTAR JUNIOR BGA MICROSTAR JUNIOR ZQW
Pins 113
Package Qty 2500
Eco Plan
(2)
Lead/ Ball Finish SNAGCU
MSL Peak Temp
(3)
Samples (Requires Login)
ACTIVE
Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)
Level-3-260C-168 HR
MSP430FG4618IZQWT
ACTIVE
ZQW
113
250
SNAGCU
Level-3-260C-168 HR
PZ PZ ZQW
100 100 113
90 1000 250
MSP430FG4619IZQWR
ACTIVE
ZQW
113
2500
SNAGCU
Level-3-260C-168 HR
MSP430FG4619IZQWT
ACTIVE
ZQW
113
250
SNAGCU
Level-3-260C-168 HR
(1)
The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 2
www.ti.com
1-Mar-2011
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
PACKAGE MATERIALS INFORMATION

www.ti.com 24-Aug-2011
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins Type Drawing BGA MI CROSTA R JUNI OR BGA MI CROSTA R JUNI OR BGA MI CROSTA R JUNI OR BGA MI CROSTA R JUNI OR BGA MI CROSTA R JUNI OR BGA MI CROSTA R JUNI ZQW 113
SPQ
Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 330.0 16.4 7.3
B0 (mm) 7.3
K0 (mm) 1.5
P1 (mm) 12.0
W Pin1 (mm) Quadrant 16.0 Q1
MSP430FG4616IZQWR
2500
MSP430FG4616IZQWT
ZQW
113
250
330.0
16.4
7.3
7.3
1.5
12.0
16.0
Q1
MSP430FG4617IZQWR
ZQW
113
2500
330.0
16.4
7.3
7.3
1.5
12.0
16.0
Q1
MSP430FG4617IZQWT
ZQW
113
250
330.0
16.4
7.3
7.3
1.5
12.0
16.0
Q1
MSP430FG4618IZQWR
ZQW
113
2500
330.0
16.4
7.3
7.3
1.5
12.0
16.0
Q1
MSP430FG4618IZQWT
ZQW
113
250
330.0
16.4
7.3
7.3
1.5
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION

www.ti.com 24-Aug-2011
Device
Package Package Pins Type Drawing OR
SPQ
Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 330.0 16.4 7.3
B0 (mm)
K0 (mm)
P1 (mm)
W Pin1 (mm) Quadrant
MSP430FG4619IZQWT
BGA MI CROSTA R JUNI OR
ZQW
113
250
7.3
1.5
12.0
16.0
Q1
*All dimensions are nominal
Device MSP430FG4616IZQWR MSP430FG4616IZQWT MSP430FG4617IZQWR MSP430FG4617IZQWT MSP430FG4618IZQWR MSP430FG4618IZQWT MSP430FG4619IZQWT
Package Type BGA MICROSTAR JUNIOR BGA MICROSTAR JUNIOR BGA MICROSTAR JUNIOR BGA MICROSTAR JUNIOR BGA MICROSTAR JUNIOR BGA MICROSTAR JUNIOR BGA MICROSTAR JUNIOR
Package Drawing ZQW ZQW ZQW ZQW ZQW ZQW ZQW
Pins 113 113 113 113 113 113 113
SPQ 2500 250 2500 250 2500 250 250
Length (mm) 333.2 333.2 333.2 333.2 333.2 333.2 333.2
Width (mm) 345.9 345.9 345.9 345.9 345.9 345.9 345.9
Height (mm) 28.6 28.6 28.6 28.6 28.6 28.6 28.6
Pack Materials-Page 2
MECHANICAL DATA
MTQF013A OCTOBER 1994 REVISED DECEMBER 1996
PZ (S-PQFP-G100)
PLASTIC QUAD FLATPACK
0,50 75 51
0,27 0,17
0,08 M
76
50
100
26
0,13 NOM
1 12,00 TYP 14,20 SQ 13,80 16,20 SQ 15,80 1,45 1,35
25 Gage Plane
0,05 MIN
0,25 0 7
0,75 0,45 Seating Plane
1,60 MAX
0,08
4040149 /B 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026
DALLAS, TEXAS 75265
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MSP430xG461x MIXED SIGNAL MICROCONTROLLER

SLAS508I APRIL 2006 REVISED MARCH 2011

D Low Supply-Voltage Range: 1.8 V to 3.6 V D Ultralow-Power Consumption:

D Universal Serial Communication Interface

Copyright 2011, Texas Instruments Incorporated

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

MSP430xG461x MIXED SIGNAL MICROCONTROLLER

DEVELOPMENT TOOL SUPPORT

D Debugging and Programming Interface

D Debugging and Programming Interface with Target Board

D Standalone Target Board

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

MSP430xG461x MIXED SIGNAL MICROCONTROLLER

pin designation, MSP430xG461xIPZ

TDI/TCLK TDO/TDI XT2IN XT2OUT P1.0/TA0 P1.1/TA0/MCLK P1.2/TA1

P6.2/A2/OA0I1 P6.1/A1/OA0O P6.0/A0/OA0I0 RST/NMI TCK TMS

AVCC DV SS1 AVSS

P2.0/TA2 P2.1/TB0 P2.2/TB1

MSP430xG4616IPZ MSP430xG4617IPZ MSP430xG4618IPZ MSP430xG4619IPZ

P9.3/S14 P9,2/S15 P9.1/S16 P9.0/S17 P8.7/S18 P8.6/S19

P8.5/S20 P8.4/S21 P8.3/S22 P8.2/S23

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

MSP430xG461x MIXED SIGNAL MICROCONTROLLER

pin designation, MSP430xG461xIZQW (top view)

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

MSP430xG461x MIXED SIGNAL MICROCONTROLLER

functional block diagram

Oscillators FLL+ MCLK

Flash (FG) ROM (CG) 120kB 116kB 92kB 92kB

RAM 4kB 8kB 8kB 4kB

ADC12 12 Bit 12 Channels

DAC12 12 Bit 2 Channels Voltage out

OA0, OA1, OA2 3 Op Amps

Ports P1/P2 Comparator _A 2x8 I/O Interrupt capability

Ports P3/P4 P5/P6 4x8 I/O

Ports P7/P8 P9/P10 4x8/2x16 I/O

8MHz CPUX incl. 16 Registers

DMA Controller 3 Channels

Enhanced Emulation (FG only ) JTAG Interface

Brownout Protection SVS /SVM

Hardware Multiplier MPY, MPYS , MAC, MACS

LCD_A 160 Segments 1,2,3,4 Mux

USCI_A0: UART , IrDA, SPI USCI_B0: SPI, I2C

USART 1 UART, SPI

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

MSP430xG461x MIXED SIGNAL MICROCONTROLLER

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

MSP430xG461x MIXED SIGNAL MICROCONTROLLER

Terminal Functions (Continued)

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

MSP430xG461x MIXED SIGNAL MICROCONTROLLER

Terminal Functions (Continued)

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

MSP430xG461x MIXED SIGNAL MICROCONTROLLER