ENGI 242/ELEC 222 Updated 23 February 2005

Voltage Divider Bias

ENGI 242
ELEC 222

BJT Biasing 3
For the Voltage Divider Bias Configurations
• Draw Equivalent Input circuit
• Draw Equivalent Output circuit
• Write necessary KVL and KCL Equations
• Determine the Quiescent Operating Point
– Graphical Solution using Load lines
– Computational Analysis
• Design and test design using a computer simulation

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Voltage Divider Bias 1

ENGI 242/ELEC 222 Updated 23 February 2005

Voltage-divider bias configuration

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Voltage Divider Input Circuit Approximate Analysis

This method is valid only if R2 ≤ .1 β RE
Under these conditions RE does not significantly load R2 and it may be ignored:
IB << I1 and I2 and I1 ≅ I2 Therefore:
⎛ R2 ⎞
VB = VCC ⎜ ⎟
⎝ R1+R2 ⎠
We may apply KVL to the input, which gives us:
-VB + VBE + IE RE = 0
Solving for IE we get:

VB - VBE
IE =
RE

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Voltage Divider Bias 2

ENGI 242/ELEC 222 Updated 23 February 2005

Input Circuit Exact Analysis

This method is always valid must be used when R2 > .1 β RE
Perform Thevenin’s Theorem
Open the base lead of the transistor, and the Voltage Divider bias circuit is:
⎛ R2 ⎞
VTH = VCC ⎜ ⎟
⎝ R1+R2 ⎠
Calculate RTH
We may apply KVL to the input, which gives us:
-VTH + IB RTH + VBE + IE RE = 0
Since IE = (β + 1) IB
RTH
-VTH + IE + VBE + IE RE = 0
β+1
Solving for IE we obtain:
VTH - VBE
IE =
RTH
+ RE
β+1

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Redrawing the input circuit for the network

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Voltage Divider Bias 3

ENGI 242/ELEC 222 Updated 23 February 2005

Determining VTH

⎛ R2 ⎞
VTH = VCC ⎜ ⎟
⎝ R1 + R2 ⎠

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Determining RTH

R1 R2
RTH =
R1 + R2

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Voltage Divider Bias 4

ENGI 242/ELEC 222 Updated 23 February 2005

The Thévenin Equivalent Circuit

Note that VE = VB – VBE and IE = (β + 1)IB

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Input Circuit Exact Analysis

We may apply KVL to the input, which gives us:

-VTH + IB RTH + VBE + IE RE = 0
Since IE = (β + 1) IB

RTH
-VTH + IE + VBE + IE RE = 0
β+1
Solving for IE we obtain:
VTH - VBE
IE =
RTH
+ RE
β+1

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Voltage Divider Bias 5

ENGI 242/ELEC 222 Updated 23 February 2005

Collector-Emitter Loop

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Collector-Emitter (Output) Loop

Applying Kirchoff’s voltage law: - VCC + IC RC + VCE + IE RE = 0

Assuming that IE ≅ IC and solving for VCE: IC = VCC - VCE

RC + RE
Solve for VE: V E = IE R E

Solve for VC: VC = VCC - IC RC

or
VC = VCE + IE RE

Solve for VB: VB = VCC - IB RB

or
VB = VBE + IE RE

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Voltage Divider Bias 6

ENGI 242/ELEC 222 Updated 23 February 2005

Voltage Divider Bias Example 1

VCC = 22V
R1 = 39kΩ
R2 = 3.9kΩ
RC = 10kΩ
RE = 1.5kΩ
β = 140

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Voltage Divider Bias Example 2

VCC = 18V
R1 = 39kΩ
R2 = 8.2kΩ
RC = 3.3kΩ
RE = 1kΩ
β = 120

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Voltage Divider Bias 7

ENGI 242/ELEC 222 Updated 23 February 2005

Voltage Divider Bias Example 3

VCC = 16V
R1 = 62kΩ
R2 = 9.1kΩ
RC = 3.9kΩ
RE = .68kΩ
β = 80

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Design of CE Amplifier with Voltage Divider Bias

1. Select a value for VCC
2. Determine the value of β from spec sheet or family of curves
3. Select a value for ICQ
4. Let VCE = ½ VCC (typical operation, 0.4 VCC ≤ VC ≤ 0.6 VCC )
5. Let VE = 0.1 VCC (for good operation, 0.1 VCC ≤ VE ≤ 0.2 VCC )
6. Calculate RE and RC
7. Let R2 ≤ 0.1 β RE (for this calculation, use low value for β)
8. Calculate R1
⎛ VCC - VB ⎞
R1 = R2 ⎜ ⎟
⎝ VB ⎠

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Voltage Divider Bias 8

ENGI 242/ELEC 222 Updated 23 February 2005

CE Amplifier Design
• Design a Common Emitter Amplifier with Voltage Divider
Bias for the following parameters:
VCC = 24V
IC = 5mA
VE = .1VCC
VC = .55VCC
β = 135

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Voltage Divider Bias 9

ENGI 242/ELEC 222 Updated 23 February 2005

CE Amplifier Design

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CE Amplifier Design Voltage Divider Bias

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Voltage Divider Bias 10

ENGI 242/ELEC 222 Updated 23 February 2005

Collector Feedback Bias

ENGI 242
ELEC 222

BJT Biasing 4
For the Collector Feedback Bias Configuration:
• Draw Equivalent Input circuit
• Draw Equivalent Output circuit
• Write necessary KVL and KCL Equations
• Determine the Quiescent Operating Point
– Graphical Solution using Loadlines
– Computational Analysis
• Design and test design using a computer simulation

23 February 2005 ENGI 242/ELEC 222 22

Voltage Divider Bias 11

ENGI 242/ELEC 222 Updated 23 February 2005

DC Bias with Collector (Voltage) Feedback

Another way to improve the stability of a bias circuit is to add a feedback path
from collector to base
In this bias circuit the Q-point is only slightly dependent on the transistor β
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Base – Emitter Loop Solve for IB

Applying Kirchoff’s voltage law: -VCC + IC′RC + IBRB + VBE + IERE = 0

Note: IC′ = IE = IC + IB
Since IE = (β + 1) IB then: -VCC + (β + 1)IB RC + IBRB + VBE (β + 1)IBRE = 0

Simplifying and solving for IB: IB = VCC - VBE

RB + (β + 1) (RC + RE)
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Voltage Divider Bias 12

ENGI 242/ELEC 222 Updated 23 February 2005

Base – Emitter Loop Solve for IE

Applying Kirchoff’s voltage law: -VCC + IERC + IBRB + VBE + IERE = 0

Since IE = (β + 1) IB then: RB
-VCC + IE RC + IE + VBE + IERE = 0
(β + 1)
VCC - VBE
Simplifying and solving for IE: IE =
RB
+ (RC + RE)
(β + 1)
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Collector Emitter Loop

Applying Kirchoff’s voltage law: IE RE + VCE + IC′RC – VCC = 0

Since IC′ = IE and IE = (β + 1) IB: IE(RC + RE) + VCE – VCC =0
Solving for VCE: VCE = VCC – IE (RE + RC)

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Voltage Divider Bias 13

ENGI 242/ELEC 222 Updated 23 February 2005

Network Example

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Network Example

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Voltage Divider Bias 14

ENGI 242/ELEC 222 Updated 23 February 2005

Collector feedback with RE = 0Ω

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Design of CE Amplifier with Collector Feedback Bias

1. Select a value for VCC
2. Determine the value of β from spec sheet or family of curves
3. Select a value for IEQ
4. Let VCE = ½ VCC (typical operation, 0.4 VCC ≤ VC ≤ 0.6 VCC )
5. Let VE = 0.1 VCC (for good operation, 0.1 VCC ≤ VE ≤ 0.2 VCC )
6. Calculate RE, RC and RB
.1VCC
VE = .1VCC RE =
IE
VCC - VCQ VCC - .6VCC .4VCC
RC = = ; RC =
IE IE IE
VCC - IERC - VBE - IERE VCC - IE (RC + RE) - 0.7V
RB = ; RB =
IE IE
β +1 β +1

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Voltage Divider Bias 15

ENGI 242/ELEC 222 Updated 23 February 2005

Common Emitter Bias

with Dual Supplies

Voltage Divider Bias with Dual Power Supply

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Voltage Divider Bias 16

ENGI 242/ELEC 222 Updated 23 February 2005

Voltage Divider Bias with Dual Power Supply

Input Circuit Find VTH and RTH

⎛ R2 ⎞
VTH1 = VCC ⎜ ⎟
⎝ R1 + R2 ⎠
(Note VEE is negative)
⎛ R1 ⎞
VTH2 = - VEE ⎜ ⎟
⎝ R1 + R2 ⎠
VTH = VTH1 + VTH2
⎛ R2 ⎞ ⎛ R1 ⎞
VTH = VCC ⎜ ⎟ - VEE ⎜ ⎟
⎝ R1 + R2 ⎠ ⎝ R1 + R2 ⎠
R1 R2
RTH =
R1 + R2

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Voltage Divider Bias with Dual Power Supply

Output Circuit
-VCC + ICRC + VCE + IERE - VEE = 0
If we assume IE ≅ IC (when β > 100)
VCC + VEE - VCE
IC =
RC + RE
If we use the exact solution IC = αIE
VCC + VEE - VCE
IC =
RE
RC +
α
β
where α =
β +1

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Voltage Divider Bias 17

ENGI 242/ELEC 222 Updated 23 February 2005

Voltage Divider Bias with Dual Power Supply

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PSpice Simulation

Voltage Divider Bias 18

ENGI 242/ELEC 222 Updated 23 February 2005

PSpice Bias Point Simulation

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PSpice Simulation for DC Bias

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Voltage Divider Bias 19

ENGI 242/ELEC 222 Updated 23 February 2005

PSpice Simulation for DC Sweep

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PSpice Simulation for DC Sweep

The response of VC demonstrates rises rapidly towards

the Q Point and then increases gradually towards a
maximum value

The response of VCE demonstrates that it

reaches a peak value near the Q point and
then decreases

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Voltage Divider Bias 20

ENGI 242/ELEC 222 Updated 23 February 2005

PSpice Simulation for AC Sweep

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PSpice Simulation for AC Sweep

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Voltage Divider Bias 21