Improved DSP-controlled online UPS system with high real output power

T.-J. Liang and J.-L. Shyu Abstract: A circuit topology is proposed for single-phase online UPS systems. The proposed circuit incorporates a built-in bidirectional AC/DC converter, which provides power factor correction and active power ltering. The input stage, based on a bidirectional AC/DC converter, functions as a rectier with unity power factor correction for normal AC line mode operation, and as an active power lter for outage mode operation. During input power failure, the bidirectional AC/DC converter functions as an active power lter, providing reactive power to the load. Simultaneously, the DC/AC voltage inverter output stage supplies real power from the battery bank to the critical load. The real power capability is improved compared with that of a conventional online UPS system, and extra loads can be connected to the UPS system during outage. The power circuit of the proposed UPS system is presented and analysed. Circuit models are derived and a UPS digital control system using a digital signal processor (DSP) is developed. Finally, simulated and experimental results obtained from a laboratory prototype are presented to conrm the feasibility and features of the proposed UPS scheme.

Introduction

Uninterruptible power supplies (UPS) ensure continuous power ow to critical loads in the event of disturbance surges or AC line failure, and have been used for a wide variety of loads, including telecommunication systems, medical systems, industrial control systems etc. Generally, an UPS system requires the normal utility AC line input current to have a low total harmonic distortion (THD) sinusoidal current with unity power factor. A UPS is required to deliver a well-regulated sinusoidal output voltage with low THD to the load, regardless of whether the utility AC power source is normal or not. Online and ofine UPS systems are the two major UPS schemes [16]. Online UPS systems are generally preferred because of high reliability and good voltage regulation. Because AC lines are easily contaminated, a power factor correction circuit is usually employed to obtain high power factor from the UPS system, thereby preventing contamination of the AC lines [79]. In a conventional online UPS system, the input stage is disabled and kept idle during AC line outage. The conventional UPS system has an inherent real output power limitation for nonlinear loads, as the load current may contain undesirable harmonics and is not kept in phase with the output voltage. As a result, the output power factor of the conventional UPS systems is low while feeding nonlinear loads because the real power absorbed by the load is low. Nevertheless, a UPS system is expected to produce nearly sinusoidal output current at the output side

and thus raise the output power factor of the UPS system. An active power lter (APF) is usually employed to compensate for line current harmonics and the reactive power of nonlinear loads, yielding a near-unity power factor and sinusoidal current waveform for the AC voltage source [10, 11]. This paper presents the hardware implementation and experimental results of a bidirectional AC/DC converter with power factor correction and active power ltering, a system that was presented previously as a simulation [12]. The input stage, based on a bidirectional AC/DC converter, functions as a power factor correction circuit for normal AC line mode operation to increase the AC line power factor and to reduce the AC line current harmonic components. During input power failure, the bidirectional AC/DC converter functions as an active power lter, providing reactive power to the load. Thus the real output power capability is improved compared with that of a conventional online UPS, and an efcient economic UPS system is achieved. 2 Proposed UPS conguration

Figure 1 shows the proposed online UPS circuit conguration which consists of a bidirectional AC/DC converter and a DC/AC voltage inverter. An LC lowpass lter is used at the output side for eliminating unwanted harmonic
S2 S1 LS
AC

r IEE, 2004 IEE Proceedings online no. 20040020 doi:10.1049/ip-epa:20040020 Paper rst received 20th September and in revised form 4th June 2003 T.-J. Liang is with the Department of Electrical Engineering, National Cheng Kung University, 1 University Road, Tainan, Taiwan 70101, ROC J.-L. Shyu is with the Department of Electrical Engineering, Kao Yuan Institute of Technology, 1821 Chung-Shan Road, Lu-Chu Hsian, Kaohsiung Hsian, Taiwan, ROC IEE Proc.-Electr. Power Appl., Vol. 151, No. 1, January 2004
AC line

Lo + CD bidirectional AC/DC converter VDC DC/AC voltage inverter Co + vo rated extra load load

vs

Fig. 1

Proposed online UPS system

121

components from the inverter output voltage. Switch S1 is incorporated in the power circuit to provide isolation between the UPS and the input AC power. When an input power failure occurs, power is transferred to the critical load from the battery bank through the DC/AC voltage inverter. The system has two operating modes. One is the normal mode (Fig. 2a), and the other is the outage mode (Fig. 2b). In the normal mode, switch S2 is opened and the bidirectional AC/DC converter functions as a power factor correction rectier, so that the line current is sinusoidal and in phase with the line voltage. The DC/AC voltage inverter is modulated such that the output voltage amplitude is held constant with low THD. During outage mode operation, switch S2 is closed and the bidirectional AC/DC converter is linked with the output of the DC/AC voltage inverter. The bidirectional AC/DC converter functions as an active power lter, i.e. the bidirectional converter provides reactive power and non-sinusoidal current to the load. The DC/AC voltage inverter can supply high real output power to the load. Thus the output power factor of the DC/AC voltage inverter is near-unity and the overall real output power capability of the UPS system is improved. For outage operation, this additional real power capability allows the addition of signicantly extra load.

is + vs
AC

LS + vp

id

iL RDC

SW1 SW3ic + vDC C SW2 SW4 D + + a * + vDC

i* s + is

current controller voltage controller

vcp

vtri

SW1 SW2 SW3 SW4

sin t

vDC

Gsc (s) + + vcp (k) kif b sin (k ) ev (k ) v *DC (k ) Gpv (z) 1 kif is kad vp +

vs 1 Lss

* (k ) is

kcp current controller fi

kpwm

is

id

S2

off

* (k) v (k ) is voltage pv current controller loop k vf c

vDC RDC RDC CD s +1

S1 AC line

on

is LS + VDC CD DC/AC voltage inverter Lo

if + Co vo

io il rated extra load load

fv

S1 AC line
AC

Fig. 2

a Schematic of proposed online UPS system during normal mode b Schematic of proposed online UPS system during outage mode

AC

vs

PFC rectifier a S2 on

Fig. 3 Circuit conguration and control strategy of bidirectional AC/DC converter during normal mode
a PFC circuit b Current loop c Voltage loop

off LS CD +V active power filter (APF) b DC/AC voltage inverter

DC

if Lo Co

io + vo

ia il rated extra load load

vs

If the control voltage vcp is kept constant over a switching period, the duty ratios of the PFC rectier can be expressed by: 1 vcp d1p 2 2vtri 1 vcp 1 d2p 2 2vtri where d1p and d2p denote the duty ratios of lower switches SW2 and SW4 at every switching period Ts. The amplitude of the triangular carrier is vtri. Resistance of the AC line is neglected to simplify circuit analysis. The equations of the PFC circuit model shown in Fig. 3a can be obtained as follows: dis vs vp 2 Ls dt where vp is the pulse width modulation (PWM) PFC voltage, vs is the supply voltage and is is the line current. PFC voltage vp is represented in terms of duty ratios d1p and d2p as: vp d1p d2p VDC kpwm vcp 3 where kpw vDC/vtri is the gain of the PFC rectier. If the battery bank is fully charged and neglecting the power loss of the converter, the DC-side current of the PFC circuit can be expressed as: dvDC vDC 4 id CD dt RDC
IEE Proc.-Electr. Power Appl., Vol. 151, No. 1, January 2004

UPS operation modes

System analysis and controller design

The proposed UPS system comprises a bidirectional AC/ DC converter and a DC/AC voltage source inverter.

3.1

Power factor correction rectier

Figure 3 shows the circuit schematic and the controller of the power factor correction (PFC) rectier [79]. When utility AC power is normal, the bidirectional AC/DC converter operates as a PFC rectier to improve input power factor. The control scheme consists of two parts: an inner current controller and outer voltage controller. The control strategy of the gating signals involves comparing the output voltage vcp of the current controller with triangular carrier vtri. Under this gating control scheme, the line current is follows the current command i s such that nearunity power factor and low current harmonics are obtained.
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Using the power balance relation between the input and output of the PWM converter at unity power factor gives: id vs kad 9 5 is vDC where kad denotes as power transfer gain. Figs. 3b and c show the controllers using circuit modelling equations (1)(5). To eliminate the disturbance of the line voltage vs shown in Fig. 3b, the disturbance compensator is set to: Gsc s 1=kpwm 6 A proportional controller kcp is chosen as the current controller. In this case, the transfer function between i s and is can be derived as: kcp kpwm is 1 k i L s k k k s cp pwm if if s 7

if + Lf vDC vi SW6 SW 8 DC/AC voltage inverter * io + io sin t + SW SW 7 5

io

ia

il LS + + rated extra va vo load load

ic + SW SW5 7 CD vDC SW6 SW8 APF

vca current vtri controller voltage controller a

+ + v* + DC vDC

SW5 SW6 SW7 SW8

Gos (s) * (k) + io + + + va kif b sin (k) ev (k) Gav (z) voltage controller vav (k) + Gis (s) +

vo 1 Ls s ia

il + io

kca

kpwm

where kif is current feedback scaling gain and i s is the line current command. The digital current control algorithm can be written as: vs k vcp k i s k is k kcp kpwm 8
v* (k)
DC

current vca (k ) controller fi

il 1 vDC CD s

The digital proportionalFintegral (PI) controller Gpv(z) shown in Fig. 3c is used to regulate the DC voltage and is expressed as: kpi Tv 9 z1 where Tv is the sampling period of the voltage loop, and kpp and kpi are the proportional and integral gains of the PI controller. Therefore, the nite difference equation of the PI controller can be obtained as: Gpv z kpp vpv k kpp fev k ev k 1g kpi ev k vpv k 1 10 where ev(k1) and vpv(k1) are the voltage error and controller output at the (k1) sampling instant. Multiplying vpv(k) by the synchronising signal sin(k) of measured supply voltage vs(k), the resulting line current command i s k is then obtained as: i s k vpv k sin k 11 Substituting (10) into (11) gives the line current command i s k . Therefore, the desired duty ratios d1p(k) and d2p(k) can be calculated by substituting (8) into (1).

i i* o (k) current o loop kvf c

1 kif

kad ia ic

fv

Fig. 4 Circuit conguration and control strategy of bidirectional AC/DC converter during outage mode
a APF circuit b Current loop c Voltage loop

3.2

Active power lter

When utility power failure is detected, the APF is immediately connected in parallel with the loads through switch S2. The input stage bidirectional AC/DC converter is then switched from PFC mode to APF mode and connected in parallel with the DC/AC voltage inverter. The APF circuit conguration and controllers are shown in Fig. 4 [10, 11]. Multi-loop controls, an inner current loop for regulating the DC/AC inverter output current io and an outer voltage loop for regulating the DC bus voltage, are used as the APF control system. The APF is designed to provide compensatory reactive energy to load current il so that the DC/AC voltage inverter output current io is in phase with the sinusoidal output voltage vo regardless of load nonlinearities. Using a procedure similar to the above PFC circuit analysis, the APF circuit modelling equations can now be written. The duty ratios d1a and d2a of the switches SW1
IEE Proc.-Electr. Power Appl., Vol. 151, No. 1, January 2004

(SW4) and SW3 (SW2) are expressed as: 1 vca d1a 2 2vtri 12 1 vca d2a 2 2vtri where d1a and d2a are the APF duty ratios and vtri is the amplitude of the triangular carrier. The voltage equation of APF can be derived as: dia va vo 13 Ls dt where ia is the APF output current, vo is the output voltage of the DC/AC voltage inverter and va is the PWM APF voltage. The APF voltage va can be obtained in terms of duty ratios d1a and d2a as: 14 va d1a d2a VDC kpwm vca where kpwm vDC/vtri denotes the APF converter gain. The current equations on the DC side and AC side can be written as: dvDC 15 ic CD dt il ia io 16 The current controller and voltage controller are illustrated in Figs. 4b and c, where kif and kvf are the current and voltage sensor scaling gains. The current controller shown in Fig. 4b is a proportional controller with proportional
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gain kca. The closed-loop transfer function of current loop is expressed as: kpwm kca 1 i il 17 io Ls s kif kpwm kca o Ls s kif kpwm kca The second term of (17) shows that il is viewed as a disturbance. If the feed-forward compensator Gos(s) shown in Fig. 4b is set to 1/kpwm and the current controller kca is set to high proportional gain, then disturbance is eliminated for vo and il. Thus the resulting current loop can be further simplied to a constant gain: io 1 18 k i if o The control voltage vca(k) generated from the current loop can be derived as: vo k 19 vca k i o k io k kca kpwm The outer voltage loop is shown in Fig. 4c. A digital PI voltage controller Gav(z) is used. Using procedures similar to those described previously in the PFC control system, the composite voltage loop control algorithm can also be obtained as: vav k kap fev k ev k 1g kai ev k vav k 1 20
v* o (k) v* o (k)

if + SW5 SW7 + Lo +

io il extra load

vDC SW6 SW 8

vo load vi C o vci + + a + v* o vo

SW5 SW6 SW7 SW8

i f*

+ if

current controller

vtri

voltage controller

Gvs (s) + + vci (k) kif b + + io + vi

vo

i f* (k)

kci current controller fi

kpwm

1 Los

if

Gff (z )

Gis (s)

1 Zload 1 Cos

where kap and kai are the proportional and integral gain of the PI controller. By letting feed-forward disturbance compensator Gls(s) kif, disturbance il is cancelled. Then, the output current command i o k of the DC/AC voltage inverter is computed by multiplying i o k with unit vector sin(k) of the output voltage vo(k). This gives: i 21 o k vav k sink kif il k Equation (20) is used to determine i o k . Duty ratios d1a and d2a are obtained by substituting (19) into (12).

ev (k)

kvi

++ i *f (k)

1 kif current loop kvf

+ if

vo

voltage controller

fv c

Fig. 5 Circuit conguration and control strategy of DC/AC voltage inverter

a Inverter circuit b Current loop c Voltage loop

3.3

DC/AC voltage inverter

The circuit diagram and control block diagram of a voltage inverter are shown in Fig. 5 [1315]. The inverter has two controllers: one is for the inner current loop and the other is for the outer voltage loop. The multi-loop control technique with feed-forward control is used to make the output voltage vo follow the sinusoidal voltage command v o closely. The duty ratios d1i and d2i of upper switches SW5 (SW8) and SW7 (SW6) are: 1 vci d1i 2 2vtri 22 1 vci d2i 2 2vtri Applying Kirchhoffs law on the AC output side gives: dif vi vo Lo 23 dt where vi is the PWM inverter output voltage, which may be obtained from duty ratios d1i and d2i as: vi d1i d2i VDC kpwm vci 24 where kpwm vDC/vtri denotes the inverter gain. From Fig. 5a, the current equation can be obtained as: dvo if io 25 Co dt where if is the inductor current and io is the output current. Using (22)(25), the multi-loop control system of the inverter output voltage can therefore be developed as
124

shown in Figs. 5b and c. kvf and kif are the voltage and current sensor scaling gains. The voltage controller and current controller can be realised by proportional gains kvi and kci to simplify the control algorithm. As shown in Fig. 5b, if feed-forward disturbance compensator Gvs(s) satises: Gvs s 1=kpwm 26 the disturbance of output voltage vo can be cancelled. The transfer function of the current loop can be simplied as: if 1 27 if kif The desired control voltage vci(k) is vci k i f k if k kci vo k kpwm 28

The output current io also acts as a disturbance to the voltage loop shown in Fig. 5c. Likewise, io can be eliminated by setting: Gis s kif 29 To produce an output voltage with zero steady state error, a command feed-forward controller Gff(s) is used, derived as: kif Co 30 Gff s kvf
IEE Proc.-Electr. Power Appl., Vol. 151, No. 1, January 2004

Thus the inductor current command i f k is represented by:

i f k vo k vo k kvi

vs

is

kcf Co  v k kif io k kvf

31

where v o k is the sinusoidal voltage command. Substituting (31) into (28), the control voltage vci(k) can be obtained. The duty ratios d1i and d2i at every switching period can then be calculated by substituting (28) into (22). Note that the DSP software design is easy to implement as the multi-loop control algorithms during normal and outage modes have similar control structures.
vs

Simulated and experimental results

is

The closed-loop UPS system has been tested by both simulation and experiment. An experimental prototype using a digital signal processor TMS320F240 digital controller was built. The sampling frequency fc and fv of the current controller and voltage controller were set to 18 kHz and 9 kHz, respectively. The PWM switching frequency fs was 18 kHz. The UPS specications and circuit parameters are: AC input voltage : 110 Vrms ; 60 Hz AC output voltage : 110 Vrms ; 60 Hz DC bus voltage : VDC 210 V Power factor :  0:98 Input filter inductance : Ls 3:0 mH Switching frequency fs : 18 kHz Output filter capacitor : Co 30 mF DC capacitor : CDC 940 mF Output filter inductor : Lo 1:0 mH DC Load : RDC 80 O In the design of these controllers, the controller parameters were chosen to ensure that satisfactory dynamic response was obtained over the operating range of the UPS system. The controllers were tested systematically in the operating conditions given in Table 1.
100

distortion, % 0 0

frequency, Hz c

2.0k

Fig. 6 Simulated and experimental results of AC line voltage vs and current is in normal mode (vs 50 V/division, is 5 A/division, time 5 ms/division)
a Simulated result b Experimental result c Harmonic spectrum of line current is; THD 3.16%

Table 1: Parameters of the controllers

PFC controller (normal mode) APF controller (outage mode) Voltage controller (voltage inverter) kpp 0.6, kpi 0.92, kcp 30, kvf 0.02, kif 0.21, kad 0.51, kpwm 42 kap 0.091, kai 0.03, kca 30, kvf 0.02, kif 0.2, kad 0.51, kpwm 42 kvi 0.6, kci 20, kpwm 42 kvf 0.02, kif 0.2,

Figure 6 shows the line voltage vs and line current is waveforms for the PFC rectier during normal mode. It conrms that, under normal mode condition, the PFC rectier can obtain high power factor line current with low current harmonics. The line current is controlled to be sinusoidal and in phase with the AC mains voltage while in normal mode. Line current harmonic components show a THD of 3.16% and an input power factor of 0.995. The UPS output voltage shows good regulation with low THD when feeding nonlinear loads, as shown in Fig. 7. Despite a distorted current io, the measured THD of inverter output voltage vo is 4.53%. Figure 8 shows that the bidirectional AC/DC converter acts as an APF and produces the current required by a nonlinear load in outage mode. Inverter
IEE Proc.-Electr. Power Appl., Vol. 151, No. 1, January 2004

output voltage vo, load current il, active lter current ia and output current io are presented in Fig. 8. Active lter current ia shows almost the same harmonic components as load current il. Thus inverter output current io becomes sinusoidal with nearly unity power factor at the DC/AC voltage inverter side. The THD of the DC/AC voltage inverter output current io is 6.89%. Table 2 lists the measured values during normal and outage modes. It also shows that line current THD, reactive power Q and UPS apparent power S are signicantly decreased when the UPS operates at outage mode, clearly showing the effectiveness of the proposed UPS system. Consequently, the proposed UPS system ensures 353 W real output power to the existing load, but is also capable of delivering an additional 143 W real power to any additional load. Thus the proposed UPS exhibits excellent performance for nonlinear loads. The transitions from normal mode to outage mode and vice versa are shown in Figs. 9 and 10. The above experimental results all give consistent agreement with simulated results, conrming
125

vo vo

io

il

ia

io

a
a vo vo io

il

ia

b
100 io

b distortion, % 100

frequency, Hz c

2.0k

Fig. 7 Simulated and experimental results of DC/AC inverter output voltage vo and output current io in normal mode (vo 50 V/ division, io: 5 A/division, time 5 ms/division)
a Simulated result b Experimental result c Harmonic spectrum of voltage vo; THD 4.53%

distortion, % 0 0 frequency, Hz c 2.0k

Fig. 8 Simulated and experimental results of UPS system during outage mode (inverter output voltage vo, 100 V/division; load current il, 10 A/division; bidirectional AC/DC output current ia, 5 A/division; inverter output current io, 5 A/division; time 5 ms/division)
a Simulated result b Experimental result c Harmonic spectrum of inverter output current io; THD 6.89%

good performance compared with the conventional UPS approach. 5 Conclusions

This paper has presented a online UPS system with built-in bidirectional AC/DC converter with improved performance relative to that of a conventional UPS system. A DSP-based UPS prototype has been implemented to verify the multiloop digital control schemes. The control systems are described and simulations presented to verify the performance of the proposed system. Simulation results for normal mode show a near-unity input power factor and a well-regulated output voltage to the load. The UPS system shows a well-regulated output voltage and an output current in phase with the output voltage during outage. Experimental results are in good agreement with simulated results, conrming the effectiveness of the proposed UPS and improved operating characteristics compared with those of conventional online UPS systems. Advantages of the proposed system include high real output power
126

Table 2: Operating parameters at outage mode

Conventional UPS Output current io THD % Output power factor Real power P Reactive power Q Apparent power S Inverter voltage vo RMS Inverter output current io RMS 71.62 0.707 353 W 357 VAr 500 VA 110 V 4.48 A Proposed UPS system 6.89 0.991 353 W 45 VAr 356 VA 110 V 3.21 A

IEE Proc.-Electr. Power Appl., Vol. 151, No. 1, January 2004

vs

capacity, full utilisation of the power converter and low system cost per unit of real output power. 6
is ia

Acknowledgments

is / ia

The authors wish to thank Dr. J.F. Chen for offering many useful suggestions concerning the research in this paper. 7 References

vo

io

il

Fig. 9 Experimental results of UPS system during sudden transition from normal to outage mode

vs

ia ia / is

is

vo

io

il

Fig. 10 Experimental results of UPS system during sudden transition from outage to normal mode

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