Gray Code to Binary Converter August 23, 2010 Document No. 001-58814 Rev.

*A 1 EP 58814 Project Name: Example_ShiftRegister Programming Language: C Associated Part Families:CY8C38xx/CY8C55xx Software: PSoC Creator Related Hardware: CY8CKIT-001 Author: Vivek Sriram Project Objective This example project illustrates a hardware implementation of gray code to binary converter in PSoC 3 using the shift register. Overview Gray code is a binary numeral system where two successive values differ by one bit. Gray codes are widely used to facilitate error correction in digital communications. However, for computational purposes this must be converted to its corresponding binary form. This example project illustrates the conversion of gray code to binary using only hardware elements. Hardware implementation implies that it is possible to attain a conversion rate in the order of a MHz using PSoC 3, which is otherwise only possible with FPGAs. Top Design The following diagram shows the pin assignment. [+] Feedback EP58814 August 23, 2010 Document No. 001-58814 Rev. *A 2 Component Configuration The following table lists the hardware resources occupied by each user module. Instance Name Component Name Version Component Category Comments ShiftReg_1 Shift Register Digital Functions Loads the gray code value and stores the binary value after shift operation is done ShiftReg_2 Shift Register Digital Functions Used only for the purpose of providing a clock to ShiftReg_1 and Counter_1 Counter_1 Counter 1.50 Digital Functions Count of the number of rising edges on ShiftReg_1 Clock Clock_SReg Clock System Clock input to the two digital functions LCD_1 Character LCD 1.50 Display Displays the gray and the corresponding binary value Shift Register ShiftReg_1 An 8-bit, left shifting shift register is configured as ShiftReg_1. This is loaded initially with an 8-bit gray value. The output is routed back to the input so that after eight shifts, the corresponding binary value is in the shift register. Store input is enabled to store the value of the shift register after every eight clock cycles into the FIFO buffer. ShiftReg_2 ShiftReg_2 is configured as an 8-bit shift register. This shift register is loaded initially with a value of 0xAA and its only purpose is to serve as a clock for the gray to binary conversion

system, that is, ShiftReg_1, D-Flip Flop, and Counter_1. [+] Feedback EP58814 August 23, 2010 Document No. 001-58814 Rev. *A 3 Counter Counter_1 Interrupt for the counter is set to terminal count in the Advanced tab. The counter is also reloaded on Terminal count. The terminal count is set to 8 so that after eight rising edges, the terminal count undergoes a low to high transition for one clock cycle. This is used as an input for the store signal of the shift register and the asynchronous reset of the D-Flip Flop. LCD The LCD component with its default settings is used to display the gray value and its corresponding binary value. Design Wide Resources The project uses the default system wide resources settings. Refer to the Example_ShiftRegister.cydwr file for the setting. Operation This project implements a gray code to binary converter using only hardware elements such as a shift register, a XOR gate, and a D Flip Flop. Logic The logic for the conversion of gray code to binary is as follows: The most significant bit of the binary equivalent is the same as the gray code and is passed on as it is. The next significant bit is obtained by XORing the corresponding bit in the gray code with the result of the previous XOR. The second step is repeated until the least significant bit of the binary value is obtained. [+] Feedback EP58814 August 23, 2010 Document No. 001-58814 Rev. *A 4 Implementation This project uses an 8-bit shift register to illustrate the conversion from gray code to binary. To implement the conversion from most significant bit to the least significant bit, ShiftReg_1 uses shifts leftward. The initial state of the D-Flip Flop is 0. This ensures that the most significant bit passes on unchanged. In case of continuous loading, ensure that before the start of each conversion the initial state of the flip-flop is 0. The shift register is loaded with a gray code value. ShiftReg_1 and Counter_1 are started. ShiftReg_2 (which is used only for providing clock to the other shift register, flip-flop and the counter) is then started. The counter is an up counter that reloads on terminal count. Terminal count is reached on eight rising edges. The terminal count also acts as a reset signal for the flip-flop ensuring that the initial state of the flip-flop is zero for a new conversion. The terminal count also acts as the input to the store signal of ShiftReg_1. This implies that after every eight shifts, the shift register value is moved to the FIFO. An interrupt routine is triggered by a rising edge on the terminal count signal. In the interrupt service routine, the FIFO is read to find the binary equivalent of the initially loaded gray code value. In this example, the shift register and the counter are stopped after one conversion. By increasing only the size of the shift register, higher bits of gray code can be converted to its corresponding binary value. By using the load pin of the shift register, you can implement a hardware level design to continuously load gray code values. This example project simply illustrates a complete hardware implementation of the conversion. Therefore, only a single time conversion is illustrated. However, application specific modifications to the design can be made to load multiple/continuous gray code data in the shift register. If required, an additional shift register can be used to store the binary value instead of storing it in the same register. Hardware Connections All jumpers in the DVK must be left to the default state. Refer to the PSoC Development Kit Board Guide for the default jumper settings Connect LCD on connector P18 Enable the LCD power by placing the Jumper J12 to ON position. [+] Feedback EP58814 August 23, 2010 Document No. 001-58814 Rev. *A 5 Output Load the initial gray code value Build the project and program the chip The gray value and the corresponding binary value are displayed on the LCD in hex format Note The default device selection is PSoC 3 (CY8C3866AXI-040). To use this project with PSoC 5 device do the following steps. Go to Project Device Selector PSoC 5 (CY8C5588AXI060), build the project again and program the PSoC 5 device as shown in the following figure.

PSoC is a registered trademark of Cypress Semiconductor Corp. PSoC Creator is a trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are the property of their respective owners. Cypress Semiconductor 198 Champion Court San Jose, CA 95134-1709 Phone: 408-943-2600 Fax: 408-943-4730 http://www.cypress.com/ Cypress Semiconductor Corporation, 2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. This Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. [+] Feedback