Lecture 3 Inverters and Combinational Logic

Konstantinos Masselos Department of Electrical & Electronic Engineering Imperial College London

URL: http://cas.ee.ic.ac.uk/~kostas E-mail: k.masselos@imperial.ac.uk

Inverters and Combinational Logic Introduction to Digital Integrated Circuit Design Lecture 3 - 1

Based on slides/material by

P. Cheung http://www.ee.ic.ac.uk/pcheung/teaching/ee4_asic/index.html J. Rabaey http://bwrc.eecs.berkeley.edu/Classes/IcBook/instructors.html Digital Integrated Circuits: A Design Perspective, Prentice Hall D. Harris http://www.cmosvlsi.com/coursematerials.html Weste and Harris, CMOS VLSI Design: A Circuits and Systems Perspective, Addison Wesley

Inverters and Combinational Logic

Introduction to Digital Integrated Circuit Design

Lecture 3 - 2

Recommended Reading

J. Rabaey et. al. Digital Integrated Circuits: A Design Perspective: Chapter 5 (5.1 5.3), Chapter 6 Weste and Harris, CMOS VLSI Design: A Circuits and Systems Perspective: Chapter 2 (2.5), Chapter 6 (6.1, 6.2)

Inverters and Combinational Logic

Introduction to Digital Integrated Circuit Design

Lecture 3 - 3

Outline

CMOS Inverter
response delays

Logic gates
Static CMOS
Conventional Static CMOS Logic Ratioed Logic Pass Transistor/Transmission Gate Logic

Dynamic CMOS
Domino np-CMOS

Tristates and Multiplexers

Inverters and Combinational Logic

Introduction to Digital Integrated Circuit Design

Lecture 3 - 4

The CMOS Inverter: A First Glance

VDD

Vin

Vout CL

Inverters and Combinational Logic

Introduction to Digital Integrated Circuit Design

Lecture 3 - 5

CMOS Inverters
VDD PMOS

1.2m =2 In Out Metal1 Polysilicon

NMOS GND

Inverters and Combinational Logic

Introduction to Digital Integrated Circuit Design

Lecture 3 - 6

Inverter DC Response

DC Response: Vout vs. Vin for a gate Inverter

When Vin = 0 When Vin = VDD -> -> Vout = VDD Vout = 0

In between, Vout depends on transistor size and current By KCL, must settle such that Idsn = |Idsp| Transfer function can be found by solving equations, but graphical solution gives more insight Current depends on region of transistor behavior (cutoff, linear, saturation) VDD

Vin

Idsp Idsn

Vout

Inverters and Combinational Logic

Introduction to Digital Integrated Circuit Design

Lecture 3 - 7

nMOS Operation

Cutoff Vgsn < Vtn Vin < Vtn

Linear Vgsn > Vtn Vin > Vtn Vdsn < Vgsn Vtn Vout < Vin - Vtn

Saturated Vgsn > Vtn Vin > Vtn Vdsn > Vgsn Vtn Vout > Vin - Vtn

VDD

Vgsn = Vin Vdsn = Vout

Vin

Idsp Idsn

Vout

Inverters and Combinational Logic

Introduction to Digital Integrated Circuit Design

Lecture 3 - 8

pMOS Operation

Cutoff Vgsp > Vtp Vin > VDD + Vtp

Linear Vgsp < Vtp Vin < VDD + Vtp Vdsp > Vgsp Vtp Vout > Vin - Vtp

Saturated Vgsp < Vtp Vin < VDD + Vtp Vdsp < Vgsp Vtp Vout < Vin - Vtp

VDD

Vgsp = Vin - VDD Vdsp = Vout - VDD

Vtp < 0
Vin

Idsp Idsn

Vout

Inverters and Combinational Logic

Introduction to Digital Integrated Circuit Design

Lecture 3 - 9

Operating Regions

Region A B C D E

nMOS Cutoff Saturation Saturation Linear Linear

pMOS Linear Linear Saturation Saturation Cutoff

VDD A Vout B

D 0
Vtn VDD/2

E
VDD+Vtp

VDD

Vin

Inverters and Combinational Logic

Introduction to Digital Integrated Circuit Design

Lecture 3 - 10

Load Line Analysis

Current vs Vout, Vin For a given Vin:

Plot Idsn, Idsp vs. Vout Vout must be where |currents| are equal in

VDD Vin Idsp Idsn Vout

Vin0

Vin5

Idsn, |Idsp|

Vin1 Vin2 Vin3 Vin4 Vout VDD

Vin4 Vin3 Vin2 Vin1

Inverters and Combinational Logic

Introduction to Digital Integrated Circuit Design

Lecture 3 - 11

DC Transfer Curve

Transcribe points onto Vin vs. Vout plot

Vin0

Vin5

VDD A Vout B

Vin1 Vin2 Vin3 Vin4 Vout VDD

Vin4 Vin3 Vin2 Vin1

D 0
Vtn VDD/2

E
VDD+Vtp

VDD

Vin

Inverters and Combinational Logic

Introduction to Digital Integrated Circuit Design

Lecture 3 - 12

Beta Ratio

Exact switching point depends on p / n If p / n 1, switching point will move from VDD/2 Otherwise:

VDD
p = 10 n

Vout
p = 0.1 n

2 1 0.5

0 Vin VDD

Inverters and Combinational Logic

Introduction to Digital Integrated Circuit Design

Lecture 3 - 13

Noise Margins

How much noise can a gate input see before it does not recognize the input?

Output Characteristics Logical High Output Range

VDD

Input Characteristics Logical High Input Range Indeterminate Region Logical Low Input Range

VOH NMH VIH VIL NML

Logical Low Output Range

VOL GND

Inverters and Combinational Logic

Introduction to Digital Integrated Circuit Design

Lecture 3 - 14

Logic Levels

To maximize noise margins, select logic levels at

unity gain point of DC transfer characteristic

Vout VDD VOH p / n > 1 Vin Vout Unity Gain Points Slope = -1

VOL 0 Vtn VIL VIH VDD- VDD |Vtp|

Vin

Inverters and Combinational Logic

Introduction to Digital Integrated Circuit Design

Lecture 3 - 15

Transient Response

DC analysis tells us Vout if Vin is constant Transient analysis tells us Vout(t) if Vin(t) changes
Requires solving differential equations

Input is usually considered to be a step or ramp

From 0 to VDD or vice versa

Inverters and Combinational Logic

Introduction to Digital Integrated Circuit Design

Lecture 3 - 16

Inverter Step Response

Ex: find step response of inverter driving load cap

Vin (t ) = u(t t0 )VDD Vout (t < t0 ) = VDD I dsn (t ) dVout (t ) = dt Cload

0 2 I dsn (t ) = V V ( ) DD 2 V (t ) VDD Vt out 2 t t0 Vout > VDD Vt V (t ) V < V V out out DD t
t0 Vout(t) t

Vin(t)

Vout(t) Cload Idsn(t)

Vin(t)

Inverters and Combinational Logic

Introduction to Digital Integrated Circuit Design

Lecture 3 - 17

Ideal Inverter

Vout

Ri = Ro = 0 g=

Vin

Inverters and Combinational Logic

Introduction to Digital Integrated Circuit Design

Lecture 3 - 18

Voltage Transfer Characteristic of Real Inverter

5.0 4.0 Vout (V) 3.0 2.0 1.0 NML

VM NMH

0.0

1.0

2.0 3.0 Vin (V)

4.0

5.0

Inverters and Combinational Logic

Introduction to Digital Integrated Circuit Design

Lecture 3 - 19

Outline

CMOS Inverter
response delays

Logic gates
Static CMOS
Conventional Static CMOS Logic Ratioed Logic Pass Transistor/Transmission Gate Logic

Dynamic CMOS
Domino np-CMOS

Tristates and Multiplexers

Inverters and Combinational Logic

Introduction to Digital Integrated Circuit Design

Lecture 3 - 20

Delay Definitions
Vin

50% t Vout t pHL t pLH 90% 50% 10% t

tf

tr

Inverters and Combinational Logic

Introduction to Digital Integrated Circuit Design

Lecture 3 - 21

Impact of Rise Time on Delay

0.35

0.3 tpHL(nsec)

0.25

0.2

0.15

0.2

0.4 0.6 trise (nsec)

0.8

Inverters and Combinational Logic

Introduction to Digital Integrated Circuit Design

Lecture 3 - 22

Simulated Inverter Delay

Solving differential equations by hand is too hard SPICE simulator solves the equations numerically
Uses more accurate I-V models too!

But simulations take time to write

2.0

1.5

1.0 (V)

Vin
0.5

tpdf = 66ps

tpdr = 83ps

Vout

0.0

0.0

200p

400p t(s)

600p

800p

1n

Inverters and Combinational Logic

Introduction to Digital Integrated Circuit Design

Lecture 3 - 23

Delay Estimation

Need to easily estimate delay

Not as accurate as simulation But easier to ask What if?

The step response usually looks like a 1st order RC response with a decaying exponential. Use RC delay models to estimate delay
C = total capacitance on output node Use effective resistance R So that tpd = RC

Characterize transistors by finding their effective R

Depends on average current as gate switches

Inverters and Combinational Logic

Introduction to Digital Integrated Circuit Design

Lecture 3 - 24

RC Delay Models

Use equivalent circuits for MOS transistors

Ideal switch + capacitance and ON resistance Unit nMOS has resistance R, capacitance C Unit pMOS has resistance 2R, capacitance C

Capacitance proportional to width Resistance inversely proportional to width

d R/k g kC s kC kC d k s kC g kC d

kC 2R/k

d k s

Inverters and Combinational Logic

Introduction to Digital Integrated Circuit Design

Lecture 3 - 25

Computing the Capacitances

VDD M2 Vin Cgd12 Cdb2 Vout Cg 4

VDD

M4 Vout2

Cdb1 M1

Cw

Cg 3

M3

Interconnect

Fanout

Simplified Model

Vin

Vout
CL

Inverters and Combinational Logic

Introduction to Digital Integrated Circuit Design

Lecture 3 - 26

Computing the Capacitances

Inverters and Combinational Logic

Introduction to Digital Integrated Circuit Design

Lecture 3 - 27

Delay as a function of VDD

28 24 Normalized Delay 20 16 12 8 4 0 1.00 2.00 3.00 4.00 5.00

VDD (V)

Inverters and Combinational Logic

Introduction to Digital Integrated Circuit Design

Lecture 3 - 28

Outline

CMOS Inverter
response delays

Logic gates
Static CMOS
Conventional Static CMOS Logic Ratioed Logic Pass Transistor/Transmission Gate Logic

Dynamic CMOS
Domino np-CMOS

Tristates and Multiplexers

Inverters and Combinational Logic

Introduction to Digital Integrated Circuit Design

Lecture 3 - 29

Digital Gates Fundamental Parameters

Functionality Reliability, Robustness Area Performance

Speed (delay) Power Consumption Energy

Inverters and Combinational Logic

Introduction to Digital Integrated Circuit Design

Lecture 3 - 30

Fan-in and Fan-out

(a) Fan-out N

M N (b) Fan-in M

Inverters and Combinational Logic

Introduction to Digital Integrated Circuit Design

Lecture 3 - 31

Combinational vs. Sequential Logic

Logic In Circuit Out

In

Logic Circuit

Out

State

(a) Combinational Output = f(In )

(b) Sequential Output = f(In, Previous In)

Inverters and Combinational Logic

Introduction to Digital Integrated Circuit Design

Lecture 3 - 32

Outline

CMOS Inverter
response delays

Logic gates
Static CMOS
Conventional Static CMOS Logic Ratioed Logic Pass Transistor/Transmission Gate Logic

Dynamic CMOS
Domino np-CMOS

Tristates and Multiplexers

Inverters and Combinational Logic

Introduction to Digital Integrated Circuit Design

Lecture 3 - 33

Static CMOS Circuit

At every point in time (except during the switching transients) each gate output is connected to either Vdd or Vss via a low-resistive path. The outputs of the gates assume at all times the value of the Boolean function, implemented by the circuit (ignoring, once again, the transient effects during switching periods). This is in contrast to the dynamic circuit class, which relies on temporary storage of signal values on the capacitance of high impedance circuit nodes.

Inverters and Combinational Logic

Introduction to Digital Integrated Circuit Design

Lecture 3 - 34

Static CMOS
VDD In1 In2 In3

PUN

PMOS Only
F=G

In1 In2 In3

PDN

NMOS Only

VSS

PUN and PDN are Dual Networks

Inverters and Combinational Logic Introduction to Digital Integrated Circuit Design Lecture 3 - 35

NMOS Transistors in Series/Parallel Connection

Transistors can be thought as a switch controlled by its gate signal NMOS switch closes when switch control input is high
A X A B Y Y = X if A and B

Y = X if A OR B

NMOS Transistors pass a strong 0 but a weak 1

Inverters and Combinational Logic

Introduction to Digital Integrated Circuit Design

Lecture 3 - 36

PMOS Transistors in Series/Parallel Connection

PMOS switch closes when switch control input is low
A X A B Y = X if A AND B = A + B

Y = X if A OR B = AB

PMOS Transistors pass a strong 1 but a weak 0

Inverters and Combinational Logic Introduction to Digital Integrated Circuit Design Lecture 3 - 37

Complementary CMOS Logic Style Construction

Inverters and Combinational Logic

Introduction to Digital Integrated Circuit Design

Lecture 3 - 38

NAND Gate

Inverters and Combinational Logic

Introduction to Digital Integrated Circuit Design

Lecture 3 - 39

NOR Gate

Inverters and Combinational Logic

Introduction to Digital Integrated Circuit Design

Lecture 3 - 40

Complex Gates
VDD B A C D

OUT = D + A (B+C)
A D B C

Inverters and Combinational Logic

Introduction to Digital Integrated Circuit Design

Lecture 3 - 41

4-input NAND Gate

Vdd
In1 In2 In1 In2

VDD In3 In4 Out

Out

In3 In4

GND
In1 In2 In3 In4

Inverters and Combinational Logic

Introduction to Digital Integrated Circuit Design

Lecture 3 - 42

Standard Cell Layout Methodology

metal1

VDD Well

VSS Routing Channel signals polysilicon

Inverters and Combinational Logic

Introduction to Digital Integrated Circuit Design

Lecture 3 - 43

Two Versions of (a+b).c

VDD

VDD

x GND GND a b c

(a) Input order {a c b}

(b) Input order {a b c}

Inverters and Combinational Logic

Introduction to Digital Integrated Circuit Design

Lecture 3 - 44

Logic Graph

VDD b j a x b c a i GND b j a PDN c x c i VDD x PUN

Inverters and Combinational Logic

Introduction to Digital Integrated Circuit Design

Lecture 3 - 45

Consistent Euler Path

c x i VDD

GND

{ a b c}
Inverters and Combinational Logic Introduction to Digital Integrated Circuit Design Lecture 3 - 46

Example: x = ab+cd

x b x a GND (a) Logic graphs for (ab+cd) d c VDD x a b

x c VD D d GND (b) Euler Paths {a b c d } VD D

x GND a b c d (c) stick diagram for ordering {a b c d}

Inverters and Combinational Logic Introduction to Digital Integrated Circuit Design Lecture 3 - 47

Properties of Complementary CMOS Gates

High noise margins: VOH and VOL are at VDD and GND, respectively. No static power consumption: There never exists a direct path between VDD and VSS (GND) in steady-state mode. Comparable rise and fall times: (under the appropriate scaling conditions)

Inverters and Combinational Logic

Introduction to Digital Integrated Circuit Design

Lecture 3 - 48

Transistor Sizing
for symmetrical response (dc, ac) for performance
VDD B A 6 C D 6 F A D 1 B 2 C 2 2 12 12

Input Dependent Focus on worst-case

Inverters and Combinational Logic

Introduction to Digital Integrated Circuit Design

Lecture 3 - 49

Propagation Delay Analysis - The Switch Model

RON

=
VDD Rp A A F Rn A CL Rn B Rn A (a) Inverter (b) 2-input NAND Rp B F CL Rp

VDD

VDD Rp B Rp A Rn A F Rn B CL

(c) 2-input NOR

tp = 0.69 Ron CL (assuming that CL dominates!)

Inverters and Combinational Logic

Introduction to Digital Integrated Circuit Design

Lecture 3 - 50

What is the Value of Ron?

Inverters and Combinational Logic

Introduction to Digital Integrated Circuit Design

Lecture 3 - 51

Analysis of Propagation Delay

VDD Rp A Rn B Rn A 2-input NAND B F CL Rp

1. Assume Rn =Rp = resistance of minimum sized NMOS inverter 2. Determine Worst Case Input transition (Delay depends on input values) 3. Example: tpLH for 2input NAND - Worst case when only ONE PMOS Pulls up the output node - For 2 PMOS devices in parallel, the resistance is lower tpLH = 0.69 Rp CL 4. Example: tpHL for 2input NAND - Worst case : TWO NMOS in series tpHL = 0.69(2R n)CL

Inverters and Combinational Logic

Introduction to Digital Integrated Circuit Design

Lecture 3 - 52

Design for Worst Case

VDD

V DD

1
A B

1
A
F CL

B 2 C D 2

4 4

2
B

2
A

A D 1 B

2 2C 2

Here it is assumed that Rp = Rn

Inverters and Combinational Logic Introduction to Digital Integrated Circuit Design Lecture 3 - 53

Influence of Fan-In and Fan-Out on Delay

VDD A B C D Fan-Out: Number of Gates Connected 2 Gate Capacitances per Fan-Out

A B FanIn: Quadratic Term due to: C D 1. Resistance Increasing 2. Capacitance Increasing (tpHL )

tp = a1 FI + a2 FI 2 + a3 FO

Inverters and Combinational Logic

Introduction to Digital Integrated Circuit Design

Lecture 3 - 54

tp as a function of Fan-In
4.0 3.0 tp (nsec) 2.0 1.0
linear

tpHL

quadratic

tp

tpLH 9

0.0

5 fan-in

AVOID LARGE FAN-IN GATES! (Typically not more than FI < 4)

Inverters and Combinational Logic

Introduction to Digital Integrated Circuit Design

Lecture 3 - 55

Fast Complex Gate - Design Techniques

Transistor Sizing:
As long as Fan-out Capacitance dominates

Progressive Sizing:
Out InN MN CL M1 > M2 > M3 > MN In3 In2 In1 M3 M2 M1 C3 Distributed RC-line C2 C1

Can Reduce Delay with more than 30%!

Inverters and Combinational Logic

Introduction to Digital Integrated Circuit Design

Lecture 3 - 56

Fast Complex Gate - Design Techniques (2)

Transistor Ordering
critical path CL critical path CL

In3

M3

In1

M1

In2

M2

C2

In2

M2

C2

In1

M1

C1 (a)

In3

M3

C3 (b)

Inverters and Combinational Logic

Introduction to Digital Integrated Circuit Design

Lecture 3 - 57

Fast Complex Gate - Design Techniques (3)

Improved Logic Design

Inverters and Combinational Logic

Introduction to Digital Integrated Circuit Design

Lecture 3 - 58

Fast Complex Gate - Design Techniques (4)

Buffering: Isolate Fan-in from Fan-out

CL

CL

Inverters and Combinational Logic

Introduction to Digital Integrated Circuit Design

Lecture 3 - 59

Ratioed Logic

VDD Resistive Load RL F In1 In2 In3 PDN VSS (a) resistive load In1 In2 In3 Depletion Load

VDD VT < 0 F PDN VSS (b) depletion load NMOS In1 In2 In3 PMOS Load VSS

VDD

F PDN VSS (c) pseudo-NMOS

Goal: to reduce the number of devices over complementary CMOS

Inverters and Combinational Logic

Introduction to Digital Integrated Circuit Design

Lecture 3 - 60

Pseudo-NMOS

The pull-up p-channel transistor is always conducting.

Disadvantages: high d.c. dissipation & slow rise time.

Inverters and Combinational Logic

Introduction to Digital Integrated Circuit Design

Lecture 3 - 61

Pseudo-NMOS NAND Gate

VDD

GND

Inverters and Combinational Logic

Introduction to Digital Integrated Circuit Design

Lecture 3 - 62

Improved Loads
VDD VDD

M1

M2

Out A A B B

Out

PDN1

PDN2

VSS

VSS

Dual Cascode Voltage Switch Logic (DCVSL)

Inverters and Combinational Logic

Introduction to Digital Integrated Circuit Design

Lecture 3 - 63

Pass-Transistor Logic

B
Switch Network

Out

A Out B B

Inputs

N transistors No static consumption

Inverters and Combinational Logic

Introduction to Digital Integrated Circuit Design

Lecture 3 - 64

NMOS-only switch

C=5V A =5V B CL A =5V

C=5V M2 B Mn M1

VB does not pull up to 5V, but 5V - VTN Threshold voltage loss causes static power consumption
Inverters and Combinational Logic Introduction to Digital Integrated Circuit Design Lecture 3 - 65

Pass Transistor Logic with feedback

Inverters and Combinational Logic

Introduction to Digital Integrated Circuit Design

Lecture 3 - 66

Complementary Pass Transistor Logic

A A B B Pass-Transistor Network

(a)
A A B B Inverse Pass-Transistor Network F

A B A B AND/NAND F=AB F=AB

A B A B OR/NOR F=A+B F=A+B

A A A A EXOR/NEXOR F=A F=A

(b)

Inverters and Combinational Logic

Introduction to Digital Integrated Circuit Design

Lecture 3 - 67

4 Input NAND in CPL

Inverters and Combinational Logic

Introduction to Digital Integrated Circuit Design

Lecture 3 - 68

Transmission Gate

C A

C B A C B

C
C=5V A=5V B CL C=0V
Inverters and Combinational Logic Introduction to Digital Integrated Circuit Design Lecture 3 - 69

Pass Transistor XOR gate

Inverters and Combinational Logic

Introduction to Digital Integrated Circuit Design

Lecture 3 - 70

Outline

CMOS Inverter
response delays

Logic gates
Static CMOS
Conventional Static CMOS Logic Ratioed Logic Pass Transistor/Transmission Gate Logic

Dynamic CMOS
Domino np-CMOS

Tristates and Multiplexers

Inverters and Combinational Logic

Introduction to Digital Integrated Circuit Design

Lecture 3 - 71

Dynamic Logic
VDD Mp Out In1 In2 In3 CL PDN In1 In2 In3 PUN Out Me n network Mp p network CL VDD Me

2 phase operation:

Precharge Evaluation

Inverters and Combinational Logic

Introduction to Digital Integrated Circuit Design

Lecture 3 - 72

Example
VDD Mp Out Ratioless No Static Power Consumption A C Requires Clock B Noise Margins small (NML)

N + 1 Transistors

Me

Inverters and Combinational Logic

Introduction to Digital Integrated Circuit Design

Lecture 3 - 73

Dynamic 4 Input NAND Gate

VDD

Out
In1 In2 In3 In4

GND

Inverters and Combinational Logic

Introduction to Digital Integrated Circuit Design

Lecture 3 - 74

Cascading Dynamic Gates

VDD VDD

In Out1

Mp Out1

Mp Out2

In Out2 Me (a) Me

VTn V t (b)

Only 01 Transitions allowed at inputs!

Inverters and Combinational Logic Introduction to Digital Integrated Circuit Design Lecture 3 - 75

Domino Logic
VDD Out1

VDD VDD

Mp

Mp

Mr Out2

In1 In2 In3

PDN

In4

PDN

Static Inverter with Level Restorer

Me

Me

Inverters and Combinational Logic

Introduction to Digital Integrated Circuit Design

Lecture 3 - 76

Domino Logic - Characteristics

Only non-inverting logic Very fast - Only 1->0 transitions at input of inverter move VM upwards by increasing PMOS Adding level restorer reduces leakage and charge redistribution problems Optimize inverter for fan-out

Inverters and Combinational Logic

Introduction to Digital Integrated Circuit Design

Lecture 3 - 77

np-CMOS
VDD Mp VDD Out1 Me

In1 In2 In3

PDN

In4

PUN Out2

Me

Mp

Only 10 transitions allowed at inputs of PUN

Inverters and Combinational Logic

Introduction to Digital Integrated Circuit Design

Lecture 3 - 78

CMOS Circuit Styles - Summary

Inverters and Combinational Logic

Introduction to Digital Integrated Circuit Design

Lecture 3 - 79

Outline

CMOS Inverter
response delays

Logic gates
Static CMOS
Conventional Static CMOS Logic Ratioed Logic Pass Transistor/Transmission Gate Logic

Dynamic CMOS
Domino np-CMOS

Tristates and Multiplexers

Inverters and Combinational Logic

Introduction to Digital Integrated Circuit Design

Lecture 3 - 80

Tristates

Tristate buffer produces Z when not enabled

EN 0 0 1 1

A 0 1 0 1

Y Z Z 0 1

EN A Y

EN A EN Y

Inverters and Combinational Logic

Introduction to Digital Integrated Circuit Design

Lecture 3 - 81

Multiplexers

2:1 multiplexer chooses between two inputs

S 0 0 1 1

D1 X X 0 1

D0 0 1 X X

Y 0 1 0 1

S D0 D1 0 Y 1

Inverters and Combinational Logic

Introduction to Digital Integrated Circuit Design

Lecture 3 - 82

Gate Level Mux Design

Y = SD1 + SD0 (too many transistors)

How many transistors are needed? 20

D1 S D0

D1 S D0

4 2 4

2 4 2 2

Inverters and Combinational Logic

Introduction to Digital Integrated Circuit Design

Lecture 3 - 83

Transmission Gate Mux

Mux uses two transmission gates

Only 4 transistors

S D0 S D1 S Y

Inverters and Combinational Logic

Introduction to Digital Integrated Circuit Design

Lecture 3 - 84

Summary

Inverter response and delays

Three main operating regions (cutoff, linear, saturation) Noise margins tpHL, tpLH, tf, tr

Logic design styles

Static (ignores transient effects during switching)
Conventional static CMOS (PUP, PDN networks) Ratioed logic (resistive load on top of PDN network) Pass transistors/transmission gates (one transistor per input/good 0 and 1 values)

Dynamic (temporary stores signal values on capacitances of circuit nodes)

Domino (cascaded dynamic gates connected through inverters) np-CMOS (cascaded dynamic gates with alternating networks)

Inverters and Combinational Logic

Introduction to Digital Integrated Circuit Design

Lecture 3 - 85