Using Cadence Virtuoso XL Layout This tutorial contains the following topics: Creating a Layout of an Inverter o Creating a new

layout Cellview from an existing schematic o Connecting nodes with metal and polysilicon o Verify layout with DRC o Extracting layout and performing LVS

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Using Cadence Virtuoso XL Layout 1. Open the desired schematic cell. In this case, it is a simple inverter.

2. Go to Tools > Design Synthesis > Layout XL. A window pops up asking whether to create new or open existing. Choose the appropriate button. Next another window opens asking for the name of the layout cell. Use the default name.

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Using Cadence Virtuoso XL Layout 3. A new window will open called Virtuoso XL Layout Editing: Library Name Cell Name layout. Additionally, an LSW (layer select window) will open with a colorful palate. Each of these defines a processing step for the semiconductor process. If you do not see an LSW window, seek help.

4. First go to Options > Display and set the x and y snap size to 0.075. a. Go to Connectivity > Update > Components and Nets. A new window will open as shown below. Deselect I/O Pins, which will be the pins you assigned on the schematic and boundary for the time being.

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Using Cadence Virtuoso XL Layout

5. Now you might see the following layout. To see what the transistors actually look like, go to Options > Display. a. You can change the number of levels that are displayed for the cell by changing the stop parameter to something large like 32. b. Additionally, you can shortcut this step by typing Shift+f. To go back to the boundary view, type Ctrl+f.

6. Now your layout should have two clearly defined transistors. Is it clear which one is the PMOS device and NMOS device?

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Using Cadence Virtuoso XL Layout 7. Lets take a slight diversion. You should be VERY CLEAR on the relationship between the transistor layout picture and the device structure. a. Go to the LSW, and select nwell drw. This is the nwell region layer and drw stands for drawing. b. Select NV from the top menu. AV = all visible, NV = not visible, AS = all select, NS = not select. c. At this point, all other layers will disappear except from the nwell on the LSW. Now, you need to redraw the layout window. Go to window > redraw. Alternatively, you can type ctrl+r.

8. Now you will see one device sits in an nwell. Which device should sit in an nwell? 9. Next, select nactive on the LSW. DO NOT PRESS NV. Both layers should now be highlighted. Go to your window and type ctrl+r.

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Using Cadence Virtuoso XL Layout

The NMOS device is so-called because the channel is composed of n+ doped silicon. Can you see the channel here? Measure it with the ruler on the side toolbar. What is the length and width? Go back to your schematic. What was the minimum-sized device length and width? Why is it different from what is drawn? 10. Now select pactive on the LSW and redraw the window.

Now the window will have three colors. Measure the size of the pactive region and compare it to your schematic. Why is there a difference?

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Using Cadence Virtuoso XL Layout 11. Next select the poly region and redraw the window. What node does the poly region represent and what are the length and width of the intersection of the poly and nactive/pactive for the NMOS/PMOS devices?

12. Finally, select metal1 and redraw the circuit. What do these nodes represent?

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Using Cadence Virtuoso XL Layout 13. Now you should understand what the transistors look like and we can move forward to assembling the layout. It is straightforward to imagine arranging the NMOS and PMOS in a vertical fashion just as we would the schematic. You can move things from the Edit > Move selection or by changing the properties under which you will find an x- and y- coordinate.

14. Now connect the gates, drains and sources to one another with the metal 1 and poly layers. You can draw a connection by a. using the path command or b. drawing a metal rectangle of the appropriate dimensions. You should start by creating a power and ground rail for your cell. See below.

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Using Cadence Virtuoso XL Layout

15. Your schematic might look like something below. There is one more step. Remember that your nmos device has a bulk connection. In your schematic, it is connected to ground. Additionally, your pmos device is located in an nwell that must be connected to an nwell. Place a contact to the nwell and pwell on the layout. For the nwell, you can draw a large nwell region to accommodate for the ntap.

16. Finally, go back connectivity > update > components and nets. a. Select I/O pins. Change the Layer / Master to metal 1 drawing b. Then choose OK. You will now find four pin shapes on your layout. Put them on the appropriate node.

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Using Cadence Virtuoso XL Layout

17. Now your layout for the cell is complete. We need to verify the layout with DRC (design rule check ) and LVS (layout versus schematic). a. Go to Verify > DRC. A window will pop up. Make sure the appropriate technology (TechLib_tsmc03) is listed and a rules file (divaDRC.rul) exists. b. Select OK and look at the CIW window.

18. You may need to correct errors now. Some common errors include a. not being on the correct grid spacing. b. metal to metal spacings. Increase the spacing between the metal wires. c. Spacing between nwells and pwells. Increase the spacing between your nwell and pwells.
NOTE: In the future, you may consider running the DRC after you place your devices and before you do your wiring between transistors to make sure you are DRC clean at each

step of the layout. Continue to the next step after you have zero DRC errors. Save the DRC log file and submit it with your homework to the TA.

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Using Cadence Virtuoso XL Layout 19. Finally, we can begin our LVS. This is ESSENTIAL to verifying that the schematic and the layout are functionally the same. a. Go to Verify >Extract. This opens the extractor window. The important settings are the rules file which should be divaEXT.rul and the rules library which should be _TechLib_tsmc03. b. For the switch names, include the extract parasitic capacitors option. c. Press OK. d. In the CIW, you should see the extractor run a bunch of scripts. The extracted version has been created in your library and is the actual circuit.

20. Now run the LVS. a. Go to Verify > LVS. b. You may need to enter the some of the information about the extracted cell. The extracted cell should have the same name as the schematic. c. Type extracted for the view. d. Then press Run.

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Using Cadence Virtuoso XL Layout

21. After the LVS has run. a. You will get a message saying whether it succeeded (hopefully) or failed. b. Press OK. If it fails, you may need to save your schematic and try running it again. Otherwise you can click Info and then Run File to investigate the reason for failure.

22. Click on Output. There will be in this file a note that says whether the schematic and extracted version matches. If they do not, you need to look at your layout and discover why they do not match. Otherwise, you have almost finished.

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Using Cadence Virtuoso XL Layout 23. Finally, click on Build Analog. This makes a simulation file that will allow you to compare the actual layout to the schematic. Finally, in your library you will find new file outputs including the extracted and analog extracted view. 24. Before you close the LVS window, you can also experiment with parasitic probing. Open the extracted view and click on the parasitic probe button of the LVS window. It should provide you with the capacitance values when you select a net in the extracted view. 25. Now, you should have an av_analog_extracted view for your inverter among your many cellviews. This is the real circuit and most closely resembles the actual operation. When you are simulated your circuit in the analog environment, you can click on the setupf>environment tab and enter av_analog_extracted before schematic in the switch list. This will tell the simulator to use any extracted views for representing the inverter before using the schematic. a. First, recreate and display your netlist. You should see that the new netlist includes an av_analog_extracted view with the capacitors. b. Second, run the simulation and you should see results that are typically slower than if you had used the schematic.

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