MICROSTRIP NARROWBAND PASS

MICROSTRIP NARROWBAND PASS

CANDIDATE'S DECLARATION
I hereby declare that the work, which is being presented in the seminar, entitled
"LEAKAGE POWER REDUCTION IN CMOS CIRCUITS" in partial fulfillment for the
award of degree of "Master of Technology" in Dept.of Electronics & Communication
Engineering with specialization in VLSI and submitted to the department of Electronics &
Communication Engineering, Poornima College

of

Engineering, Rajasthan Technical

University is a record of my own investigations carried under the Guidance of Mr. Manish
Singhal,

Associate

Professor,

Department

of

Electronics

&

Communication

Engineering,PCE,jaipur.I have not submitted the matter presented in this report anywhere for
the award of anyother degree.

..
(Akshay Sharma)
M.Tech (VLSI Design)
Enrolment No: 12E2PCVLM4XP603
Poornima College of Engineering,Jaipur.

Counter Signed by:

(Mr. Manish Singhal), Associate Professor
Department of Electronics and Communication Engineering
Poornjma College of Engineering, Jaipur.

ii

ACKNOWLEDGEMENT
Certainly, help and encouragement from 'stack holders' are always appreciated and
here is golden chance to express my 'deepest thanks' and 'richest gratitude' towards personalities
who contributed their "value" to provide value to my dissertation work.
My deepest gratitude is to my Guide, Mr. Manish Singhal, Associate Professor,
Department of Electronics & Communication Engineering, Poornima College of
Engineering, Jaipur. I have been amazingly fortunate to have an advisor who gave me the
freedom to explore on my own and at the same time the guidance to recover when my steps
faltered. He taught me how to question thoughts and express ideas. His patience and support
helped me overcome many crisis situations and finish this dissertation. I hope that one day I
would

become

as

good

an

advisor

to

my students

as

he

has

been

to

me.

I am grateful to Dr. S. M. Seth,Chairman, Poornima Group of Colleges , Jaipur

and Mr. shashikant singhi,Director General of Poornima Group of Colleges, Jaipur for their
encouragement and practical advice. I am also thankful to him for properly and smooth running
of the seminar and studies in parallel.I am also grateful to the following former or current staff at
Poornima College of Engineering, Jaipur for their various forms of support during my seminar.
Lastly, I offer my regards to all of those who supported me in any respect during the completion
of the seminar.
AKSHAY SHARMA
M.TECH (VLSI DESIGN)
Enroll. No. - 12E2PCVLM4XP603

iii

Table of Contents
Candidate's Declaration ................................................................................................................ii
Acknowledgement .........................................................................................................................iii
Table of contents ............................................................................................................................iv
List of figures .................................................................................................................................vi
Abstract ..........................................................................................................................................1

CHAPTER-1
INTRODUCTION................................................................................................2-8
1.1. Multi-threshold CMOS.............................................................................................................2
1.2. Ground Bounce Basics..............................................................................................................4

CHAPTER-2
MULTI-THRESHOLD CMOS (MTCMOS)...................................................9-17
2.1. Outline of the multi-threshold cmos (MTCMOS)...................................................................9
2.2. Mtcmos circuit technique.......................................................................................................10
2.2.1. Standard MTCMOS circuits in SLEEP mode..............................................................10
2.2.2. Standard MTCMOS circuits in ACTIVE mode...........................................................12
2.3. Ground & power-gated inverters in sleep mode.....................................................................14
2.3.1. A ground-gated inverter................................................................................................14
2.3.2. A power-gated inverter.................................................................................................15

CHAPTER-3
GROUND BOUNCE........................................................................................18-29
3.1. Defining ground bounce.........................................................................................................18
iv

3.2. Cause of ground bounce.........................................................................................................20

3.3. Other cause of ground bounce................................................................................................22
3.4. Contributing factors of ground bounce...................................................................................23
3.5. Ground bounce demonstration board.....................................................................................23
3.5.1. Lead Inductance...........................................................................................................24
3.5.2. Other Packages.............................................................................................................25
3.5.3. Number of Outputs Switching.....................................................................................26
3.6. Test fixtures vs. Real systems.................................................................................................26
3.6.1. AC Loading Effects......................................................................................................26
3.6.2. LCR Tank Effect..........................................................................................................29

CHAPTER-4
GROUND BOUNCE MINIMIZATION....................................................... 30-32
4.1. Methods to minimize ground bounce.....................................................................................30
4.1.1. Flip Chip Device Packages.........................................................................................30
4.1.2. Slow Slew Rate..........................................................................................................31
4.2. General recommendations......................................................................................................31
4.2.1. Synchronous vs. Asynchronous....................................................................................31
4.2.2. Use Low Voltage Differential Signal (LVDS).............................................................31
4.2.3. Follow General Board Design Guidelines....................................................................31

CHAPTER-5
CONCLUSION......................................................................................................33
REFERENCES......................................................................................................34

List of figures
Figure No.

Particulars

Page No.

Figure 1.1

Circuit explaining ground bounce........................................................4

Figure 1.2

A typical output circuit..........................................................................6

Figure 1.3

The effect of internal inductance circuit...............................................6

Figure 1.4

The bypass capacitor provides local charge storage.............................7

Figure 2.1

Schematic of MTCMOS..........................................................................9

Figure 2.2

Power-gated MTCMOS circuit in SLEEP mode................................10

Figure 2.3

Ground-gated MTCMOS circuit in SLEEP mode..............................11

Figure 2.4

Power & ground-gated MTCMOS circuit in SLEEP mode................11

Figure 2.5

Power-gated MTCMOS circuit in ACTIVE mode.............................12

Figure 2.6

Ground-gated MTCMOS circuit in ACTIVE mode...........................12

Figure 2.7

Power & ground-gated MTCMOS circuit in ACTIVE mode.............13 A

Figure 2.8

ground-gated inverter......................................................................14 A

Figure 2.9

power-gated inverter........................................................................15

Figure

The voltage waveforms of the sleep signal and the virtual ground line

2.10
in a ground-gated MTCMOS circuit during different modes of operation....................................16
Figure 3.1

Ground Bounce Circuit Model..............................................................18

Figure 3.2

How ground bounce is generated..........................................................19

Figure 3.3

Standard ground bounce circuit.............................................................21

Figure.3.4

Ground Bounce/VDD Bounce...............................................................22

Figure.3.5

Ground Bounce Demonstration Board Block Diagram.........................24

Figure.3.6

Noise vs. Package Configuration..........................................................25

Figure.3.7

Standard Test Load...............................................................................27

Figure.3.8

Test fixture............................................................................................28

Figure.3.9

System Models......................................................................................28
vi