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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 1, JANUARY 2013

A Multilevel Inverter Scheme With Dodecagonal Voltage Space Vectors Based on Flying Capacitor Topology for Induction Motor Drives
Jaison Mathew, Member, IEEE, P. P. Rajeevan, K. Mathew, Najath Abdul Azeez, and K. Gopakumar, Fellow, IEEE
AbstractThis paper presents a multilevel inverter topology suitable for the generation of dodecagonal space vectors instead of hexagonal space vectors as in the case of conventional schemes. This feature eliminates all the 6n 1 (n = odd) harmonics from the phase voltages and currents in the entire modulation range with an increase in the linear modulation range. The topology is realized by ying capacitor-based three-level inverters feeding from two ends of an open-end winding induction motor with asymmetric dc links. The ying capacitor voltages are tightly controlled throughout the modulation range using redundant switching states for any load power factor. A simple and fast carrier-based space-vector pulsewidth modulation (PWM) scheme is also proposed for the topology which utilizes only the sampled amplitudes of the reference wave for the PWM timing computation. Index TermsDodecagonal space vectors, ying capacitor, multilevel inverters, open-end winding, space-vector pulsewidth modulation (PWM).

I. INTRODUCTION

ULTILEVEL inverters are increasingly being used in medium- and high-power electric-drive applications as they have lesser electromagnetic interference, lower switch voltage stress, and harmonic distortion compared to two-level inverters. The switching frequency of the inverters is always kept low to reduce switching losses and for the voltage control, synchronous pulsewidth modulation (PWM) is preferred to avoid subharmonics in the phase voltages. Neutral-pointclamped (NPC) inverters, cascaded H-bridge, and ying capacitor multilevel inverters are some of the popular schemes used in high-power applications. Hybrids of these basic topologies as well as some generalized topologies have also been proposed [1][9]. Multilevel inverters can also be realized by feeding the induction motor from both ends (open-end winding) [10], [11]. It is found that in the overmodulation range,

Manuscript received January 17, 2012; revised March 1, 2012 and March 30, 2012; accepted April 6, 2012. Date of current version September 11, 2012. Recommended for publication by Associate Editor R. Burgos. J. Mathew is with the Department of Electrical Engineering, Rajiv Gandhi Institute of Technology, Kottayam 686001, India, and also with the Department of Electronic Systems Engineering (formerly Centre for Electronics Design and Technology), Indian Institute of Science, Bangalore 560012, India (e-mail: jaison@ieee.org). P. P. Rajeevan, K. Mathew, N. A. Azeez, and K. Gopakumar are with the Department of Electronic Systems Engineering (formerly Centre for Electronics Design and Technology), Indian Institute of Science, Bangalore 560012, India (e-mail: prajeev@cedt.iisc.ernet.in; kmathewmace@gmail.com; najath@gmail.com; kgopa@cedt.iisc.ernet.in). Digital Object Identier 10.1109/TPEL.2012.2195784

there will be substantial amount of low-frequency harmonics, especially fth and seventh harmonics in the motor phase voltage if we are using PWM based on conventional hexagonal voltage space-vector structure. These harmonics make the current control schemes in this modulation range inaccurate and complex compensation techniques are required for smooth current control [12], [13]. A 12-sided polygonal space-vector (dodecagonal)-based multilevel inverter is an improvement over the conventional hexagonal space-vector-based multilevel inverters in this respect. Here, all 6n 1 (n = 1, 3, 5 . . .) harmonics will be absent in the entire modulation range including overmodulation with an extension in the linear modulation range [14]. A dodecagonal space-vector generation scheme for multilevel operation, based on NPC inverter and open-end winding induction motor, is presented in [15]. A cascaded H-bridge scheme is proposed in [16]. Even though the harmonic distortion is reduced in these schemes, the neutral-point voltage uctuation is still a major issue in [15] and the cascaded H-bridge topology in [16] requires a large number of isolated power sources. In this paper, the feasibility of a ying capacitor topology for the generation of multilevel dodecagonal space vectors is explored. The neutral-point charge-balancing problems reported in [15] are not present in this topology and the number of power supplies required is much lesser compared to that in [16]. For controlling the capacitor voltages in ying capacitor multilevel inverters, hysteresis-type charge controllers are used in [17]. A phase-shifted carrier scheme with equal charging and discharging duty cycles for the capacitors in a carrier cycle is proposed in [18]. But the charge control in this approach is heavily dependent on load characteristics and charge balancing at low-speed operation is problematic for motor drive applications [19]. In this paper, a hysteresis charge controller similar to that in [17] is used. For the voltage control, space-vector PWM is preferred over sine-triangle PWM as it gives more linear modulation range [20][22]. In this paper, a carrier-based space-vector PWM technique is proposed where only the sampled amplitudes of the reference waves are used to arrive at the PWM timing calculations and as such, the computation is faster compared to conventional space-vector modulation schemes.

II. INVERTER POWER STAGE AND SPACE-VECTOR DIAGRAMS The power circuit for the generation of dodecagonal space vectors is shown in Fig. 1(a). A three-level ying capacitor inverter feeds an induction motor from one end generating pole voltages, kVdc , 0.5 kVdc , and 0 kVdc , with respect to point O

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Fig. 1.

(a) Proposed IM drive for the generation of multilevel dodecagonal space vectors. (b) Multilevel dodecagonal space-vector diagram. TABLE I SWITCH STATES AND POLE VOLTAGES CORRESPONDING TO PHASE-A WINDING

and another three-level inverter from the other end giving pole voltages, 0.366 kVdc , 0.183 kVdc , and 0 kVdc , with respect to point O . Here, Vdc (volts) represents the radius of the space-vector diagram of conventional two-level inverters. The inverters are fed from isolated dc sources having their voltages in the ratio 1:0.366. This ratio of voltage can easily be obtained from stardelta combination of transformer windings with the 3 + 1 : 1 [14]. For same number of turns as 1 : 0.366 = 0.366 kVdc example, to get 1 kVdc , rectier stage generating is cascaded with rectier stage generating 3 0.366 kVdc . The use of this particular transformer winding connections will help improve the input side power factor also [15]. Now, with reference to Fig. 1(a), let a ctitious point n be the neutral of the system, as the system by itself does not have a neutral, and for balanced loads Vao = Van + Vn o ; Vn o = Van Vbo = Vbn + Vn o ; Vco = Vcn + Vn o (1) (2) Vcn = Vco Vn o (3) (4)

1 (Vao + Vbo + Vco ) 3 = Vao Vn o ; Vbn = Vbo Vn o ;

Vn o = Va n

1 (Va o + Vb o + Vc o ) 3 = Va o Vn o ; Vb n = Vb o Vn o

Vc n = Vc o Vn o . Therefore, the phase voltages are Vaa = Van Va n ;

(5)

Vcc = Vcn Vc n . (6) The resultant voltage space vector is given by VR = Vaa + Vbb ej 120 + Vcc ej 240 .

Vbb = Vbn Vb n ;

(7)

Out of the possible voltage-space vectors that can be generated by the inverter power structure, only those vectors are chosen whose tips lie on the vertices of 12-sided polygons. The dodecagons used in this study are shown in Fig. 1(b) (AF). The dodecagon A has the maximum radius and is equal to 1.225 kVdc . The radii of the dodecagons have magnitudes in the ratio 1:cos(15):cos(30):cos(45):cos(60):cos(75). All these do-

decagons lie inside an outermost hexagon pattern with radius equal to 1.366 kVdc which is not shown in the gure, but will be used for PWM timing calculations. It can be seen in the gure that the sectors are partitioned into many triangular regions for multilevel operation. The space vectors are numbered from 0 to 72 with vector numbers 112 corresponding to the dodecagon F, 1324 corresponding to the dodecagon E, etc. The spacevector points in Fig. 1(b) are obtained from the phase voltage information, using (7). Table I gives the switching states and the

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TABLE II VECTOR LOCATIONS AND THE CORRESPONDING SWITCHING STATES

relevant pole voltages for phase-A winding of the system. The effective pole voltage of the system for phase A is Va o Va o , which is the same as Va a + Voo where Va a is the phase voltage of phase A and Voo is the common-mode voltage of the system. The pole voltage information reveals that the system makes up a nine-level inverter (asymmetric levels). A list of all space-vector locations with their multiplicities and corresponding switching states is given in Table II. In this table, state 2 corresponds to an inverter pole voltage of kVdc and state 1 corresponds to an inverter pole voltage of 0.5 kVdc for INV-I. Similarly, state 2 corresponds to an inverter pole voltage of 0.366 kVdc and state 1 corresponds to an inverter pole voltage of 0.183 kVdc for INV-II. State 0 and state 0 correspond to the pole voltage

of 0 V. The rst triplet in the column under switching states in Table II represents the pole voltage levels of INV-I whereas the second set of three numbers gives the pole voltage levels of INV-II. The value of k decides the length of the space-vector diagram. The selection of the value of k and the extension of linear modulation range offered by dodecagonal switching can be explained as follows. Let us rst consider the case of space-vector modulation applied to two-level inverters, based on hexagonal space-vector diagram. Vdc represents the radius of the hexagonal spacevector diagram in two-level inverters. The limit of linear modulation occurs at a phase voltage Vdc Cos(30) 2/3 = 0.577 Vdc which corresponds to the radius of the largest circle that can

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be inscribed in the hexagon. At the rated frequency, the rated voltage of the motor corresponds to the maximum fundamental voltage that may be applied to the motor from the inverter. If 100% modulation represents 50 Hz operation (six-step mode), then the fundamental component of the six-step mode (0.637 Vdc ) corresponds to the rated voltage of the motor. Thus, the limit of linear modulation occurs at a modulation index of 90.6% (0.577/0.637). Similarly, for space-vector modulation based on dodecagonal space-vector diagram, the 50 Hz operation corresponds to the 12-step mode (m = 100%) and the tips of the switched vectors lie at the vertices of the outermost dodecagon. If V represents the radius of the outermost dodecagon, the fundamental phase voltage at this operating mode is 0.659 V. The limit of linear modulation occurs at a phase voltage V Cos(15) 2/3 = 0.644 V which corresponds to the radius of the largest circle that can be inscribed in the outermost dodecagon. Thus, the limit of linear modulation occurs at a modulation index of 97.7% (0.644/0.659). Hence, there is an extension of linear modulation range compared to hexagonal spacevector diagram-based space-vector modulation. For the purpose of comparison, the fundamental voltage obtained in the dodecagonal space-vector diagram at the 12-step operation mode is also made equal to 0.637 Vdc at the rated frequency mentioned previously. Hence, 0.659 V = 0.637 Vdc , i.e., V = 0.966 Vdc . Thus, the radius of the outermost dodecagon V is related to the radius Vdc of the hexagon in two-level inverter spacevector diagram by this expression. This means that the machine phase windings are less voltage stressed in the case of dodecagonal drive compared to hexagonal drives also. Now, in terms of the dc-link voltage, the radius of the outermost dodecagon is 1.225 kVdc . Therefore, 1.225 kVdc = 0.966 Vdc ; i.e., the value of k is 0.789. Hence, the dc-bus magnitudes of INV-I and INV-II required are, respectively, 0.789 and 0.288 Vdc . Thus, the switch voltage rating required in this topology is quite low and is equal to 0.395 Vdc for INV-I and 0.144 Vdc for INV-II compared to Vdc in the two-level case. It is already mentioned that elimination of 6n 1 (n = 1, 3, 5 . . .) harmonics occurs if we use dodecagonal vector switching. In the topology described in this paper, the tips of the vectors that are switched lie at the vertices of the 12-sided polygons (adjacent vectors are 30 separated). As illustrated in [11], this set of 12 space vectors can be divided into two sets of vectors, separated by 30 . If these two sets of vectors are switched with a 30 phase delay in time, the fundamental component due to these two sets gets added up whereas the (6n 1)th (n = 1, 3, 5 etc.) order harmonics of the leading set of vectors move 150 in the anticlockwise direction and align exactly in the opposition to the (6n 1)th (n = 1, 3, 5, etc.) order harmonics of the lagging set of switching vectors. Hence, all (6n 1)th (n = 1, 3, 5, etc.) order harmonics (negative sequence components) of two sets of vectors cancel each other. Similarly, the (6n +1)th (n = 1, 3, 5, etc.) order harmonic components (positive sequence components) produced by the leading set of vectors rotate 210 in the clockwise direction and come exactly in opposition to those of the lagging set and hence cancel each other. Thus, a 30 disposition of switching vectors cancels all the harmonics of the order 6n 1 (n = 1, 3, 5 . . .)from the motor phase voltages.

III. PWM TIMING CALCULATION The intention of partitioning the space-vector diagram to many subregions in multilevel inverters is to reduce the error vector between the reference vector and the switched vector so that the current ripple is minimized. In two-level inverters, for the same output voltage, this error vector is much larger than that in multilevel inverters and consequently, the torque ripple and current harmonics will be higher [23]. Here also, we have to switch the nearest vectors around the reference vector and to use carrier-based space-vector PWM for voltage control. The key idea is to switch the nearby vectors at every sampling interval such that the volt-second balance is maintained. The PWM computation strategy presented here makes use of the sampled amplitudes of three reference voltages like in the familiar twolevel carrier-based schemes [21]. The PWM timings are derived using the conventional multilevel hexagonal structure with the same radius for the 12-sided as well as the hexagonal structure. So, knowing the PWM timings for the conventional hexagonal structure, the PWM for the present 12-sided structure can be easily derived. The modulation scheme presented in this paper is more generic, easier to comprehend and implement when compared to the multilevel dodecagonal PWM scheme in [15] that used six reference voltages. The steps in the PWM timing calculation used in this paper are as follows: 1) generation of the three-phase reference voltage; 2) sample the reference voltage to nd the 60 hexagonal sector, where at that particular sampling instant the reference vector is located, by using the reference voltage magnitudes; 3) calculate the time durations required in a switching period for the active and zero vectors for the hexagonal sector for conventional two-level space-vector modulation using the sampled amplitudes; 4) locate the dodecagonal sector (30 sectors) and calculate the dodecagonal timing from the hexagonal timing information in step 3; 5) nd the timings for the vectors corresponding to all the triangular regions inside the dodecagonal sectors; 6) search for the triangular region in which the timings corresponding to the vectors at the vertices of the triangular region are all positive and switch the corresponding vectors as per the PWM timings obtained. These steps are elaborated as follows. Assume that we are using V/f method of speed control. The amplitude and frequency requirement decide the locus of the reference voltage space vector (Vref ) which is shown in Fig. 2. The three-phase waveform corresponding to this reference space-vector trajectory can be obtained using the transformation 2/3 0 Va Vb = 1/3 1/ 3 V (8) V Vc 1/3 1/ 3 where V and V are the projections of the reference space vector at every sampling interval onto the and axes where -axis is placed along the A-phase axis. The space-vector diagram can be divided into to six hexagonal sectors as in two-level

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Fig. 3. Fig. 2. Reference vector and the dodecagonal sectors 1 and 2 in the spacevector diagram.

Dodecagonal subsectors 1 and 2 inside a dodecagonal sector.

rst dod-sector can be obtained from the volt-second balance equations Vref Ts = (|V1Hex | 0)T1Hex + (|V2Hex | 60)T2Hex = (|V1Do d | 0)T1Do d + (|V2Do d | 30)T2Do d . (11) The unknowns T1Do d and T2Do d in the aforementioned equation can be easily found out by equating the real and imaginary parts of the aforementioned equation. We get for dod-sector 1 T1Do d T2Do d and for dod-sector 2 T1Do d T2Do d = = 1 0 1 3 T1Hex T2Hex T1Hex . T2Hex (12)

space-vector PWM [20]. Let the sectors be numbered from 1 to 6 in anticlockwise direction starting from the axis of phase-A winding (see Fig. 2). We can identify the sectors from the sampled amplitudes of the reference voltage waveform. For example, if |Va | > |Vb | > |Vc | Sector 1 . Further, the timings of the active vectors for the two-level hexagonal space-vector modulation T1Hex and T2Hex for a sector can also be computed [21]. For odd numbered sectors T1Hex T2Hex Vm ax Vm id = . |V1Hex | Vm id Vm in Ts (9)

For even numbered sectors T1Hex T2Hex = Vm id Vm in |V1Hex | Vm ax Vm id Ts (10)

3 0 1 1

(13)

where Ts denotes the sampling period, Vm ax , Vm id , and Vm in represent the maximum, mid, and minimum amplitudes of the reference wave at that particular sampling instant, respectively, and |V1Hex | is the radius of the outermost hexagonal pattern of the space-vector diagram due to the present system. Let the voltage space vector is in sector 1. The timings obtained give information on how long the hexagonal vectors V1Hex and V2Hex , shown in Fig. 2, are to be switched in a sampling period. The analysis presented here applies when the reference vector is in other sectors also. After every 60 , we are relabeling V2Hex as V1Hex like that in conventional space-vector modulation and that is why the timings are different for odd and even sectors. Now that we have obtained the hexagonal timings, we can extend the analysis to incorporate the dodecagonal sectors. Each 60 hexagonal sector can be partitioned into two subsectors each spanning 30 . These dodecagonal subsectors will be called dodsectors and the dod-sectors 1 and 2 for the rst hexagonal sector are shown in Fig. 2. The ctitious vectors V1Do d and V2Do d shown in the gure have the same vector length as V1Hex and V2Hex . The reference vector Vref will be in the rst dod-sector if T1Hex > T2Hex . Else it will be in the second dod-sector. It is apparent that a reference vector situated in the rst dod-sector can be realized using the dodecagonal vectors V1Do d and V2Do d also instead of the hexagonal vectors V1Hex and V2Hex . Similar is the case with a reference vector situated in the second dodsector. The required dodecagonal timing information for the

After every 30 , we are relabeling V2Do d as V1Do d like that in the case of hexagonal sectors. There are 12 such dodecagonal sectors and thus we are able to get dodecagonal vector switching timings instead of hexagonal vector timings for the sampled reference wave. In other words, we get equivalent timings in a 30 resolution. We need a resolution of 15 to accurately track all the triangular regions inside the space-vector diagram, shown in Fig. 1(b). For that, each dod-sector is further divided into two subsectors, each spanning 15 . The dod-subsectors 1 and 2 for the rst dod-sector are indicated in Fig. 3. The reference vector will be in the dod-subsector 1 if T1Do d > T2Do d . Otherwise, it will be in the dod-subsector 2. If the reference vector is, say, in the dod-subsector 1, it can be realized using the vectors V1Do d and V2Do d as well as V1Do d15 and V2Do d15 which are also shown in the gure. V1Do d15 and V2Do d15 can also be considered as the active vectors of a 15 shifted dodecagonal sector with respect to the A phase axis and T1Do d15 and T2Do d15 represent the corresponding timings. For the reference vector in the dod-subsector 1, the timings for the active vectors of the 15 rotated dodecagon can be computed using volt-second balance equations similar to the aforesaid dodecagonal case as T1Do d15 T2Do d15 = 0.5176 0.5176 0 .5176 2 T1Do d T2Do d (14)

when the reference vector is in the dod-subsector 2, the timings for the corresponding 15 rotated dodecagon vectors are T1Do d15 2 0.5176 T1Do d = . (15) T2Do d15 0.5176 0.5176 T2Do d

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Fig. 4.

General triangular region formed by vectors V 1 , V 2 , and V 0 . Fig. 5. One typical limb of the inverter topology.

Now we have to consider the case when the reference vector is inside a triangular region. For that, a typical situation is illustrated in Fig. 4 where the triangular region is formed by the vectors V1 , V2 , and V0 . Let V1 and V2 represent the active vectors corresponding to a dod-sector and let T1 and T2 represent the respective timings. The required active vectors are V1 and V2 and the pivot vector is V0 . Using the concept of volt-second balance again, the timings can be obtained as T0 = T1 = T2 = |V1 | (T1 + T2 ) |V2 | Ts cos(15) |V0 | |V2 | cos(15) 2 |V1 | T1 cos(15) |V0 | T0 2 |V1 | cos(15) 2 |V2 | T2 cos(15) |V0 | T0 . 2 |V2 | cos(15) (16) (17) (18)

1 dvC 1 S = [ 1 1 ] a 1 ia . Sa 2 dt C1

(21)

If the T0 , T1 , and T2 timings are positive, then it implies that the reference vector is within the triangular region formed by V0 , V1 , and V2 . So the approach used here is to locate the 15 dod-subsector from the reference voltage waveform rst and then compute the pivot and active vector timings for all the triangular regions that make up the 15 region. Only one triangular region will give positive values for all T0 , T1 , and T2 and that triangle is taken for switching the power devices to realize the reference waveform in tandem with the computed timings. Since the algorithm requires only a few scaling operations, summations, and comparisons, the method is much faster compared to conventional multilevel space-vector modulation algorithms. IV. CAPACITOR CHARGE CONTROL One typical limb of the inverter is shown in Fig. 5, where the power devices are represented by ideal switches and VDC represents the dc-link voltage. The assumed positive direction of load current and capacitor current are also indicated. It is clear that switches Sa 1 and Sa 1 are to be complementarily switched to eliminate the possibility of short circuiting two different voltage sources. Similar is the case with Sa 2 and Sa2 . The charging status of a capacitor is decided by the current direction and switching functions Sa 1 and Sa 2 which can take on values 1 and 0. The capacitor current can be written as ic = (Sa 1 Sa 2 )ia . The state variable expressions are then Vao = [ 1 1 ] Sa 1 VC 1 + [Sa 1 ] VDC Sa 2 (20) (19)

For controlling the voltage of capacitor C1 , depending on the current direction, we can switch the devices properly in every sampling period, while ensuring that the required voltage level is always generated. A hysteresis controller with zero comparator band is used and the control action occurs in every sampling period. Even though the time duration for which control action is taking place is dependent on the pulse width demanded by the switching vector, as the sampling rate is high, the capacitor voltage can be controlled with good regulation in the entire modulation range. The capacitor can be selected by considering the average delay of one sampling period for the control action and the permissible deviation in the capacitor voltage. The capacitor value can be selected as C= Im Ts V (22)

where Im denotes the peak load current and V is the maximum ripple voltage allowed in a switching period Ts . A multilevel dodecagonal space-vector generation scheme using NPC inverters was proposed in [15]. The neutral-point voltage uctuation was a major concern there and was controlled to some extent by sizing the capacitors accordingly. But in every switching period, the NPC voltage control was not possible and the voltage uctuation could be averaged out only over a fundamental period. In this paper, this issue has been solved by using a ying capacitor topology where we can provide corrective action for the capacitor voltages in every sampling period. So, a tighter control of capacitor voltages is possible for the full modulation range using redundant switching states for any load power factor. V. EXPERIMENTAL RESULTS A 3.7-kW, 415-V, 50-Hz, 4-pole induction motor was used for the experiment. For the speed control, a DSP (TMS320F2812) was used which computes the PWM timings using the sampled reference wave amplitudes stored in a lookup table. The DSP outputs the triangle number within which the reference wave is located and further, two PWM outputs corresponding to active vectors are also generated by the DSP. These signals are decoded by a eld-programmable gate array (FPGA) (SPARTAN XC3S200) to generate the actual gate-timing waveforms for the switching devices. A comparator outside the DSP gives information regarding the current direction. For controlling the

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Fig. 6. Voltage and current waveforms of phase A at 5 Hz operation. x-axis: 50 ms/div and y-axis: 1) phase voltage 50 V/div; 2) pole voltage Va o 150 V/div; 3) pole voltage Va o 150 V/div; and 4) phase current 2 A/div.

Fig. 7. Capacitor ripple voltages of phase A capacitors at 5 Hz operation. x-axis: 50 ms/div and y-axis: 1) phase voltage 50 V/div; 2) ripple voltage of capacitor C1 5 V/div; 3) ripple voltage of capacitor C1 5 V/div; and 4) phase current 2 A/div.

capacitor voltage, the ADC block inside the DSP samples the capacitor voltages and depending on the current direction, the DSP generates signals on six of its output pins, each signal representing whether a capacitor is to be charged or discharged. These signals are used by the FPGA to decide on the actual gating signals so that the required voltage levels are generated while satisfying the capacitor voltage balancing requirements. The motor is run at no load and the results are taken with the motor running under steady state at different operating frequencies. The motor is then accelerated up to rated speed using an open-loop V/f control. Finally, the capacitor charge balancing is illustrated by disabling the charge control scheme and enabling it afterward. For fundamental frequency of operation of 10 Hz and above till 15 Hz, the number of samples per sector is taken as 10. This means that the switching frequency is 120 times the fundamental frequency. For operation above 15 Hz and below 25 Hz, the number of samples per sector is taken as 8. For operation above 25 Hz and below 40 Hz, the number of samples is taken as 4; while beyond this frequency, the number of samples is taken as 2. This nally leads to switching points only at the vertices of the outer most dodecagon where one sample is taken at the start of the sector. Throughout the modulation range above 10 Hz, synchronous PWM is used where samples in a sector are synchronized with the start of the sector. Below 10 Hz, a carrier frequency of 1.2 KHz was used and as the frequency modulation ratio is high, asynchronous PWM is used. The experimental results under steady-state operating conditions are shown in Figs. 617. The PWM voltage waveforms maintain all symmetries and it is observed that the phase current of the motor is nearly sinusoidal. From the harmonic spectrum of the phase voltages, it can be seen that the 6n 1 (n = odd)harmonics are completely absent in the phase voltages and phase currents. The subharmonics are also absent due to synchronous PWM. The individual switching frequency of the inverters is lesser than the carrier frequency as can be seen from the pole voltages. For example, at 40 Hz, the carrier frequency is 960 Hz. But the inverters, INV-I and INV-II switch at 720 Hz (1840). The switching frequency of individual IGBTs is only half this value. Further, the waveforms also show that the capacitor voltages are well balanced and the peak-to-peak ripple voltage is less than 2 V in all modulation

Fig. 8. Voltage and current waveforms of phase A at 20 Hz operation. x-axis: 10 ms/div and y-axis: 1) phase voltage 100 V/div; 2) pole voltage Va o 100 V/div; 3) pole voltage Va o 200 V/div; and 4) phase current 2 A/div.

Fig. 9. Capacitor ripple voltages of Phase A capacitors at 20 Hz operation. x-axis: 10 ms/div and y-axis: 1) phase voltage 100 V/div; 2) ripple voltage of capacitor C1 5 V/div; 3) ripple voltage of capacitor C1 5 V/div; and 4) phase current 2 A/div.

Fig. 10. (a) and (b) Normalized harmonic spectrum of phase voltage and current, respectively, at 20 Hz operation.

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Fig. 11. Voltage and current waveforms of phase A at 40 Hz operation. x-axis: 5 ms/div and y-axis: 1) phase voltage 200 V/div; 2) pole voltage Va o 150 V/div; 3) pole voltage Va o 150 V/div; and 4) phase current 2 A/div.

Fig. 15. Capacitor ripple voltages of Phase A capacitors at 49.9 Hz Operation. x-axis: 5 ms/div and y-axis: 1) phase voltage 200 V/div; 2) ripple voltage of capacitor C1 5 V/div; 3) ripple voltage of capacitor C1 5 V/div; and 4) phase current 2 A/div.

Fig. 12. Capacitor ripple voltages of Phase A capacitors at 40 Hz operation. x-axis: 5 ms/div and y-axis: 1) phase voltage 200 V/div; 2) ripple voltage of capacitor C1 5 V/div; 3) ripple voltage of capacitor C1 5 V/div; and 4) phase current 2 A/div.

Fig. 16. Voltage and current waveforms of phase A at 50 Hz operation. x-axis 5 ms/div and y-axis 1) phase voltage 200 V/div; 2) pole voltage Va o 150 V/div; 3) pole voltage Va o 150 V/div; and 4) phase current 2 A/div.

Fig. 13. (a) and (b) Normalized harmonic spectrum of phase voltage and current, respectively, at 40 Hz operation. Fig. 17. (a) and (b) Normalized harmonic spectrum of phase voltage and current, respectively, at 50 Hz operation.

Fig. 14. Voltage and current waveforms of phase A at 49.9 Hz operation. x-axis: 5 ms/div and y-axis: 1) phase voltage 200 V/div; 2) pole voltage Va o 150 V/div; 3) pole voltage Va o 150 V/div; and 4) phase current 2 A/div.

ranges of operation. Figs. 18 and 19 show the results during acceleration of the motor. It is seen that the capacitor voltages are fairly held constant during the period of acceleration and

Fig. 18. Transition from 24 steps to 12 steps. x-axis 10 ms/div and y-axis 1) phase voltage 100 V/div; 2) voltage across capacitor C1 100 V/div; 3) voltage across capacitor C1 100 V/div; and 4) phase current 2 A/div.

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starting prole of the motor, demonstrating the capability of the control scheme to charge up the capacitors to the rated voltage from rest. VI. CONCLUSION The space-vector diagram used in this study, realized by ying capacitor-based three-level inverters feeding from two ends of an open-end winding induction motor, is characterized by dodecagonal space vectors which eliminates all 6n 1 (n = odd)harmonics from the phase voltage in the entire modulation range with an extension of the linear modulation range and with reduced voltage stress in the phase windings. There is no issue of neutral-point voltage unbalance as in the NPC inverter and the number of power supplies required is much lesser compared to cascaded H-bridge multilevel inverters or NPC-based dodecagonal voltage space-vector generation schemes. Further, the capacitors have inherent charge balancing capability in the entire modulation range. For the voltage control, a PWM technique is used where only the sampled amplitudes of the reference waveform are utilized to arrive at the PWM timing calculations and as such, the computation is faster than the conventional space-vector approaches. The proposed topology with the synchronous PWM operation may be extended to higher power levels making it useful in medium- and high-power electric-drive applications. REFERENCES
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Fig. 19. Acceleration prole of the motor. x-axis 1 s/div and y-axis 1) phase voltage 100 V/div; 2) voltage across capacitor C1 100 V/div; 3) voltage across capacitor C1 20 V/div; and 4) phase current 2 A/div.

Fig. 20. Disabling the charge control scheme of capacitors of phase A at time A and reestablishing the charge control at B, 30 Hz operation. x-axis 0.5 s/div and y-axis 1) capacitor voltage Vc 1 100 V/div; 2) capacitor voltage Vc 1 20 V/div; and 3) phase Current iL 2 A/div.

Fig. 21. Disabling the charge control scheme of capacitors of phase A at time A and reestablishing the charge control at B, 46 Hz operation. x-axis 0.5 s/div and y-axis 1) capacitor voltage Vc 1 100 V/div; 2) capacitor voltage Vc 1 , 20 V/div; and 3) phase current iL 2 A/div.

Fig. 22. Voltage and current waveforms of Phase A during starting up of the motor. x-axis 1 s/div and y-axis: 1) phase voltage 200 V/div; 2) voltage across capacitor C1 100 V/div; 3) voltage across capacitor C1 20 V/div; and 4) phase current 2 A/div.

the phase current is smooth without much glitches. Two typical cases where the effectiveness of the charge control scheme in regaining the charge balance are illustrated in Figs. 20 and 21. It can be seen from the gures that the capacitors regain the voltage levels within a fraction of a second. Fig. 22 shows the

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K. Mathew received the B.E. degree in electronics and communication engineering from K.V.G Engineering College, Mangalore, India, in 1994, and the M.Tech. degree in electronic design from the Centre for Electronics Design and Technology, Indian Institute of Science, Bangalore, India, in 2006. He is currently working toward the Ph.D. degree at the Centre for Electronics Design and Technology, Indian Institute of Science, Bangalore. He is a Member of the faculty with the Department of Electronics Engineering, M.A College of Engineering, Kothamangalam, India. His research interests include embedded systems, power electronics, and electromechanic systems.

Najath Abdul Azeez received the B.Tech. degree from the National Institute of Technology, Calicut, India, in 2003 and the M.Tech. degree from the Indian Institute of Science, Bangalore, India, in 2008. He is currently working toward the Doctoral degree at the Department of Electronic Systems Engineering (formerly Center for Electronics Design and Technology), Indian Institute of Science. His research interests include power converters and drives.

Jaison Mathew (S96M02) received the B.Tech. degree in electrical engineering from the Rajiv Gandhi Institute of Technology, Kottayam, India, in 1998 and the M.Tech. degree in power systems from the College of Engineering, Trivandrum, India, in 2001. He is currently working toward the Ph.D. degree at the Department of Electronic Systems Engineering, Indian Institute of Science, Bangalore, India. He is a Faculty with the Department of Electrical Engineering, Rajiv Gandhi Institute of Technology. His research interests include power converters, motor drives, and power quality.

K. Gopakumar (M94SM96) received the B.E., M.Sc. (Engg.), and Ph.D. degrees from the Indian Institute of Science, Bangalore, India, in 1980, 1984, and 1994, respectively. He was with the Indian Space Research Organization, Bangalore, from 1984 to 1987. He currently holds the position of Chairman and Professor at the Department of Electronics System Engineering (formerly Center for Electronics Design and Technology), Indian Institute of Science. His research interests include PWM converters and high power drives. He is a fellow of the Institution of Electrical and Telecommunication Engineers India and Indian National Academy of Engineers. Dr. Gopakumar is currently an Associate Editor of the IEEE TRANSACTION ON INDUSTRIAL ELECTRONICS.

P. P. Rajeevan received the B.Tech. degree in electrical engineering from the University of Calicut, Kerala, India, and the M.E. degree in power electronics from Bangalore University, Bangalore, India. He is currently working toward the Ph.D. degree at the Centre for Electronics Design and Technology, Indian Institute of Science, Bangalore. His research interests include multilevel power converters, drives, PWM techniques, and power quality.