Assembly and Reliability of Lead-Free Solder Joints
By John H. Lau and Ning-Cheng Lee
()
About this ebook
This book focuses on the assembly and reliability of lead-free solder joints. Both the principles and engineering practice are addressed, with more weight placed on the latter. This is achieved by providing in-depth studies on a number of major topics such as solder joints in conventional and advanced packaging components, commonly used lead-free materials, soldering processes, advanced specialty flux designs, characterization of lead-free solder joints, reliability testing and data analyses, design for reliability, and failure analyses for lead-free solder joints. Uniquely, the content not only addresses electronic manufacturing services (EMS) on the second-level interconnects, but also packaging assembly on the first-level interconnects and the semiconductor back-end on the 3D IC integration interconnects. Thus, the book offers an indispensable resource for the complete food chain of electronics products.
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Assembly and Reliability of Lead-Free Solder Joints - John H. Lau
© The Editor(s) (if applicable) and The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2020
J. H. Lau, N.-C. LeeAssembly and Reliability of Lead-Free Solder Jointshttps://doi.org/10.1007/978-981-15-3920-6_1
1. Solder Joints in PCB Assembly and Semiconductor Packaging
John H. Lau¹ and Ning-Cheng Lee²
(1)
Unimicron Technology Corporation, Taoyuan, Taiwan
(2)
Indium Corporation (United States), Clinton, NY, USA
1.1 Introduction
Assembly and reliability of lead-freesolder joints are very important topics in electronic manufacturing. There are many books [1–69] and papers [70–315] written on them. In this book, the assembly of lead-free solder joints such as prevailing lead-free materials, soldering processes, advanced specialty flux design, and characterization of lead-free solder joints will be discussed, respectively in Chaps. 2–5. The reliability of lead-free solder joints such as reliability testing and data analyses, design for reliability, and failure analyses of lead-free solder joints will be discussed, respectively in Chaps. 6–8. The special features of this book are the materials covered are not only for electronic manufacturing services (EMS) on the second-level interconnects, but also for packaging assembly on the first-level interconnects and for the semiconductor back-end on the 2.5D and 3D IC integration interconnects as shown in Fig. 1.1. The solder joints in various plated-through hole (PTH ) and surface mount technology (SMT) printed circuit board (PCB) assemblies, and semiconductor packages will be discussed in this chapter.
../images/495286_1_En_1_Chapter/495286_1_En_1_Fig1_HTML.pngFig. 1.1
Solder joints in single chip and multichip (heterogeneous integration) packaging
1.2 Solder Joints in Conventional PTH Assemblies
The solder joints in duel in-line package (DIP) and pin-grid array (PGA) PCB assembly will be briefly discussed in this section.
1.2.1 Duel In-Line Package (DIP)
Figure 1.2 shows the top-view and bottom-view of a DIP and its PCB assembly. It can be seen that the leads are soldered (for example, by hand or wave soldering) through the holes on the PCB . The pitch of DIP is 2.54 mm.
../images/495286_1_En_1_Chapter/495286_1_En_1_Fig2_HTML.pngFig. 1.2
Solder joints in DIP PCB assembly
1.2.2 Pin-Grid Array (PGA)
Figure 1.3 shows the top-view and bottom-view of a PGA and its PCB assembly. It can be seen that leads (pins) are soldered by wave soldering through the holes on the PCB . The pins are commonly spaced 2.54 mm apart. The solder joints are much reliable than those of the SMT components.
../images/495286_1_En_1_Chapter/495286_1_En_1_Fig3_HTML.pngFig. 1.3
Solder joints in PGA PCB assembly
1.3 Solder Joints in Conventional SMT Assemblies
The solder joints in ceramic capacitor, plastic leaded chip carrier (PLCC), small outline integrated circuit (SOIC), thin small outline package (TSOP), plastic quad flat pack (PQFP), thin quad flat pack (TQFP), plastic ball grid array (PBGA), ceramic ball grid array (CBGA), ceramic column grid array (CCGA), and quad-flat no-lead (QFN) PCB assemblies are briefly mentioned.
1.3.1 Ceramic Capacitor
Figure 1.4 shows a ceramic capacitor and its PCB assembly. Today, the smallest size of capacitor (0.25 mm × 0.125 mm × 0.125 mm) is developed by, e.g., Murata and Kyocera called monolithic ceramic capacitor or multilayer ceramic capacitor.
../images/495286_1_En_1_Chapter/495286_1_En_1_Fig4_HTML.jpgFig. 1.4
Solder joints in Ceramic capacitor PCB assembly
1.3.2 Plastic Leaded Chip Carrier (PLCC)
Figure 1.5 shows the top-view and bottom-view of a PLCC and its PCB assembly. The special feature of the package is its J-leads and the J-lead solder joints. The standard J-lead pitch of the PLCC is 1.27 mm.
../images/495286_1_En_1_Chapter/495286_1_En_1_Fig5_HTML.pngFig. 1.5
Solder joints in PLCC PCB assembly
1.3.3 Small Outline Integrated Circuit (SOIC) and Thin Small Outline Package (TSOP)
Figure 1.6 shows the SOIC and TSOP and their PCB assembly. The special feature of these packages is their gull-wing leads and their solder joints. The pitch of the gull-wing leads for the SOIC is 1.27 mm and for the TSOP is 0.65 mm.
../images/495286_1_En_1_Chapter/495286_1_En_1_Fig6_HTML.pngFig. 1.6
Solder joints in SOIC and TSOP PCB assembly
1.3.4 Plastic Quad Flat Pack (PQFP)
Figure 1.7 shows the PQFP and its PCB assembly. Again, the special feature of this package is its gull-wing leads and solder joints. Thin quad flat pack (TQFP) is very similar to PQFP except TQFP is much thinner. The pitch of PQFP /TQFP can go down to 0.4 mm.
../images/495286_1_En_1_Chapter/495286_1_En_1_Fig7_HTML.pngFig. 1.7
Solder joints in PQFP PCB assembly
1.3.5 Plastic Ball Grid Array (PBGA)
Figure 1.8 shows the PBGA and its PCB assembly. The special feature of this package is the package substrate and array solder balls. Unlike PLCC , SOIC , TSOP , PQFP , and TQFP solder joints which can be inspected by microscopes alone, PBGA solder joints are underneath the package substrate and must be inspected by an X-ray machine. The pitch of the solder joints, right now, can go down to 0.35 mm.
../images/495286_1_En_1_Chapter/495286_1_En_1_Fig8_HTML.pngFig. 1.8
Solder joints in PBGA PCB assembly
1.3.6 Ceramic Ball Grid Array (CBGA)
Figure 1.9 shows the CBGA and its PCB assembly. It can be seen from the failed sample (after thermal cycling test) that the crack of the solder joints occurs near the interface between the ceramic package and the bulk solder.
../images/495286_1_En_1_Chapter/495286_1_En_1_Fig9_HTML.pngFig. 1.9
Solder joints in CBGA PCB assembly
1.3.7 Ceramic Column Grid Array (CCGA)
Figure 1.10 shows the CCGA and its PCB assembly. It can be seen from the failed sample (after thermal cycling test) that the crack of the solder joints occurs near the Sn90Pb solder column and the lead-free solder paste fillet.
../images/495286_1_En_1_Chapter/495286_1_En_1_Fig10_HTML.pngFig. 1.10
Solder joints in CCGA PCB assembly
1.3.8 Quad-Flat No-Lead (QFN)
Figure 1.11 shows the top-view and bottom-view of a QFN and its PCB assembly. The special feature of this package is there are no leads and its solder joints. The standard QFN pad pitch is 0.5 mm.
../images/495286_1_En_1_Chapter/495286_1_En_1_Fig11_HTML.pngFig. 1.11
Solder joints in QFN PCB assembly
1.4 Solder Joints in Flip Chip Assemblies
The first flip chip assembly was proposed by IBM [35] more than 50 years ago. Since then, the flip chip technology has been progressed to finer pitch, smaller bump size, and chip-to-chip applications.
1.4.1 The First Flip Chip Assembly
The flip chip technology was introduced by IBM in the early 1960s for their solid logic technology, which became the logical foundation of the IBM System/360 computer line [70]. Figure 1.12a shows the first IBM flip chip with three terminal transistors, which are Ni/Au plated Cu balls embedded in a SnPb solder bump on the three I/O pads of transistor. A CrCuAu adhesion/seed layer is deposited between the AlSi contact pads on the Si chip and the solder bump. Figure 1.12b shows the first IBM flip chip assembly (three chips) on a ceramic substrate. As the inputs/outputs increase, the Cu ball is replaced by the C4 (controlled-collapse chip connection) bumps [71].
../images/495286_1_En_1_Chapter/495286_1_En_1_Fig12_HTML.pngFig. 1.12
IBM’s first flip chip assembly
1.4.2 Wafer Bumping—C4 Bumps
Wafer bumping is the mother of flip chip technology. There are many ways to bump the wafer [33]. In this book, only the electroplating or electrochemical deposition (ECD) method is briefly mentioned.
In general, the pad size is equal to 100 μm and the target bump height is equal to 100 μm. After redefining the passivation opening (usually it is not required), either Ti or TiW (0.1–0.2 μm) are sputtered over the entire surface of the wafer first, followed by 0.3–0.8 μm of Cu. Ti–Cu and TiW–Cu are called under bump metallurgy (UBM). In order to obtain 100 μm bump height, a 40 μm layer of resist is then overlaid on the Ti–Cu or TiW–Cu and a solder bump mask is used to define (ultraviolet exposure) the bump pattern as shown in steps #1–4 in Fig. 1.13. The opening in the resist is 7–10 μm wider than the pad opening in the passivation layer. A layer of Cu (≥5 μm) is then plated over the UBM , followed by electroplating the solder. This is done by applying a static or pulsed current through the plating bath with the wafer as the cathode. In order to plate enough solder to achieve the target (100 μm), the solder is plated over the resist coating by about 15 μm to form a mushroom shape. The resist is then stripped off and the Ti–Cu or TiW–Cu is removed with a hydrogen peroxide or plasma etching. The wafer is then reflowed with flux , which creates smooth truncated spherical solder C4 bumps Fig. 1.14a, due to surface tension as shown in steps #5–8 on the upper right-hand side of Fig. 1.13.
../images/495286_1_En_1_Chapter/495286_1_En_1_Fig13_HTML.pngFig. 1.13
Wafer bumping: C4 versus C2
../images/495286_1_En_1_Chapter/495286_1_En_1_Fig14_HTML.jpgFig. 1.14
(a) C4 Solder bumps and (b) C2 Cu-pillar with solder cap
1.4.3 Wafer Bumping—C2 Bumps
Because of higher pin-count and tighter pitch (smaller spacing between pads), there is a possibility of shorting the adjacent solder C4 bumps. Wire interconnects [72] and Cu-pillar with solder cap [73–75] can be a solution. The fabrication process is basically the same as that of the C4 bumps except electroplating the Cu instead of solder as shown in step #5 on the lower right-hand side of Fig. 1.13. It is followed by electroplating the solder cap and then reflowing the solder with flux . Figure 1.14b shows the chip connection (C2) Cu-pillar with solder cap bump.
1.4.4 C4 Versus C2 Bumps
In general, because the solder volume is very small compared with the C4 bump, the surface tension is not enough to perform the self-alignment of the C2 (Cu pillar with the solder cap) bump. Besides being able to handle finer pitch and higher pin-count, C2 bumps also provide better thermal and electrical performances than C4 bumps. This is because the thermal conductivity (W/m K) and electrical resistivity (μΩ m) of Cu (400 and 0.0172) are superior than those (55–60 and 0.12–0.14) of solder.
1.4.5 Solder Joints in Flip Chip Examples
Figure 1.15 [228] shows a flip chip assembly on a bismaleimide triazine (BT) package substrate with via-in-pad (VIP), which is soldered onto a PCB . The chip sizes are 5.334 mm × 3.662 mm. The package substrate is 0.164 mm thick. There are two sets of solder joints, namely, the solder joints between the chip and the substrate and the solder joints between the substrate and PCB .
../images/495286_1_En_1_Chapter/495286_1_En_1_Fig15_HTML.pngFig. 1.15
Solder joints in a flip chip PCB assembly
Figure 1.16 shows the flip chip substrate assembly with solder bump on leads (BOLs) [154]. It can be seen that the chip is with Cu-pillar + SnAg solder cap. The traces (leads) width is 25 μm. They are BOLs and on a 160 μm pitch.
../images/495286_1_En_1_Chapter/495286_1_En_1_Fig16_HTML.pngFig. 1.16
Solder joints in a BOL flip chip assembly
Figure 1.17 shows a flip chip substrate assembly with underfill [76]. The solder joints between the chip and package substrate can be clearly seen.
../images/495286_1_En_1_Chapter/495286_1_En_1_Fig17_HTML.pngFig. 1.17
Solder joints in a flip chip in PBGA assembly
Figure 1.18 shows a flip chip assembly [77]. The bump (Cu-pillar with Ni + solder cap) on the chip and the Si-interposer is the same. The solder joints are formed by thermal compression bonding of the chip to Si-interposer.
../images/495286_1_En_1_Chapter/495286_1_En_1_Fig18_HTML.pngFig. 1.18
Micro solder joints (Cu-pillar with solder cap) in a flip chip on Si-interposer assembly
Figure 1.19 shows a flip chip assembly [177]. The UBM, Fig. 1.19a, on the Si carrier is electroless nickel (Ni) and immersion gold (Au) (ENIG ). The solder bump, Fig. 1.19b, c, on the Si chip is Cu-pillar with Sn. The solder joints, Fig. 1.19d, e, are formed by thermal compression bonding of the chip and carrier.
../images/495286_1_En_1_Chapter/495286_1_En_1_Fig19_HTML.pngFig. 1.19
Micro solder joints (Cu-pillar with solder cap + ENIG UBM) in a flip chip assembly. (a) ENIG UBM. (b) CuSu solder bump on chip. (c) SEM/FIB of the CuSn solder bump. (d) Chip on Si-carrier assembly. (e) Enlarge the corner solder joint.
Figure 1.20 shows a flip chip face-to-face assembly [192]. The mother chip is bonded to the daughter chip by thermal compression bonding. The ENIG UBM is on the mother chip and the Cu-pillar with AuSn solder cap bump is on the daughter chip.
../images/495286_1_En_1_Chapter/495286_1_En_1_Fig20_HTML.pngFig. 1.20
Micro solder joints in a flip chip (face-to-face) assembly
Figure 1.21 shows a flip chip face-to-face bonding [157]. The top chip and bottom chip are connected through the Cu-pillar and the solder joints on an interposer. There are also solder joints between the interposer and the package substrate, and the package substrate and the PCB .
../images/495286_1_En_1_Chapter/495286_1_En_1_Fig21_HTML.pngFig. 1.21
Solder joints in a flip chip (face-to-face) on an interposer assembly
Figure 1.22 shows a flip chip face-to-face assembly [78]. The top chip and the bottom chip are connected through a through-silicon via (TSV )-interposer. The UBM on the TSV-interposer is Cu-pillar + Ni. The bump on the chip is Cu-pillar + Sn cap. The solder joints are shown in Fig. 1.22.
../images/495286_1_En_1_Chapter/495286_1_En_1_Fig22_HTML.pngFig. 1.22
Micro solder joints in a flip chip (face-to-face) on an interposer assembly
Figure 1.23 shows a flip chip face-to-face assembly [79]. The top chips and the bottom chip are with C4 bumps and are mass reflowed on a TSV-interposer. The solder joints between the chips and the TSV-interposer, and between the TSV-interposer and the package substrate can be clearly seen.
../images/495286_1_En_1_Chapter/495286_1_En_1_Fig23_HTML.pngFig. 1.23
Solder joints in a flip chip (face-to-face) assembly
1.5 Solder Joints in Fan-In Wafer-Level Packaging
The unique feature of most fan-in wafer-level packaging is the use of a metal (usually Cu) RDL to redistribute the fine-pitch peripheral-arrayed pads on the chips of a wafer to much larger-pitch area-arrayed pads with much taller and bigger solder joints as shown in Fig. 1.24. The packages made from the fan-in wafer-level packaging technology are called wafer-level chip scale packages (WLCSPs) [215, 217]. Thus, with WLCSPs , the demand on the PCB is relaxed and the underfill may not be necessary. From the system houses’ point of view, WLCSPs is just like another solder-bumped flip chip
SMT component, except for the followings: (a) the solder bumps of WLCSP are much taller and bigger; (b) the PCB assembly of WLCSP is more robust; and (c) they are so happy that they may not have to struggle with the underfill encapsulant. Figure 1.25 shows a 6.5 mm × 6.5 mm WLCSP on PCB without underfill .
Fig. 1.24
Solder joints in a fan-in wafer-level chip scale package (WLCSP)
../images/495286_1_En_1_Chapter/495286_1_En_1_Fig25_HTML.pngFig. 1.25
Solder joints in a fan-in WLCSP
1.6 Solder Joints in Fan-Out Wafer-Level Packaging
Figure 1.26a schematically shows the cross sections of a typical fan-out wafer-level packaging (FOWLP) assembly. The manufacturing process flow is very simple [80, 81, 138–140]. First, the device wafer is tested for known-good dies (KGDs) and then singulated into individual chips. This is followed by picking up the KGDs and placing them face-down on a temporary carrier that can be round (wafer) or rectangular (panel) with a double-sided thermal release tape. Then, the reconfigured carrier is over-molded using the compression molding method with epoxy molding compound (EMC ) before removing the carrier and the double-sided tape. Next comes building the RDLs for signals, power, and grounds from the pads. Finally, solder balls are mounted and the whole molding (with KGDs , RDLs, and solder balls) is diced into individual packages. Figure 1.26b shows the image of cross-sectional RDL while Fig. 1.26c shows the image of longitudinal RDL . This classical process is also called embedded wafer level ball grid array (eWLB) technology [80, 81].
../images/495286_1_En_1_Chapter/495286_1_En_1_Fig26_HTML.pngFig. 1.26
Solder joints in a fan-out wafer-level packaging (FOWLP)
HTC shipped (2013) their smartphones with this FOWLP technology. Figure 1.27 shows the cross-section image of their application processor and modem chip side-by-side with SMT equipment. There are two RDLs with line width and spacing = 20 μm. There are 230 solder joints between the fan-out package and PCB .
../images/495286_1_En_1_Chapter/495286_1_En_1_Fig27_HTML.pngFig. 1.27
Solder joints in FOWLP shipped by HTC in 2013 (two chips side-by-side by SMT )
Instead of chip face-down, Fig. 1.28 shows a FOWLP with chip face-up process [141, 143]. The chip size is 10 mm × 10 mm and there are three RDLs. The package size is 13.42 mm × 13.42 mm and there are 908 SnAgCu solder joints on 0.4 mm pitch.
../images/495286_1_En_1_Chapter/495286_1_En_1_Fig28_HTML.pngFig. 1.28
Solder joints in FOWLP of a very large chip with three RDLs
Figure 1.29 shows a face-down FOWLP [82]. The solder joints are subjected to thermal cycling test. The failure location of the solder joints is at the package corner and the major failure mode is the cracking near the interface between the package and the bulk solder.
../images/495286_1_En_1_Chapter/495286_1_En_1_Fig29_HTML.jpgFig. 1.29
Solder joints in FOWLP for power device
Figure 1.30 shows a heterogeneous integration of two fan-out chips (chip1 and chip2) and one solder bumped flip chip (chip3) [81]. There are two groups of solder joints. One is between chip3 and the RDLs in the upper molding and the other is between the RDLs in the lower molding and PCB .
../images/495286_1_En_1_Chapter/495286_1_En_1_Fig30_HTML.pngFig. 1.30
Solder joints in FOWLP with multiple chips
Figure 1.31 shows a heterogeneous integration of four chips and four capacitors with FOWLP [135–140]. The gap between the large chip and the small chip is only 100 μm. The package size is 10 mm × 10 mm and there are 405 solder joints on 0.4 mm pitch.
../images/495286_1_En_1_Chapter/495286_1_En_1_Fig31_HTML.pngFig. 1.31
Solder joints in FOWLP of four chips and four capacitors
Figure 1.32a shows a heterogeneous integration of two set of chips with FOWLP [83]. These sets of chips are the application processor and the memory chip (or cube). Samsung showed that with this structure, the electrical performance is very good as shown in Fig. 1.32b.
../images/495286_1_En_1_Chapter/495286_1_En_1_Fig32_HTML.jpgFig. 1.32
Solder joints in FOWLP with application processor and memory side-by-side (Samsung)
1.7 Solder Joints in Package-On-Package
There are at least two kinds of package-on-package (PoP) for application processor. One is with solder bumped flip chip and the other is with fan-out packaging.
1.7.1 PoP with Solder Bumped Flip Chip
Figure 1.33 shows the PoP from Qualcomm and manufactured by Amkor [84]. The application processor is solder bumped flip chip in the bottom package. Figure 1.34 shows the PoP from Apple. Again, the application processor (A9) is solder bumped flip chip on a 2-2-2 build-up package substrate in the bottom package.
../images/495286_1_En_1_Chapter/495286_1_En_1_Fig33_HTML.pngFig. 1.33
Solder joints in PoP for solder bumped flip chip application processor and memory (Qualcomm)
../images/495286_1_En_1_Chapter/495286_1_En_1_Fig34_HTML.pngFig. 1.34
Solder joints in PoP for solder bumped flip chip application processor and memory (Apple)
1.7.2 PoP with Fan-Out Packaging
Figure 1.35 shows the PoP for the smartphones from Apple and manufactured by TSMC [85]. It can be seen that the application processor (A12) is packaged by TSMC’s integrated fan-out (InFO) technology with RDLs. The PoP package is SMT soldered on a substrate-like PCB .
../images/495286_1_En_1_Chapter/495286_1_En_1_Fig35_HTML.jpgFig. 1.35
Solder joints in PoP for application processor (InFO ) and memory (Apple)
Figure 1.36 shows the PoP for the smart watches from Samsung. It can be seen that the application processor and power management IC (PMIC) are packaged by their fan-out packaging technology. The PoP package is then SMT on a PCB .
../images/495286_1_En_1_Chapter/495286_1_En_1_Fig36_HTML.pngFig. 1.36
Solder joints in PoP for application processor + PMIC (fan-out) and memory (Samsung)
1.8 Solder Joints in 2D IC Integration
There are many kinds of 2D IC integration. For examples, the 2D IC fan-out integration and the 2D flip chip IC integration.
1.8.1 2D IC Fan-Out Integration
Figure 1.37 shows a 2D IC fan-out integration [135–140]. It can be seen that there are four chips side-by-side in a 2D format. These four chips are packaged by a FOWLP technology. The solder joints are between the RDLs of the fan-out package and the PCB .
../images/495286_1_En_1_Chapter/495286_1_En_1_Fig37_HTML.pngFig. 1.37
Solder joint in four chips (FOWLP ) 2D IC integration
1.8.2 2D IC Flip Chip Integration
Figure 1.38 shows a 2D IC flip chip integration. It can be seen that there are two chips side-by-side in a 2D format. These two chips are packaged by a flip chip technology on a build-up organic package substrate and then soldered to a PCB. The solder joints are between the chips and the substrate, and between the substrate and PCB .
../images/495286_1_En_1_Chapter/495286_1_En_1_Fig38_HTML.pngFig. 1.38
Solder joints in two flip chips 2D IC integration
1.9 Solder Joints in 2.1D IC Integration
Figure 1.39 shows a 2.1D IC integration by Shinko [86, 87]. It can be seen that on top of the build-up layer of the organic package substrate, there are thin-film layers. These thin-film layers are with fine line width and spacing (down to 2 μm) RDLs. An example of the application of 2.1D IC integration is shown in Fig. 1.40 [87]. It can be seen that the micro solder bump, micro pad, and micro solder joints are properly done [87].
../images/495286_1_En_1_Chapter/495286_1_En_1_Fig39_HTML.pngFig. 1.39
Micro solder joints in Shinko’s 2.1D IC integration
../images/495286_1_En_1_Chapter/495286_1_En_1_Fig40_HTML.jpgFig. 1.40
Micro bumps and pads and solder joints in Shinko’s 2.1D IC integration
1.10 Solder Joints in 2.5D IC Integration
In the past few years, because of the very high-performance, high-density, high I/Os, and ultrafine pitch requirements such as the sliced field programmable gate array (FPGA ), even a 12 build-up layers (6-2-6) package substrate is not enough to support the chips and a TSV interposer is needed [27, 28].
1.10.1 CoWoS
For example, Fig. 1.41 shows the Xilinx/TSMC’s FPGA chip on wafer on substrate (CoWoS) [88]. It can be seen that the TSV (10 μm-diameter) interposer (100 μm-deep) has four top RDLs: three Cu damascene layers and one aluminum layer. The 10,000+ of lateral interconnections between FPGA chips are connected mainly by the 0.4 μm-pitch (minimum) RDLs of the interposer. The minimum thickness of the RDLs and passivation is 1 μm. Each FPGA has more than 50,000 microbumps (200,000+ micro bumps on the interposer) at 45 μm pitch as shown in Fig. 1.41. The CoWoS also called the 2.5D IC integration.
../images/495286_1_En_1_Chapter/495286_1_En_1_Fig41_HTML.jpgFig. 1.41
Micro solder joints in Xilinx/TSMC’s 2.5D IC integration
1.10.2 Stacking of 2.5D IC Integration
Mobile electronic products demand multifunctional module comprising digital, radio frequency (RF) and memory functions. TSV technology provides a means of implementing complex, multi-functional integration with a higher packing density for a heterogeneous integration. Figure 1.42 shows a stack of two 2.5D IC integrations [191]. The package consists of two stacks assembled with three chip sets. The module dimensions are 12 mm × 12 mm × 1.3 mm. The silicon carrier size is 12 mm × 12 mm with 168 peripherally populated vias. Carrier 1 is assembled with a 5 mm × 5 mm flip-chip. The carrier 2 is assembled with a 5 mm × 5 mm flip-chip and two 3 mm × 6 mm wirebond-chip. The carrier 2 is over molded to protect the wire bonds. The silicon carrier has been fabricated with two metal layers with SiO2 as dielectric/passivation layer. Electrical connections through the carrier are formed by TSVs.
../images/495286_1_En_1_Chapter/495286_1_En_1_Fig42_HTML.pngFig. 1.42
Micro solder joints in IME’s stacked 2.5D IC integration
1.11 Solder Joints in 3D IC Integration
There are many 3D IC integrations [27, 28]. In this book, the 3D IC integration is defined by the chips with TSVs stacked with micro solder joints.
1.11.1 The First HVM 3D IC Integration
Figure 1.43 shows the first (August 27, 2014) high volume manufacturing of 3D IC integration by Samsung. It is the industry’s first TSV-based double data rate 4 (DDR4) dynamic random-access memory (DRAM). The 64GB DDR4 DRAM module consists of 36 DDR4 DRAM chips, each of which consists of four 4-gigabit (Gb) DDR4 DRAM dies. It performs twice as fast as a module that uses wire bonding packaging, while consuming approximately half the power. On November 26, 2015, Samsung produced the 128GB RDIMM (registered dual inline memory module).
../images/495286_1_En_1_Chapter/495286_1_En_1_Fig43_HTML.jpgFig. 1.43
Micro solder joints in Samsung’s 3D IC integration
1.11.2 A Multichip 3D IC Integration
Figure 1.44 shows a heterogeneous integration of various chips and a stack of four chips on a TSV interposer [181]. It can be seen that the interposer (with 15 μm-vias) supports four memory chips (with 10 μm-vias) stacked, one thermal chip, and one mechanical chip. It is over molded for pick-and-place purpose as well as protecting the chips from harsh environments. There are RDLs on both top and bottom sides of the interposer. Also, stress sensors are implanted on the top side and integrated passive devices (IPDs ) are fabricated through the thickness (100 μm) of the interposer (12.3 mm × 12.2 mm). This test vehicle can be degenerated to the case of: (a) wide I/O DRAM if there are not mechanical and thermal chips and the interposer is an ASIC chip; (b) wide I/O memory if there is not the memory-chip stacking nor the TSVs in the mechanical/thermal chips and the interposer is either an application specific IC (ASIC ) or microprocessor; and (c) wide I/O interface if there is not the memory-chip stacking and there is not any TSV in the thermal/mechanical chips.
../images/495286_1_En_1_Chapter/495286_1_En_1_Fig44_HTML.jpgFig. 1.44
Micro solder joints in ITRI’s 3D IC integration
1.11.3 HBM and HBM2
The memory stacks in Figs. 1.43 and 1.44 are for capacity but not for wide bandwidth. The high bandwidth memory (HBM) is designed for higher bandwidth and less power. The HBM has been adopted by JEDEC as an industry standard in October 2013 and manufactured by Hynix and Samsung. The HBM2 has been accepted by JEDEC in January 2016 and manufactured by Samsung. The cross-section of Samsung’s new 4GB (HBM ) is shown in Fig. 1.45a and 8GB (HBM2 ) is shown in Fig. 1.45b. The HBM DRAM chips are several times faster than the previous best DRAM chips available on the market. The DRAM chips are with TSVs and connected through micro solder joints as shown in Fig. 1.45.
../images/495286_1_En_1_Chapter/495286_1_En_1_Fig45_HTML.pngFig. 1.45
Micro solder joints in Samsung’s (a) HBM and (b) HBM2
1.11.4 AMD’s 3D IC Integration
Figure 1.46 shows AMD’s Radeon R9 Fury X graphic processor unit (GPU) shipped in the second-half of 2015. The GPU is built on TSMC’s 28 nm process technology and is supported by four HBM cubes manufactured by Hynix. Each HBM consists of four DRAMs with C2 bumps and a logic base with TSVs straight through them. Each DRAM chip has >1000 TSVs. The GPU and HBM cubes are on top of a TSV interposer (28 mm × 35 mm), which is fabricated by UMC with a 64 nm process technology. The final assembly of the TSV interposer (with C4 bumps) on a 4-2-4 organic package substrate (fabricated by Ibiden) is by ASE.
../images/495286_1_En_1_Chapter/495286_1_En_1_Fig46_HTML.pngFig. 1.46
Micro solder joints in AMD’s 3D IC integration
1.11.5 NVidia’s 3D IC Integration
Figure 1.47 shows NVidia’s Pascal 100 GPU, which shipped in the second-half of 2016. The GPU is built on TSMC’s 16 nm process technology and is supported by four HBM2 (16 GB) fabricated by Samsung. Each HBM2 consists of four DRAMs with C2 bumps and a base logic die with TSVs straight through them. Each DRAM chip has >1000 TSVs. The GPU and HBM2s are on top of a TSV interposer (1200 mm²) called CoWoS-2 [92], which is fabricated by TSMC with a 64 nm process technology. The TSV interposer is attached to a 5-2-5 organic package substrate with C4 bumps. Figure 1.48 shows the micro solder joints and Cu-C4 solder joints.
../images/495286_1_En_1_Chapter/495286_1_En_1_Fig47_HTML.pngFig. 1.47
Micro solder joints in NVidia (P100) 3D IC integration
../images/495286_1_En_1_Chapter/495286_1_En_1_Fig48_HTML.jpgFig. 1.48
Micro solder joints in NVidia’s 3D IC integration
1.11.6 Xilinx’s 3D IC Integration
Figure 1.49 shows Xilinx’s FPGA and HBM3D IC integration [89]. It can be seen that there are micro solder joints between the FPGA and the TSV-interposer. There are also Cu-C4 solder joints between the Si-interposer and the package substrate.
../images/495286_1_En_1_Chapter/495286_1_En_1_Fig49_HTML.pngFig. 1.49
Micro solder joints in Xilinx/TSMC’s 3D IC integration
1.11.7 Intel/Micron’s 3D IC Integration
Figure 1.50 shows Intel’s Knights Landing central processing unit (CPU) with Micron’s HMC (hybrid memory cube), which have been shipping to Intel’s favorite customers since the second-half of 2016. It can be seen that the 72-core processor is supported by eight multi-channel DRAMs (MCDRAM) based on Micron’s HMC technology. Each HMC consists of four DRAMs and a logic controller (all with TSVs), and each DRAM has >2000 TSVs with C2 bumps. The DRAM + logic controller stack is attached to an organic package substrate.
../images/495286_1_En_1_Chapter/495286_1_En_1_Fig50_HTML.pngFig. 1.50
Micro solder joints in Intel/Micron’s 3D IC integration
1.11.8 Cisco’s 3D/2.3D IC Integration
Figure 1.51 shows a 3D IC integration designed and manufactured with a large organic interposer with fine-pitch and fine-line interconnections by Cisco [97]. The organic interposer has a size of 38 mm × 30 mm × 0.4 mm. (Because of the organic interposer, it is also called 2.3D IC integration.) The minimum line width, spacing, and thickness of the front side and back side of the organic interposer are the same and are, respectively, 6 μm, 6 μm, and 10 μm. It is a ten-layer high density organic interposer (substrate) and the via size is 20 μm. A high-performance application-specific IC (ASIC ) die measured at 19.1 mm × 24 mm × 0.75 mm is attached on top of the organic interposer along with four HBM DRAM die stacks. (Because of the HBM , that’s why it is also called 3D IC integration.) The 3D HBM die stack with a size of 5.5 mm × 7.7 mm × 0.48 mm includes one base buffer die and four DRAM core dice that are interconnected with TSVs and fine-pitch micro-pillars with solder cap bumps. The pad size and pitch of the front side of the organic interposer are 30 μm and 55 μm, respectively.
../images/495286_1_En_1_Chapter/495286_1_En_1_Fig51_HTML.jpgFig. 1.51
Micro solder joints in Cisco’s 2.3D/3D IC integration
1.12 Solder Joints in MEMS
Figure 1.52 shows the 3D IC integration of the Micro-electro-mechanical systems (MEMS) device and the ASIC provided by Analog Devices. It is assembled by chip (MEMS ) to (ASIC ) wafer bonding. The interconnection between the MEMS and the ASIC is by RDLs and TSVs. The solder bump will become solder joint as soon as the MEMS is SMT to the PCB .
../images/495286_1_En_1_Chapter/495286_1_En_1_Fig52_HTML.pngFig. 1.52
Solder joints in MEMS + ASICheterogeneous integration system
Figure 1.53 shows a MEMS package based on interposer wafer developed by IZM [95]. It can be seen that the MEMS device is attached to a TSV-interposer wafer with Cu-filled TSVs and RDLs, and is hermetic sealed with a cap wafer with cavity. This is a 2.5D MEMS and IC integration. The micro solder joints are connecting the MEMS device to the TSV-interposer.
../images/495286_1_En_1_Chapter/495286_1_En_1_Fig53_HTML.pngFig. 1.53
Solder joints in a MEMS package
Figure 1.54 shows the 3D IC integration of the MEMS device on ASIC and is hermetic sealed by a silicon cap developed by IME [30]. It is assembled by chip (MEMS ) to (ASIC ) wafer bonding and (cap) wafer to (ASIC with MEMS ) wafer bonding.
../images/495286_1_En_1_Chapter/495286_1_En_1_Fig54_HTML.pngFig. 1.54
Solder joints in a MEMS + ASIC system
1.13 Solder Joints in LED
Figure 1.55 schematically shows a wafer level packaging with Light-emitting diode (LED) devices in the cavities of a Si substrate developed by HKUST [93, 94]. It can be seen that the Si-substrate has cavities on its top side to house the LED devices and TSVs to connect the LEDs to the RDLs on its bottom side. The Si-substrate is covered by a glass with yellow phosphor. It can be seen that: (a) the LED device is attached on the bottom of the cavity of the Si-substrate, (b) the glass is bonded on the top of the Si-substrate, (c) the LED pads are connected to the RDL through the TSV with contactor size of about 20 μm, and (d) the encapsulation separates the Si-substrate from the RDL , which prevents electrical shortage between the cathode and the anode.
../images/495286_1_En_1_Chapter/495286_1_En_1_Fig55_HTML.pngFig. 1.55
Solder joints in a LED system
1.14 Solder Joints in CIS
Figure 1.56 shows a 3D complementary metal-oxide-semiconductor (CMOS) image sensor (CIS ) and IC integration developed by STMicroelectronics and presented in [96]. It consists of the CIS , coprocessor IC, and glass carrier. The I/O count of the CIS is 80 and that of the IC is 164. The size of the CIS and the coprocessor is not the same. The dimensions of the CIS are 5 mm × 4.4 mm and of the IC are 3.4 mm × 3.5 mm. The IC and the CIS are bonded face-to-back, as shown in Fig. 1.56. The interconnects of the CIS and IC are Cu-pillar with SnAg solder cap. The TSVs are in the CIS , which are connected to the substrate with solder bump and RDLs.
../images/495286_1_En_1_Chapter/495286_1_En_1_Fig56_HTML.pngFig. 1.56
Micro solder joints in a CIS system
1.15 Solder Joints in VCSEL System
Figure 1.57 shows a single-channel OECB (opto-electrical circuit board) with embedded waveguide using traditional PCB manufacturing process [172]. The OECB is made up of four electrical layers and one optical layer embedded below a 60-μm-thick BT substrate. Two optical vias with 100 μm diameter are formed to guide the optical beam from VCSEL (vertical-cavity surface-emitting laser) to the 45° mirror coupler. Likewise, optical beam exiting the waveguide is diverted from the 45° mirror coupler through the optical via and received by the photodetector. A 10 cm-long embedded polymer waveguide consists of a 70 μm × 70 μm core and a 15 μm thick top and bottom cladding. Two 45° mirror couplers are formed at both corners of the waveguide by using 90° diamond dicing blade. These mirrors convert optical beam emitted from VCSEL in the vertical path to the planar direction and into the waveguide.
../images/495286_1_En_1_Chapter/495286_1_En_1_Fig57_HTML.pngFig. 1.57
Solder joints in a VCSEL system
Figure 1.58 shows an embedded hybrid 3D IC integration for opto-electronic interconnects