MKCE ECE MID SEMESTER Microprocessor and Its Application-Answer Key Date: 22.0 .20!" Ti#e: $."0a# !2.

."0 p# %ear&Se#: III&' Ma(.Mar)s:!00 *ART A +!0 ( 2 , 20- ANSWER ALL THE QUESTIONS !- .ist t/ree cycles o0 212 DMA Controller.+2 DMA Read cycle DMA 3rite cycle and DMA 'eri0y cycle 2- Distin45is/ 6etween t/e #e#ories #apped I&7 and perip/eral I&78 +eac/ point !&2S.: 97 Me#ory Mapped I&7 *erip/eral I&7 ! !:-6it de;ice address -6it de;ice address Data trans0er 6etween any Data is trans0er only 2 4eneral-p5rpose re4ister and 6etween acc5#5lator and I&7 I.7 port port. T/e #e#ory #ap +:<K- is T/e I&7 #ap is independent o0 t/e #e#ory #ap= 21: inp5t " s/ared 6etween I&7 de;ice de;ice and 21: o5tp5t de;ice can and syste# #e#ory. 6e connected < 1 More /ardware is re>5ired to decode !:-6it address Arit/#etic or lo4ic operation can 6e directly per0or#ed wit/ I&7 data .ess /ardware is re>5ired to decode -6it address Arit/#etic or lo4ical operation cannot 6e directly per0or#ed wit/ I&7 data

"- Di00erence 6etween two )ey loc)o5t and 9 )ey rollo;er #odes in 22$. <- 9a#e t/e si( #odes o0 operations o0 an 21" pro4ra##a6le inter;al ti#er. Eac/ o0 t/e t/ree co5nters o0 21" can 6e operated in one o0 t/e 0ollowin4 si( #odes o0 operation. !. Mode 0 +Interr5pt on ter#inal co5nt2. Mode ! +?ardware retri44era6le one -s/ot". Mode 2 +Rate 4enerator<. Mode " +S>5are wa;e 4enerator1. Mode < +So0tware tri44ered stro6e:. Mode 1 +?ardware tri44ered stro6e1- State 0eat5res o0 21!A @SART. It is @ni;ersal Sync/rono5s Async/rono5s Recei;er Trans#itter It /as 65ilt in 6a5d rate 4enerator It allows 05ll d5ple( trans#ission and reception It pro;ides error detection lo4ic

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is Instr5ction >5e5e in 0 : #icroprocessor 8 It is : 6ytes lon4 *art o0 A5s Inter0ace @nit To speed 5p t/e pro4ra# e(ec5tionB t/e AI@ 0etc/es si( instr5ctions a /ead o0 ti#e 0ro# t/e #e#ory. T/ese pre0etc/ed instr5ction 6ytes are /eld 0or e(ec5tion 5nit a 4ro5p o0 re4ister called Instr5ction C5e5e

2- Di00erent types o0 se4#ent re4ister a;aila6le in 0 :. T/ere are < se4#ent re4isters present in 0 :. T/ey are !. Code Se4#ent +CS - re4ister 2. Data Se4#ent +DS - re4ister ". Stac) Se4#ent +SS - re4ister <. E(tra Se4#ent +ES - re4ister - ?ow #any address lines are re>5ired to inter0ace KA #e#ory 8 KA , 2" D 2!0 , 2!" !" address lines are re>5ired to inter0ace KA #e#ory $- 3rite t/e 0la4s o0 0 :8 T/e 0 : /as nine 0la4s and t/ey are !. Carry Ela4 +CE:. 7;er0low Ela4 +7E2. *arity Ela4 +*E2. Trace Ela4 +TE". A5(iliary carry Ela4 +AE. Interr5pt Ela4 +IE<. Fero Ela4 +FE$. Direction Ela4 +DE1. Si4n Ela4 +SE!0-7peration per0or#ed 6y M9&MG and its pin n5#6er in 0 :. M9&MG "" pin 3/en /i4/ 0 : acts as Mini#5# #ode 3/en low 0 : acts as Ma(i#5# #ode *ART A ANSWER ALL THE QUESTIONS !!-a- i- E(plain in deatil a6o5t 22$+ H Aloc) Dia4ra#

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H Types o0 Display A;aila6le H Types o0 )eys a;aila6le H E(planation a6o5t all 6loc)s in t/e 6loc) dia4ra# ii- E(plain a6o5t DAC + +7R6- 3rite in detail a6o5t 21$ pro4ra##a6le interr5pt controller. +!:H Aloc) Dia4ra#

H E(planation a6o5t all 6loc)s in t/e 6loc) dia4ra# !2-a- E(plain a6o5t 212 in detail +!:H Aloc) Dia4ra#

H E(planation a6o5t all 6loc)s in t/e 6loc) dia4ra# +7R6- i- Draw and e(plain a " 6it A&D Con;erter wit/ its 6loc) dia4ra# +:ii- E(plain Control word 0or#at o0 211A 0or I&7 #ode wit/ its dia4ra# +!0-

H H H H

Aloc) Dia4ra# E(planation a6o5t all t/e ports a;aila6le. E(planation a6o5t t/e #odes o0 trans0er E(plain t/e control 3ord Re4ister

!"-a- E(plain in detail a6o5t 21" +!:+7R6-3rite in detail a6o5t C*@ Ma(i#5# Mode o0 0 :+!:-

!<-a- E(plain Arc/itect5re o0 0 : wit/ neat s)etc/ o0 its 6loc) dia4ra#.+!:-

+7R6- i- E(plain in detail a6o5t Ti#in4 dia4ra# 0or #e#ory write in #a(i#5# #ode o0 0 : + ii- Me#ory se4#entation and its types in 0 : + !1- a- E(plain a6o5t C*@ Mini#5# #ode o0 0 : +!:-

+7R6- i- E(plain Addressin4 #odes o0 0 : +!2ii- Mention t/e types o0 instr5ction set in 0 : and e(plain any one type in detail +<T/e entire 4ro5p o0 instr5ctions deter#ines w/at 05nctions t/e #icroprocessor can per0or# are called instr5ction set.

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